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Part ECAD Model Manufacturer Description Datasheet Download Buy Part
BD70522GUL BD70522GUL ECAD Model ROHM Semiconductor Ultra Low Iq Buck Converter For Low Power Applications
BD9P155MUF-C BD9P155MUF-C ECAD Model ROHM Semiconductor 3.5V to 40V Input, 5.5V Output, 1A Single 2.2MHz Buck DC/DC Converter For Automotive, VQFN20FV4040 Package
BD9P255MUF-C BD9P255MUF-C ECAD Model ROHM Semiconductor 3.5V to 40V Input, 5.5V Output, 2A Single 2.2MHz Buck DC/DC Converter For Automotive, VQFN20FV4040 Package
BD9P135MUF-C BD9P135MUF-C ECAD Model ROHM Semiconductor 3.5V to 40V Input, 3.3V Output, 1A Single 2.2MHz Buck DC/DC Converter For Automotive, VQFN20FV4040 Package
BD9P135EFV-C BD9P135EFV-C ECAD Model ROHM Semiconductor 3.5V to 40V Input, 3.3V Output, 1A Single 2.2MHz Buck DC/DC Converter For Automotive, HTSSOP-B20 Package
BD9P255EFV-C BD9P255EFV-C ECAD Model ROHM Semiconductor 3.5V to 40V Input, 5.5V Output, 2A Single 2.2MHz Buck DC/DC Converter For Automotive, HTSSOP-B20 Package

for PLL IC 565 Datasheets Context Search

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PLL IC 565

Abstract: for PLL IC 565 565 PLL pin diagram lock range of 565 PLL IC 0420 LOP pll 565 FO56 16G041-HD CERAMIC LEADLESS CHIP CARRIER 16G041-HA
Text: °C operating temperature range 1 Patented, self-acquiring PLL GaAs IC design ■Available in standard frequencies: 100,155.52, 250, 565 , and 622.08 Mbit/s. Custom frequencies available upon request. • PLL , -H integrates GigaBit's 16G041 PLL clock and data recovery GaAs IC together with a high performance loop filter , (GBLj GigaBit Logic 16G041-H Low Power, PLL Clock & Data Recovery Circuit 100 to 625 Mbit/s , and provides immunity to component aging and temperature effects • Retains lock for long constant


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PDF 16G041-H PLL IC 565 for PLL IC 565 565 PLL pin diagram lock range of 565 PLL IC 0420 LOP pll 565 FO56 16G041-HD CERAMIC LEADLESS CHIP CARRIER 16G041-HA
2004 - Mobile Camera Module

Abstract: 55560-0201 PLL IC 565 565RGB FPC CONNECTOR 20pin 20 fpc digital camera CMOS Camera Module connector mobile camera cmos camera module VS6524P02S
Text: as a 2.8 V single supply camera or as a 1.8 V / 2.5 V supply camera. The integrated PLL allows for low frequency system clock, and flexibility for successful EMC integration. This complete camera , , demosaicing, sharpening, gamma correction and color space conversion Embedded camera controller for , to QVGA, QQVGA and subQCIF ITU-R BT.656-4 YUV (YCbCr) 4:2:2 with embedded syncs, RGB 565 , RGB , syncs, 24 MHz clock Two-wire serial control interface On-chip PLL , 6.5 to 27 MHz clock


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PDF VS6524 10-bit 10-without Mobile Camera Module 55560-0201 PLL IC 565 565RGB FPC CONNECTOR 20pin 20 fpc digital camera CMOS Camera Module connector mobile camera cmos camera module VS6524P02S
1995 - JFET TRANSISTOR REPLACEMENT GUIDE j201

Abstract: UA6538 DC motor speed control using 555 and ir sensor U2740B-FP UAA145 CQY80 U2840B tcrt9050 TCDF1910 sod80 smd zener diode color band
Text: Complete system integration of analog signal processing and digital control circuit One IC for several , voltage CT2 RX/TX IC High integrated transceiver unit for CT2 1.1 GHz synthesizer Low current , ­16 Function Trans­impedance amplifier Data regenerator LED­driver Key Features IC kit for data rates up , 1.3 GHz prescaler U6225B­FP SO­16 2.9 GHz PLL for SAT­TV receiver U6235B­FP SO­16 3.5 GHz PLL for SAT­TV receiver U6359B­FL U6223B-FP U6224B U810BS U811BS U812BS U813BS SO


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PDF U3750BM U3760MB-FN U3760MB-SD SSO-44 SD-40 U3800BM U3810BM U4030B U4030B JFET TRANSISTOR REPLACEMENT GUIDE j201 UA6538 DC motor speed control using 555 and ir sensor U2740B-FP UAA145 CQY80 U2840B tcrt9050 TCDF1910 sod80 smd zener diode color band
am signal using multiplier ic 565

Abstract: encoder FSK Reed Solomon decoder IC ENCODER "Frequency Synthesizer" INTERPOLATOR 6 BITS SIN COS DATA CLK 16-DQAM BD-A AM MODULATOR using multiplier IC
Text: Low-cost Solution for HFC Network Return-channel Tx Function: 5-40 MHz/ 5-65 MHz Includes Programmable SRRC , (5-40 M Hz Aout) 20.48 M Hz w/ PLL enabled, 122.88 M Hz w/ PLL disabled ( 5-65 M Hz Aout) 27.792 M Hz w/ PLL , data out Substrate ground connection PLL ground connection Supply voltage for PLL PLL loop filter , Outline 44-Lead Metric Quad Flatpack IC Package (MQFP) SUBJECT TO CHANGE 0.063 (1.60) For further , Clock I X6 PLL I Control Functions T R e f C lo c k In 2 0 .4 8 M H z T FEC E n a b le / D


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PDF QPSK/16-QAM Hz/5-65 QPSK/DQPSK/16-QAM AD9853 AD9853 44-Lead am signal using multiplier ic 565 encoder FSK Reed Solomon decoder IC ENCODER "Frequency Synthesizer" INTERPOLATOR 6 BITS SIN COS DATA CLK 16-DQAM BD-A AM MODULATOR using multiplier IC
Signetics NE561

Abstract: AM DEMODULATOR USING PLL 565 SIGNETICS PLL ne561 NE561 signetics Signetics NE562 566 vco Signetics NE565 UA711 NE561N
Text: general pur pose PLL , the PLL with an added m ultiplier and the PLL tone decoder. The 560N. 562N and 565 , purpose phase locked loop intended solely for use as a tone decoder. It contains a complete PLL includ ing , enhances the inteference-rejection characteristics; second, it provides a short term memory for the PLL and , Linear Analysis for Lock Condition- Frequency Tracking When the PLL is in lock, the non-linear capture , . The open loop transfer function for the PLL can be written as (Equation 9-2) T is ) = KvF is


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PDF 200Hz. Signetics NE561 AM DEMODULATOR USING PLL 565 SIGNETICS PLL ne561 NE561 signetics Signetics NE562 566 vco Signetics NE565 UA711 NE561N
Not Available

Abstract: No abstract text available
Text: . The IC includes a 2nd order antialiasing input fil­ ter, a 57KHz switched capacitor band pass filter, a smoothing filter and cross detector, a bit rate clock recovery circuit, a 57KHz PLL , BI-PHASE , for siqnal quality indication (Hiqh = qood) Output for ARI indication: - high when RDS+ARI are , FILTER Supply current 4.0 6.5 9.0 mA Center frequency 56.5 57 57.5 kHz kHz , f1 (KHz) f2 (KHz) f3 (KHz) A 56.5 57 57.5 APh max <5° B 56 57 58


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PDF TDA7331 57KHz 332MHz 328MHz TDA7331 outp000
2007 - Color Codes surveillance

Abstract: vga camera Hsync Vsync RGB PLL IC 565 yuv to hsync vsync rgb to hsync vsync bt.656 bt.656 parallel to serial conversion cmos camera module D101
Text: controller for automatic exposure control, automatic white balance control, black level compensation , (YCbCr) 4:2:2 with embedded syncs, RGB 565 output formats Viewlive feature allows different sizes , camera module is ready to connect to camera enabled baseband processors, back-end IC devices or PDA , ) Videophone On-chip PLL , 6.5 to 26 MHz clock input Video surveillance Analog power supply , consumption, ultra low standby current Aspheric lens, F# 3.2 ~56° HFOV January 2007 Rev 1 For


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PDF VS6525 10-bit Color Codes surveillance vga camera Hsync Vsync RGB PLL IC 565 yuv to hsync vsync rgb to hsync vsync bt.656 bt.656 parallel to serial conversion cmos camera module D101
Not Available

Abstract: No abstract text available
Text: Downstream 5-65 MHz Upstream DESCRIPTION AND APPLICATIONS The ISG2000EU is a complete RF transceiver designed for use in European cable modem applications. The transceiver integrates a diplex filter, triple , converts QAM carriers to low IF sampling frequency for digital signal processing. The transm itter section , WITH QAM DEMOD/MOD ICs · BUILT IN RF TRANSMITTER: 50 dB AGC Driver · SUPERIOR SNR: 37 dB for 64 QAM / 35 dB for 256 QAM (TYP) · BUSINESS CARD SIZE: 3.4" x 2.0" x 0.5" · RUGGED DESIGN/NO


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PDF ISG2000EU ISG2000EU
2008 - CAMERA PARALLEL RGB TO MIPI CSI-2

Abstract: MIPI CSI-2 Parallel mipi csi-2 receiver MIPI csi-2 MIPI csi mipi csi receiver RGB TO MIPI cSI2 MIPI CAMERA automotive RGB to CSI-2 MIPI CSI-2 to Parallel
Text: integrated PLL allows for low frequency system clock, and flexibility for successful EMC integration. This , scan SXGA emulation with FFOV output Low power 30 fps SVGA progressive scan for video , option (VS6735) Two-wire serial control interface On-chip PLL , 6 to 27 MHz clock input , The VS6725/VS6735 is a CMOS color digital camera featuring low size and low power consumption for , pins February 2008 20-pin socket Description ITU-R BT.656-4 YUV (YCbCr) 4:2:2, RGB 565


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PDF VS6725 VS6735 VS6725: VS6735: 1600H 10-bit VS6735) CAMERA PARALLEL RGB TO MIPI CSI-2 MIPI CSI-2 Parallel mipi csi-2 receiver MIPI csi-2 MIPI csi mipi csi receiver RGB TO MIPI cSI2 MIPI CAMERA automotive RGB to CSI-2 MIPI CSI-2 to Parallel
565 PLL pin diagram

Abstract: PLL IC 565 PLL pSK DEMODULATOR psk demodulation DIP20 S020 TDA7331 TDA7331D 57KHz rds decoder
Text: Broadcasting Union) specifications. The IC includes a 2nd order antialiasing input filter, a 57KHz switched , 57KHz PLL , BI-PHASE PSK decoder, differential decoding circuit, ARI indication and RDS signal quality , output 1187.5Hz 13 RDDA RDS data output 14 QUAL Output for signal quality indication (High = good) 15 ARI Output for ARI indication: - high when RDS+ARI are present - high when only ARI is present 16 VCC , Center frequency 56.5 57 57.5 kHz BW 3dB Bandwidth 2.5 3 3.5 kHz G Gain f = 57kHz 18 20 22 dB A


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PDF TDA7331 57KHz 332MHz 328MHz DIP20 TDA7331 TDA7331D 565 PLL pin diagram PLL IC 565 PLL pSK DEMODULATOR psk demodulation DIP20 S020 TDA7331D rds decoder
2002 - DVD read writer circuit diagram

Abstract: DVD laser pickup assembly dvd writer laser diode DVD optical pick-up assembly alpha date code System TZA1032 dvd writer circuit diagram DVD RW pickup assembly CD laser pickup assembly LQFP64
Text: -bit resolution · Automatic write-read switching for run lengths 16 · Internal modulator up to 565 MHz · , PLL oscillator features a self-learning oscillator mode for non-locked operation during read · Wide , 565 MHz PLL in Current Controlled Oscillator (CCO) mode 240 - 440 MHz depends , the clock reference for the internal PLL . DATAP 25 I data input; analog current input , driver IC test pads TEST2 5 I digital input bus for test mode control. Normal functional mode


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PDF TZA1032 SCA74 753503/01/pp24 DVD read writer circuit diagram DVD laser pickup assembly dvd writer laser diode DVD optical pick-up assembly alpha date code System TZA1032 dvd writer circuit diagram DVD RW pickup assembly CD laser pickup assembly LQFP64
CH8398

Abstract: CH8398A STG1703 TQD4133 stg170
Text: Drives singly or doubly terminated 75 Q loads ID register for software identification Power down features for "Green PC" applications Anti-sparkle circuitry Dual-programmable 135 MHz PLL clocks On-chip loop filters for PLL clocks Pin compatible to SGS-Thomson STG1703 Low power CMOS technology in 68-pin PLCC 5V , . For further information, please refer to Figure 6 on page 20. Following is the 16B1P1C ( 5-6-5 ) pixel , . For further information, please refer to Figure 6 on page 20. Following is the 16B1P2C ( 5-6-5 ) pixel


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PDF CH8398A 16-bit ATT20C498 T004133 CH8398 CH8398A STG1703 TQD4133 stg170
7S1 zener diode

Abstract: CH8398 STG1703 gi 9440 diode stg170
Text: features for "Green PC" applications Anti-sparkle circuitry Dual-programmable 135 MHz PLL clocks On-chip loop filters for PLL clocks Pin compatible to SGS-Thomson STG1703 Low power CMOS technology in 68 , . For further information, please refer to Figure 6 on page 4-45. Following is the 16B1P2C ( 5-6-5 , Read Address Register PRA specifies the address to the palette RAM for read access. CWA: PLL Clock RAM Write Address Register CWA specifies the address to the PLL RAM for write access. Using the


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PDF CH8398 16-bit ATT20C498 CH8398 7S1 zener diode STG1703 gi 9440 diode stg170
gi 9440 diode

Abstract: CH8398 STG1703 7S1 zener diode
Text: or doubly terminated 75 Q loads ID register for software identification Power down features for "Green PC" applications Anti-sparkle circuitry Dual-programmable 135 MHz PLL clocks On-chip loop filters for PLL clocks Pin compatible to SGS-Thomson STG1703 Low power CMOS technology in 68-pin PLCC 5V , for read access. CWA: PLL Clock RAM Write Address Register CWA specifies the address to the PLL RAM , RAM, and a triple 8-bit 110/135 MHz video DAC. The video clock PLL provides 16 programmable


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PDF CH8398 16-bit ATT20C498 D0023E gi 9440 diode STG1703 7S1 zener diode
2012 - MO-220-VNND-4

Abstract: adl537x D8P analog devices
Text: frequency. The AD9122-EP TxDAC+® includes features optimized for direct conversion transmit applications , , Inc. A 4-wire serial port interface provides for programming/readback of many internal parameters , allows carrier placement anywhere in the DAC bandwidth Gain, dc offset, and phase adjustment for sideband suppression Multiple chip synchronization interfaces High performance, low noise PLL clock multiplier Digital , output switching technique enhances dynamic performance. Current outputs are easily configured for


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PDF 16-Bit, AD9122-EP AD9122-EP ADL537x 52809-A MO-220-VNND-4 72-Lead CP-72-7) MO-220-VNND-4 D8P analog devices
resistor r20 Part #537

Abstract: PLL IC 565 ATIC 64 C1
Text: bits are the control bits. Latch enable pin for the dual PLL . High im pedance CM OS input. W hen LE , Downstream 5-65 MHz Upstream DESCRIPTION AND APPLICATIONS The ISG2000EU is a complete RF transceiver designed for use in cable modem applications. The transceiver integrates a diplex filter, triple conversion , PARAMETERS Power Requirements Supply Current Supply Voltage V1 Tx ( 5 V) Ic c i (Rx) |CC2 (Rx) Ic c i , inverting input to the Tx amplifier. The input frequency range spans covers 5-65 MHz. 1


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PDF ISG2000EU ISG2000EU 24-Hour resistor r20 Part #537 PLL IC 565 ATIC 64 C1
pll 566

Abstract: pll 565 application pll 565 DJZ capacitor CA1310 565 PLL AD P71 CA10 CA12 elan microelectronics 1999
Text: EM78567/566/ 565 Manual ;= PLL = 0X06 RF = 0X0F , ICE567 User manual FOR EM78565 EM78566 EM78567 Version 1.0 ELAN MICROELECTRONICS CORP. No , ) 5639977 FAX: (03) 5630118 EM78567/566/ 565 Manual EM78P567/566/ 565 Manual EM78R567 SPEC , ) PORT7(2) PORT7(3) PORT7(4) PORT7(5) 1999/Jun/14 DESCRIPTION power ground Input pin for 32.768 kHz oscillator Output pin for 32.768 kHz oscillator Phase loop lock capacitor, connect a


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PDF ICE567 EM78565 EM78566 EM78567 EM78567/566/565 EM78P567/566/565 EM78R567 DELAY22 1999/Jun/14 pll 566 pll 565 application pll 565 DJZ capacitor CA1310 565 PLL AD P71 CA10 CA12 elan microelectronics 1999
Not Available

Abstract: No abstract text available
Text: 565 to 585 MHz for CDMA cellular base station application. The KSN-585A-119+ is packaged in a metal , -585A-119+ is a Frequency Synthesizer, designed to operate from 565 to 585 MHz for CDMA cellular base station , Frequency Synthesizer 50Ω KSN-585A-119+ 565 to 585 MHz The Big Deal • Low phase , Design Engineers Search Engine finds the model you need, Instantly • For detailed performance specs & , therein. For a full statement of the Standard Terms and the exclusive rights and remedies thereunder


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PDF KSN-585A-119+ DK801
2010 - pll 565

Abstract: ADF4118 565 application frequency synthesizer 56497
Text: -585A-119+ 565 to 585 MHz Features · Integrated VCO + PLL · Low phase noise and spurious · Robust design , Frequency Synthesizer 50 KSN-585A-119+ 565 to 585 MHz The Big Deal · Low phase noise and , Product Overview The KSN-585A-119+ is a Frequency Synthesizer, designed to operate from 565 to 585 MHz for CDMA cellular base station application. The KSN-585A-119+ is packaged in a metal case (size of , , Instantly · For detailed performance specs & shopping online see Notes: 1. Performance and quality


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PDF KSN-585A-119+ DK801 pll 565 ADF4118 565 application frequency synthesizer 56497
NE565

Abstract: PLL NE565 565 PLL AM MODULATOR USING ne565 circuit diagram binary phase shift keying demodulation NE565 PLL IC NE565 pin diagram of NE565 ne 565 pll frequency shift keying demodulation using pll 565
Text: , the 565 PLL can lock to and track an input signal over a very wide bandwidth (typically ±60%) with , , adaptable filter and de modulator for the frequency range from 0.001 Hz to 500kHz. The circuit comprises a , filter as shown in the block diagram. The center frequency of the PLL is determined by the free-running , Ll 1-1 EX TERNAL C FOR VCO D E M O D U L A T E D i-OUT PUT Li. - I E X TE R N A L _U R , output for connection of com parator in frequency discrim inator · Bandwidth adjustable from < ±1% to


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PDF NE/SE565-F SE565/NE565 500kHz. 67kHz NE565 PLL NE565 565 PLL AM MODULATOR USING ne565 circuit diagram binary phase shift keying demodulation NE565 PLL IC NE565 pin diagram of NE565 ne 565 pll frequency shift keying demodulation using pll 565
2002 - 565 pin diagram

Abstract: F562 565 pin dETAILS ocs4 pll 565 565 PLL AF9704 AF9706 microcontroller mb90560 pll 565 application
Text: The MB90560/ 565 series is a general-purpose 16-bit microcontroller designed for industrial, OA, and , for processing long word (32-bit) data. s FEATURES · Clock · Internal oscillator circuit and PLL , , main clock, or PLL clock. The main clock is the oscillation clock divided into 2 (0.5 MHz to 8 MHz for , ( for oscillation = 4 MHz, PLL clock setting = × 4, VCC = 5.0 V) · Maximum CPU memory space : 16 MB · , Manual" for details. 5 MB90560/ 565 Series s PACKAGE AND CORRESPONDING PRODUCTS Package


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PDF DS07-13715-3E 16-bit F2MC-16LX MB90560/565 MB90561/561A/562/562A/F562/F562B/V560 MB90567/568/F568 F2MC-16L F0204 565 pin diagram F562 565 pin dETAILS ocs4 pll 565 565 PLL AF9704 AF9706 microcontroller mb90560 pll 565 application
2002 - 565 PLL

Abstract: DIP-64P-M01 F2MC-16LX FPT-64P-M06 FPT-64P-M09
Text: The MB90560/ 565 series is a general-purpose 16-bit microcontroller designed for industrial, OA, and , for processing long word (32-bit) data. s FEATURES · Clock · Internal oscillator circuit and PLL , , main clock, or PLL clock. The main clock is the oscillation clock divided into 2 (0.5 MHz to 8 MHz for , ( for oscillation = 4 MHz, PLL clock setting = × 4, VCC = 5.0 V) · Maximum CPU memory space : 16 MB · , Manual" for details. 5 MB90560/ 565 Series s PACKAGE AND CORRESPONDING PRODUCTS Package


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PDF DS07-13715-3E 16-bit F2MC-16LX MB90560/565 MB90561/561A/562/562A/F562/F562B/V560 MB90567/568/F568 F2MC-16L F0204 565 PLL DIP-64P-M01 FPT-64P-M06 FPT-64P-M09
2002 - programmable timer

Abstract: FF201
Text: The MB90560/ 565 series is a general-purpose 16-bit microcontroller designed for industrial, OA, and , for processing long word (32-bit) data. s FEATURES · Clock · Internal oscillator circuit and PLL , , main clock, or PLL clock. The main clock is the oscillation clock divided into 2 (0.5 MHz to 8 MHz for , ( for oscillation = 4 MHz, PLL clock setting = × 4, VCC = 5.0 V) · Maximum CPU memory space : 16 MB · , Manual" for details. 5 MB90560/ 565 Series s PACKAGE AND CORRESPONDING PRODUCTS Package


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PDF DS07-13715-3E 16-bit F2MC-16LX MB90560/565 MB90561/561A/562/562A/F562/F562B/V560 MB90567/568/F568 F2MC-16L programmable timer FF201
1997 - Not Available

Abstract: No abstract text available
Text: operates in accordance with the EBU (European Broadcasting Union) specifications. The IC includes a 2nd , cross detector, a bit rate clock recovery circuit, a 57KHz PLL , BI-PHASE PSK decoder, differential , 3 Oscill ator & Divid er 18 OSEL FSEL 12 5 7kH z PLL 1187.5Hz Bit PLL 15 AR I 14 fa st ARI , RDS clock output 1187.5Hz RDS data output Output for signal quality indication (High = good) Output for ARI indication: - high when RDS+ARI are present - high when only ARI is present Supply voltage not


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PDF TDA7331 57KHz 332MHz 328MHz TDA7331
2001 - Not Available

Abstract: No abstract text available
Text: divided into 2 (0.5 MHz to 8 MHz for a 1 MHz to 16 MHz base oscillation) . The PLL clock is the , instruction execution time : 62.5 ns ( for oscillation = 4 MHz, PLL clock setting = × 4, VCC = 5.0 V) â , -507 Hardware Manual” for details. 4 DS07-13715-5E MB90560/ 565 Series 2. MB90565 Series Part Number , for details of each package. 6 DS07-13715-5E MB90560/ 565 Series I PIN ASSIGNMENTS 64 63 , VSS power supply input pin for A/D converter. (Continued) DS07-13715-5E 11 MB90560/ 565


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PDF DS07-13715-5E 16-bit F2MC-16LX MB90560/565 MB90561A/562A/F562B/V560/567/568/F568 F2MC-16L
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