The Datasheet Archive

Top Results (6)

Part Manufacturer Description Datasheet Download Buy Part
SN74ACT7802-XXFN Texas Instruments 1KX18 OTHER FIFO, PQCC68
SN74ALVC7804-20DL Texas Instruments 512X18 OTHER FIFO, PDSO56
SN74ACT7801-20PN Texas Instruments 1KX18 OTHER FIFO, PQFP80
SN74ACT7801-20PNR Texas Instruments 1KX18 OTHER FIFO, PQFP80
SN74ACT7802-28.5FN Texas Instruments 1KX18 OTHER FIFO, PQCC68
SN74ACT7805DL Texas Instruments 256X18 OTHER FIFO, PDSO56

fifo ttl Datasheets Context Search

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Not Available

Abstract: No abstract text available
Text: , TTL ) RESET when LOW clears the FIFO address counters and sets the internal registers to zero. Data , provided to load the Data Serializer from the FIFO . Start Bit Strobe (Input, TTL ) The start bit , clock. FIFO Full (Output, TTL ) FULL goes HIGH on reset and stays HIGH until there are more than 56 bytes in the FIFO . FULL w ill go HIGH again when there are less than 56 bytes in the FIFO . TTL , Am8172 Video Data Assembly FIFO (VDAF) PRELIMINARY DISTINCTIVE CHARACTERISTICS • • â


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PDF Am8172 Am8172 WF024710 WF024750
2002 - Not Available

Abstract: No abstract text available
Text: and looped back out TXOUTA/B (B1CALCEN = X). TTL A logic 1 causes frame alignment FIFO 's to be , , FRALIGNRST resets only the unselected channel alignment FIFO . TTL Selects which input channel, RXINA , ] TXCLK+/TXCLK_SRC+/- 16 bit 155MHz 4 bit 622MHz Retiming FIFO TXOUTA+/- 2:1 MUX [15:0 , inputs operating at 155MHz or 622MHz, respectively, into an internal FIFO using source synchronous , signals and large internal FIFO for tolerance of up to +/- 75ns of serial backplane skew • Realignment


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PDF VSC9180 16-Bit 155MHz/4-Bit 622MHz STS-12/STM-4 STS-12 155MHz, 622MHz, 488GHz, 65GHz
2005 - SC16C550B

Abstract: No abstract text available
Text: the 16C450. The SC16C550B also provides DMA mode data transfers through FIFO trigger levels and the , operation at 5 V, 2 Mbit/s at 3.3 V, and 1 Mbit/s at 2.5 V 16 byte transmit FIFO 16 byte receive FIFO with , selectable baud rate generator Four selectable Receive FIFO interrupt trigger levels Standard modem interface , status reporting capabilities s 3-state output TTL drive capabilities for bi-directional data bus and , SC16C550B TRANSMIT FIFO REGISTERS TRANSMIT SHIFT REGISTER TX D0 to D7 IOR, IOR IOW, IOW RESET DATA


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PDF SC16C550B 16-byte SC16C550B ST16C550, TL16C550 PC16C550, 16C450. HVQFN32
1030J6C

Abstract: C1030B TDC1030B6C 1030J6A
Text: size of the FIFO by leaving open 7 x 64 . . . 1 x input pins must Value TTL TTL TTL TTL TTL TTL TTL , , the outputs of the FIFO are TTL compatible. When disabled (OE HIGH), the outputs go into their , he T R W T D C 1 0 3 0 is an expandable, First-In First-Out ( FIFO ) m em ory organized as 64 w o rd s , ond ing input pins, facilitating board layouts in ex p an ded form at. All inputs and outputs are TTL , 1 3 M H z · R ead ily Exp and able In W o rd A n d B it D im ension · TTL C om patib le · A synchro


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PDF 18MFHz 1030J6C C1030B TDC1030B6C 1030J6A
TRW 1030J6C

Abstract: 1030J6C SO-64 TDC1030B6C TDC1030 TDC1030B6A TDC1030C3A TDC1030C3C
Text: state of power up. With the OE LOW, the outputs of the FIFO are TTL compatible. When disabled (OE HIGH , expandable, First-ln First-Out ( FIFO ) memory organized as 64 words by 9 bits. A 15MHz data rate makes it , , facilitating board layouts in expanded format. All inputs and outputs are TTL compatible. Features • 64 , €¢ TTL Compatible • Asynchronous Or Synchronous Operation • Three-State Outputs • Master Reset , Description Data Input (Figure 1) Following power up, the Master Reset IMRI is pulsed LOW to clear the FIFO


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PDF TDC1030 TDC1030 15MHz 18MHz devi28 1030J6C 1030J6A TRW 1030J6C SO-64 TDC1030B6C TDC1030B6A TDC1030C3A TDC1030C3C
1996 - MAC8110

Abstract: MAC110 ML53101
Text: signals to indicate that a threshold number of locations TTL Output are available in the transmit FIFO , -bit FIFO transfer using these signals. TTL l/O R/W* FIFO Read/FlFO Write. The host asserts this , ; when LOW, the pin indicates a write operation. TTL Input TREN* Transfer Enable. Enables FIFO transfers. TTL Input SOF Start of Frame. The FIFO data originator asserts this signal HIGH to , being written or read is the last word in the frame. TTL l/O DATA[63:0] FIFO Data Bus. Carries


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PDF ML53101 MAC8110) 32-Bit MAC8110 MAC110
1996 - ML53101

Abstract: MAC110
Text: of bytes are TTL Output available in the receive FIFO on the indicated port. TXDRDY[7:0 , data transfer. TTL Input BVAL[7:0] Byte Valid. The FIFO data originator indicates the validity of respective data bytes within the 64-bit FIFO transfer using these signals. TTL l/O R/W , Input TREN* Transfer Enable. Enables FIFO transfers. TTL Input SOF Start of Frame. The , is the first word in the frame. TTL l/O EOF End of Frame. The FIFO data originator asserts


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PDF ML53101 MAC8110) 32-Bit 64-Bit MAC110
interlace parity

Abstract: MAC layer sequence number
Text: in the frame. FIFO Data Bus. Carries data for the FIFO interface. TTL Input TTL I/O I/O TTL , 8 M il inter faces on one side and with shared first-in, first-out queue ( FIFO ) and peripheral , ) support. · Shared 64-bit, 66-MHz FIFO Interface for TX and RX data transfer. · FIFO bus bandwidth exceeds , Frame Status can be appended at the end of a frame as an additional 64-bit data word on the FIFO Interface. · Independent dual-port RX and TX FIFOs for each MAC. · Programmable FIFO burst size of 32/ 64


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PDF ML53101 MAC8110) 10-Mbps 100-Mbps interlace parity MAC layer sequence number
1999 - CY7C9689-AC

Abstract: CY7C42X5 CY7C9689 CY7C9689-AI
Text: to The TTL parallel I/O interface may be configured as either a FIFO (configurable for depth , TTL clock input Transmit FIFO Clock. Used to sample all Transmit FIFO and related interface , TXBISTEN is HIGH. All Transmit FIFO read operations are suspended when BIST is active. TTL input , . When the Transmit FIFO is bypassed (FIFOBYP is LOW), TXRST is ignored. 9 TXHALT TTL input , continue loading data into the Transmit FIFO while TXHALT is asserted. 72 TXFULL Three-state TTL


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PDF CY7C9689 CY7C9689 10-bit CY7C9689-AC CY7C42X5 CY7C9689-AI
4b/5b encoder

Abstract: CY7C42X5 CY7C9689 CY7C9689-AC
Text: additional glue-logic. The TTL parallel I/O interface may be configured as either a FIFO (configurable for , active. 16 TXRST TTL input, sampled on TXCLKt Reset Transmit FIFO . When the Transmit FIFO is enabled , TTL output, changes following TXCLKt or REFCLKt Transmit FIFO Full status flag. When the Transmit FIFO , . Receive Path Signals 8 RXCLK Bidirectional TTL clock Receive clock. When the Receive FIFO is enabled , rxrst TTL input, sampled on rxclkT Receive FIFO Reset. Active LOW. When the Receive FIFO is enabled


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PDF CY7C9689 AM7968/7969 10-bit 12-bit 50-to-200 100-pin CY7C9689 4b/5b encoder CY7C42X5 CY7C9689-AC
Not Available

Abstract: No abstract text available
Text: additional glue-logic. The TTL parallel I/O interface may be configured as either a FIFO (configurable for , Path Signals 68 TXCLK TTL clock input Transmit FIFO Clock. CY7C9689 Used to sample all Transmit FIFO and related interface signals. 44,42, TXDATA[7:0] 40,36, 34,32, 30, 22 TTL input, sampled on , TTL input, sampled on Reset Transmit FIFO . TXCLKt When the Transmit FIFO is enabled (FIFOBYP is HIGH , asserted. When the Transmit FIFO is bypassed (FIFOBYP is LOW), TXRST is ignored. 9 TXHALT TTL


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PDF CY7C9689 10-bit 10-bit 12-bit CY7C9689
Not Available

Abstract: No abstract text available
Text: for additional glue-logic. The TTL parallel I/O interface may be configured as either a FIFO , Signal Description Transmit Path Signals 68 TXCLK TTL clock input Transmit FIFO Clock. Used , TXBISTEN is HIGH. All Transmit FIFO read operations are suspended when BIST is active. TTL input , . When the Transmit FIFO is bypassed (FIFOBYP is LOW), TXRST is ignored. 9 TXHALT TTL input , continue loading data into the Transmit FIFO while TXHALT is asserted. 72 TXFULL Three-state TTL


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PDF AM7968/7969 10-bit 12-bit 50-to-200 100-pin CY7C9689
transistor AC126

Abstract: equivalent transistor ac125 AC393 AC126 74AC393 d flip flop AC365 AC682 p6nk60z ACT03
Text: AC161 ACT161 FUNCTION Quad 2-Input NAND Gate Quad 2-Input NAND Gate ( TTL Compatible) Quad 2-Input NAND Gate (Open Drain) Quad 2-Input Positive-NOR Gate Quad 2-Input Positive-NOR Gate ( TTL Compatible) Quad 2-Input NAND Gate (Open Drain) Quad 2-Input NAND Gate (Open Drain - TTL Compatible) Hex Inverter Hex Inverter ( TTL Compatible) Hex Inverter (Unbuffered) Hex Inverter w/ Open-Drain Output Hex Inverter w/ Open-Drain Output( TTL Compatible) Hex Buffer w/ Open-Drain Output Quad 2-Input NAND Gate


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PDF ACT00 ACT02 ACT03 ACT04 ACU04 ACT05 ACT08 ACT10 ACT11 ACT14 transistor AC126 equivalent transistor ac125 AC393 AC126 74AC393 d flip flop AC365 AC682 p6nk60z ACT03
OXPCI958

Abstract: PU5103 AT96C46 at96c AD-29B C80-004 63 marking PMDS 88h-8Fh OX16PCI958 16C550
Text: Supports both 5.0-V & 3.3-V PCI signalling 32-byte deep FIFO per transmitter & receiver Baud rates up to , enhancements: · Clock prescaler allows more baud rate options · Readable FIFO levels & tuneable trigger , the receive FIFO . The state of the UART can be found at any time by reading status registers, and , by using the prioritised interrupt identification register, readable FIFO levels, and tuneable FIFO , Registers 4.3. Serial Data Format 4.4. Transmitter/Receiver Section 4.5. FIFO Interrupt Mode Operation


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PDF OX16PCI958 32-bit, 16C550type 16C550/450 32-byte DS-0022 OX16PCI958-PQAG OXPCI958 PU5103 AT96C46 at96c AD-29B C80-004 63 marking PMDS 88h-8Fh 16C550
AM8172

Abstract: No abstract text available
Text: used and four bits FDCC FIFO Full (Output, TTL ) FULL goes HIGH on reset and stays HIGH until there are , rising edge of DOTCLK. ftESfeT Reset (input, TTL ) RESET when LOW clears the FIFO address counters and , Am8172 Video Data Assembly FIFO (VDAF) _PRELIMINARY_ DISTINCTIVE CHARACTERISTICS • Supports , €¢ 10KH ECL with pixel rates of up to 200 MHz GENERAL DESCRIPTION The Am8172 Video Data Assembly FIFO is a , ALU, a 64 x 8 FIFO , and a Data Serializer. The Data Assembly ALU accepts display memory data as either


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PDF Am8172 WF024701 WF024710
BD005

Abstract: AM8172 AM8172DC
Text: FDCC FIFO Full (Output, TTL ) FULL goes HIGH on reset and stays HIGH until there are more than 56 bytes , DOTCLK. ftESfeT Reset (input, TTL ) RESET when LOW clears the FIFO address counters and sets the internal , Am8172 Video Data Assembly FIFO (VDAF) _PRELIMINARY_ DISTINCTIVE CHARACTERISTICS â , €¢ 10KH ECL with pixel rates of up to 200 MHz GENERAL DESCRIPTION The Am8172 Video Data Assembly FIFO is , ALU, a 64 x 8 FIFO , and a Data Serializer. The Data Assembly ALU accepts display memory data as


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PDF Am8172 Am8172 WF024701 WF024710 BD005 AM8172DC
2011 - CY7C42X5

Abstract: CY7C9689A CY7C9689A-AC
Text: ] . 24 CY7C9689A Transmitter TTL Switching Characteristics, FIFO Enabled Over the Operating Range . 25 CY7C9689A Receiver TTL Switching Characteristics, FIFO Enabled Over the Operating Range . 25 CY7C9689A Transmitter TTL Switching Characteristics, FIFO Bypassed Over the Operating Range . 26 CY7C9689A Receiver TTL Switching Characteristics, FIFO Bypassed Over the Operating Range , Path Signals 68 TXCLK TTL clock input Internal Pull-up Transmit FIFO Clock. Used to sample


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PDF CY7C9689A AM7968/7969 10-bit 12-bit 256-character 200-MBaud CY7C42X5 CY7C9689A CY7C9689A-AC
2001 - Not Available

Abstract: No abstract text available
Text: for additional glue-logic. The TTL parallel I/O interface may be configured as either a FIFO , ] . 24 CY7C9689A Transmitter TTL Switching Characteristics, FIFO Enabled Over the Operating Range . 25 CY7C9689A Receiver TTL Switching Characteristics, FIFO Enabled Over the Operating Range . 25 CY7C9689A Transmitter TTL Switching Characteristics, FIFO Bypassed Over the Operating Range . 26 CY7C9689A Receiver TTL Switching Characteristics, FIFO Bypassed Over the Operating Range


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PDF CY7C9689A AM7968/7969 10-bit 12-bit 256-character 200-MBaud
dp8512

Abstract: vlt 2900
Text: required in high performance raster scan video systems. Also on the VSR are four words of FIFO which by , configured as flip-flops (one word FIFO mode), and four word FIFO mode. As mentioned above, the mode control , CLOCK input shifts data out of the shift register. In the four word FIFO mode, four write operations may , written data. The four words of FIFO significantly ease the timing constraints which are present when , associated with the shift register, are TTL compatible. The shift register in- puts and control signals are


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PDF DP8515/DP8515-350/ DP8516/DP8516-350 DP8515/DP8515-350/DP8516/DP8516-350 2-26A AA32096 dp8512 vlt 2900
2002 - CY7C9689A

Abstract: CY7C9689A-AC CY7C42X5
Text: Transmit FIFO . Data is read from the Transmit FIFO and is encoded using embedded 4B/5B or 5B/6B The TTL , TTL input, asynchronous Internal Pull-up 16 TXRST TTL input, sampled on Reset Transmit FIFO , Transmit FIFO is bypassed (FIFOBYP is LOW), TXRST is ignored. 9 TXHALT TTL input, sampled on , continue loading data into the Transmit FIFO while TXHALT is asserted. 72 TXFULL Three-state TTL , . 70 TXHALF Three-state TTL output, changes following TXCLK Transmit FIFO Half-full Status


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PDF CY7C9689A CY7C9689A CY7C9689 CY7C9689A-AC CY7C42X5
1997 - als007

Abstract: ALS120 Avance Logic MX365 Application data MX08 8000h-0-7FFFh ALS300 mx38 MX4C TAG 8646
Text: Characteristic Definition 6mA TTL compatible CMOS IO (Vt=1.7V) 6mA TTL compatible CMOS IO (Vt=1.7V) 6mA TTL compatible CMOS IO (Vt=1.7V) 6mA TTL compatible CMOS IO (Vt=1.7V) 6mA TTL compatible CMOS IO (Vt=1.7V) 6mA TTL compatible CMOS IO (Vt=1.7V) 6mA TTL compatible CMOS IO (Vt=1.7V) 6mA TTL compatible CMOS IO (Vt=1.7V) 6mA TTL compatible CMOS IO (Vt=1.7V) 6mA TTL compatible CMOS IO (Vt=1.7V) 6mA TTL compatible CMOS IO (Vt=1.7V) 6mA TTL compatible CMOS IO (Vt=1.7V) 6mA TTL compatible CMOS IO (Vt=1.7V) 6mA TTL


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PDF ALS300 ALS300 RL5305 Pro/16 82371AB ALS120 als007 Avance Logic MX365 Application data MX08 8000h-0-7FFFh mx38 MX4C TAG 8646
2006 - Descrambler

Abstract: CY7C42X5 CY7C9689A CY7C9689A-AC
Text: glue-logic. The TTL parallel I/O interface may be configured as either a FIFO (configurable for depth , 68 TXCLK TTL clock input Internal Pull-up Transmit FIFO Clock. Used to sample all Transmit FIFO and related interface signals. 44, 42, TXDATA[7:0] 40, 36, 34, 32, 30, 22 TTL input , 16 TXRST TTL input, sampled on Reset Transmit FIFO . When the Transmit FIFO is enabled (FIFOBYP , Transmit FIFO while TXHALT is asserted. 72 TXFULL Three-state TTL output, changes following


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PDF CY7C9689A AM7968/7969 10-bit 12-bit 256-character 200-MBaud 100-pin CY7C9689 Descrambler CY7C42X5 CY7C9689A CY7C9689A-AC
7330-9

Abstract: No abstract text available
Text: -bit operation ECL version, Am8172, with pixel rates of up to 200 MHz TTL version, Am8171, with pixel rates of up to 75 MHz GENERAL DESCRIPTION The Am8171/Am8172 Video Data Assembly FIFO is a high-speed TTL /ECL , out SO2. 5E FULL FIFO Full (Output, TTL ) FULL goes HIGH on reset and stays HIGH until there are , Am8171/Am8172 Video Data Assembly FIFO (VDAF) ADVANCE INFORMATION j-jrt*ss-o? DISTINCTIVE , x 8 FIFO , and a Data Serializer. The Data Assembly ALU accepts display memory data as either one 8


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PDF Am8171/Am8172 Am8172, Am8171, Am8171 7330-9
2000 - CY7C42X5

Abstract: CY7C9689
Text: the Transmit FIFO and is encoded using embedded 4B/5B or 5B/6B encoders to The TTL parallel I/O , BIST is active. TTL input, sampled on Reset Transmit FIFO . TXCLK When the Transmit FIFO is enabled , Transmit FIFO while TXHALT is asserted. 72 TXFULL Three-state TTL out- Transmit FIFO Full Status , TTL out- Transmit FIFO Half-full Status Flag. put, changes following When the Transmit FIFO is , "full-chip" reset (i.e., while RESET is LOW). 60 TXEMPTY Three-state TTL out- Transmit FIFO Empty


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PDF CY7C9689 CY7C9689 10-bit CY7C42X5
2001 - Not Available

Abstract: No abstract text available
Text: BIST is active. 7 TXBISTEN 16 TXRST TTL input, sampled on Reset Transmit FIFO . TXCLK , the Transmit FIFO while TXHALT is asserted. Three-state TTL out- Transmit FIFO Full Status Flag. put , TXHALF I/O Characteristics Signal Description Three-state TTL out- Transmit FIFO Half-full Status Flag , TTL out- Transmit FIFO Empty Status Flag. put, changes following When the Transmit FIFO is enabled , Characteristics Signal Description TTL input, sampled on Receive FIFO Reset. Active LOW. RXCLK¦ When the Receive


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PDF CY7C9689A AM7968/7969 10-bit 12-bit 50-to-200 100-pin CY7C9689A CY7C9689
Supplyframe Tracking Pixel