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fastscan Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
HG71G

Abstract: HG73C HG76C LSI12 ieee1149.1 0D001 Synopsys g006 fastscan 00C001
Text: Scan,Module test,B/S) FastScan (M) Test Compiler (S) Silicon Ensemble (C) Verilog-XL (C) VCS , Silicon Ensemble Cadence Novas FastScan (v8.6_4.5) Debussy (4.3


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PDF IEEE1149 HG71G HG73C HG76C LSI12 ieee1149.1 0D001 Synopsys g006 fastscan 00C001
Celaro

Abstract: green hills compiler TC240 fastscan TX49 TC280 TC260 TC200 TC140 tc160
Text: Synopsys ATPG JTAG Mentor Graphics DFTAdvisor FastScan ATPG JTAG , TetraMAX DFTAdvisor / FastScan PowerTheater Power Compiler , Mentor Mentor Graphics Seamless XRAY DFTAdvisor FastScan ModelSim CelaroMentor Graphics


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PDF BCJ0011D BCJ0011C Celaro green hills compiler TC240 fastscan TX49 TC280 TC260 TC200 TC140 tc160
rxfe

Abstract: 10gbps serdes 160GB Prism Circuits
Text: ( Fastscan ) GDSII Encrypted Spice Netlist Datasheet and Specifications Application Notes ASIC/SOC


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PDF 160Gbps 8B/10B rxfe 10gbps serdes 160GB Prism Circuits
astro tool

Abstract: Mentor Software in VHDL AEROFLEX Simulation
Text: EDA Design Tool Support EDA Vendor Synopsys Mentor Graphics Cadence Software Package DesignCompiler PowerCompiler DFTCompiler TetraMax VHDLCompiler HDLCompiler PrimeTime VCS * VCS-MX * / Scirocco * Formality Astro Pro StarRC-XT ModelSim * Leonardo Spectrum 3 QuickFault DesignArchitect FastScan * Verilog-XL * Conformal / Verplex Encounter * Dracula Purpose Logic Synthesis Power Synthesis / Analysis Test Circuitry Synthesis ATPG Read VHDL Designs Read Verilog Designs Sign-off


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2002 - MCP8245

Abstract: MPC8245 AN2164 MPC8240 MPC8241
Text: debug address mode. None. Y Reduced FastScan test coverage In debug address mode, the , address signal. FastScan test patterns cannot be relied on to screen the part on the factory tester , FastScan testing resulting in the total test coverage being reduced to 25% coverage. 1.1 None, do , non-participating agent. 7 Error No. 1: Reduced FastScan test coverage Detailed Description: The COP scan chain contains defects. The COP scan chain must be disabled for FastScan testing resulting in the total


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PDF MPC8245CE/D MPC8245/MPC8241 MPC8245/MPC8241 and19 MCP8245 MPC8245 AN2164 MPC8240 MPC8241
z80 vhdl

Abstract: TC190 TOSHIBA TC160 LSI CMOS GATE ARRAY toshiba TC200 PLL in RTL tc260c TOSHIBA TC203 TX49 5V/130nm CMOS
Text: TetraMAX DFTAdvisor / FastScan PowerTheater Power Compiler , Mentor Mentor Graphics Seamless XRAY DFTAdvisor FastScan ModelSim CelaroMentor Graphics


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PDF TC320 TC300 TC280 TC260 TC200 TC203 TC220 TC223 TC190 TX49RISC z80 vhdl TC190 TOSHIBA TC160 LSI CMOS GATE ARRAY toshiba TC200 PLL in RTL tc260c TOSHIBA TC203 TX49 5V/130nm CMOS
1999 - Not Available

Abstract: No abstract text available
Text: Mentor Design Flow Schematics Schematics Composer Verilog/VHDL PMG Models PMG SystemBuilder QuickSim or QuickSim Pro or ModelSim Behavioural Simulation DFT Advisor DFT Insight Synopsys Design Compiler Synthesis, Optimization and scan insertion Synopsys Test Compiler SST Velocity Static Timing Analysis DFT Advisor + FastScan ATPG or FlexTest QuickGrade II + TPV + DFT Insight Test Pattern Verification Mitel MLE and/or Layout


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1999 - Gate level simulation without timing

Abstract: No abstract text available
Text: Verilog Design Flow Composer Schematics Schematics Verilog SystemBuilder PMG PMG PMG models Megacells RAM/ROM models Any Verilog Compliant simulator Behavioural Simulation Synopsys Design Compiler Synthesis and Optimization Mitel UDC + Any Verilog Compliant simulator Full timing gate level pre-layout simulation Synopsys Test Compiler or Mentor Fastscan or Flextest Synopsys TestGen Scan overlay & ATPG Mitel TPV + Cadence Verifault Test Pattern


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1999 - Not Available

Abstract: No abstract text available
Text: VITAL Design Flow Composer Schematics Schematics VHDL SystemBuilder PMG PMG PMG models Megacells RAM/ROM models Any VHDL / VITAL Compliant simulator Behavioural Simulation Synopsys Design Compiler Synthesis and Optimization Mitel UDC + Any VHDL / VITAL Compliant simulator Full timing gate level pre-layout simulation Synopsys Test Compiler or Mentor Fastscan or Scan overlay & ATPG Synopsys TestGen Mitel TPV + Cadence Verifault Test Pattern Verification


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2002 - ICX 061

Abstract: ICX-061 CCD ICX ICX061 interline C7300 C7300-10
Text: High Performance Digital CCD Camera C7300-10 DATA SHEET SPECTRAL RESPONSE CHARACTERISTICS 60 Quantum efficiency (%) 50 40 30 20 10 0 400 600 800 Wavelength (nm) v Naturally air-cooled (compact) head 1000 * This is typical, not guaranteed. This is a high-resolution, high-sensitivity digital CCD camera that achieves a frame rate of 13 Hz (1280 × 1024 pixels) using a 20 MHz / pixel fast-scan clock. A partial scan function allows the user to select only a


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PDF C7300-10 SE-171-41 SICS1066E06 MAR/2002 ICX 061 ICX-061 CCD ICX ICX061 interline C7300 C7300-10
SCR-7204

Abstract: ARX-5000 SCR-2900DF RT-0518SW RT-0518SV esm elint Direction Finding system SCP-2960 SCR-2800
Text: spectrum display units, IF-to-tape converters and other ancillary equipment. B The SCR-2725 FastSCAN High


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PDF ARX-5000 SCP-2960 SCR-2900DF RDU-2960 RDU-2960DF SCR-7204 RT-0518SW RT-0518SV esm elint Direction Finding system SCR-2800
tdc 310

Abstract: HP9000 RS6000 tpl 624
Text: Fastscan V-System Design capture Simulation Simulation Timing analysis Fault grading Design


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PDF MG113P/114P/115P/73P/74P/75P MG113P/73P MG114P/74P MG115P/75P MG7xPB08 MG7xPB10 MG7xPB12 MG7xPB14 MG7xPB16 HP9000/7xx, tdc 310 HP9000 RS6000 tpl 624
1996 - O4N10

Abstract: 54XX 80C31 UTR100 UTR25 UTR35 UTR50 UTR75 Micromaster
Text: processes. Design analysis tools include : DESIGN ANALYSIS TOOL FastScan ®/ FlexTest ® / Test , , FastScan , FlexTest and DFT Advisor a re registered trademarks of Mentor Graphics Corporation Sun is a


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PDF 0E-10 UTR-1-11-96 O4N10 54XX 80C31 UTR100 UTR25 UTR35 UTR50 UTR75 Micromaster
80C196 users manual

Abstract: UTMC Gate Array IC5050 1553 VHDL 80C196 54XX UT100 UT200 UT25 UT50
Text: CompilerTM Viewlogic VantageTM FastScan / Flextest / DFTAdvisor® Test Compiler PlusTM Any , , FastScan , FlexTest and DFT Advisor are registered trademarks of Mentor Graphics Corporation Sun is a


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2000 - ARM dual port SRAM compiler

Abstract: DSPG synopsys dc ultra rm2510 STD130 STD110 IEEE1284 ARM940T ARM920T 16C550
Text: Insertion Synopsys TestGen, Synopsys TestComand ATPG piler, Synopsys TetraMax, Mentor Fastscan Static


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PDF STD130 STD130 24nW/MHz ARM920T/ARM940T, ARM dual port SRAM compiler DSPG synopsys dc ultra rm2510 STD110 IEEE1284 ARM940T ARM920T 16C550
1994 - 5962-96B02

Abstract: fpga radiation 80C31 "UNITED TECHNOLOGIES MICROELECTRONICS"
Text: processes. Design analysis tools include: DESIGN ANALYSIS TOOL FastScan ®/ FlexTest® / Test , Graphics, AutoLogic II, QuickSim II, QuickFault III, QuickVHDL, QuickGrade II, FastScan , FlexTest and DFT


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PDF 0E-10 64KPROM-2-6-96 5962-96B02 fpga radiation 80C31 "UNITED TECHNOLOGIES MICROELECTRONICS"
O4N10

Abstract: intel 80C31 UTR75 UTR50 UTR35 UTR25 UTR100 80C31 54XX Micromaster
Text: . Design analysis tools include: DESIGN ANALYSIS TOOL FastScan ®/ FlexTest® / DFT Advisor® Test , , FastScan , FlexTest and DFT Advisor are registered trademarks of Mentor Graphics Corporation Sun is a


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PDF 0E-10 O4N10 intel 80C31 UTR75 UTR50 UTR35 UTR25 UTR100 80C31 54XX Micromaster
2500k

Abstract: leon3 Micromaster UT54LVDS032LV UT54LVDS031LV 80C31 80C196 54XX hp 530 MIL-STD-1553 vhdl
Text: . 5 Mentor Graphics - ModelSim - FastScan Synopsys - Design Compiler (with Power Compiler) - , , Mentor Graphics, AutoLogic II, QuickSim II, QuickFault II, QuickHDL, QuickGrade II, FastScan , FlexTest


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PDF 25HBD 0E-10 2500k leon3 Micromaster UT54LVDS032LV UT54LVDS031LV 80C31 80C196 54XX hp 530 MIL-STD-1553 vhdl
tsmc 130nm metal process

Abstract: teradyne tiger aeroflex sram edac charactristics of cmos logic gates CCGA 472 teradyne flex tester leon3 synopsys dc-ultra 130NM cmos process parameters 80C31
Text: AEROFLEX Aeroflex supports libraries for: · Mentor Graphics - ModelSim - Tessent FastScan - Tessent , °C. Intel is a registered trademark of Intel Corporation Mentor, Mentor Graphics, FastScan , FlexTest and


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PDF UT130nHBD 130nm 0x10-10 tsmc 130nm metal process teradyne tiger aeroflex sram edac charactristics of cmos logic gates CCGA 472 teradyne flex tester leon3 synopsys dc-ultra 130NM cmos process parameters 80C31
2001 - designware i2c

Abstract: ARM dual port SRAM compiler NEC-V850 verilog code voltage regulator fastscan TMS320C54X TI ASIC gs40 LogicVision ARM946 ARM10
Text: Systems, Inc. Design Architect, DFTAdvisor, FastScan , Falcon Framework, FlexTest, MentorGraphics , FastScan , FlexText, DFT Advisor, LogicVision MEMBIST Fault grading Cadence Verifault Evaluation


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PDF SRST143 designware i2c ARM dual port SRAM compiler NEC-V850 verilog code voltage regulator fastscan TMS320C54X TI ASIC gs40 LogicVision ARM946 ARM10
1997 - UTMC

Abstract: 1553 VHDL O4N10 ami equivalent gates MIL-STD-1553 schematic fpga 54XX UT50 UT25 UT100 80C31
Text: Cadence Leapfrog QuickGradeII® Verilog HDL CompilerTM Viewlogic VantageTM FastScan , , FastScan , FlexTest and DFT Advisor are registered trademarks of Mentor Graphics Corporation Sun is a


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PDF MIL-PRF-38535 6CRH-1-7-97 UTMC 1553 VHDL O4N10 ami equivalent gates MIL-STD-1553 schematic fpga 54XX UT50 UT25 UT100 80C31
2000 - Samsung Soc processor

Abstract: DSPG 0.18-um synopsys dc ultra piler STD110 IEEE1284 ARM940T ARM920T 16C550
Text: Insertion Synopsys TestGen, Synopsys TestComand ATPG piler, Synopsys TetraMax, Mentor Fastscan Static


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PDF STD131 STD131 24nW/MHz ARM920T/ARM940T, Samsung Soc processor DSPG 0.18-um synopsys dc ultra piler STD110 IEEE1284 ARM940T ARM920T 16C550
2003 - ATMEL 644

Abstract: ATMEL 340 atmel edac virage IO33 ATC18RHA verilog code for half subtractor EIA-644 IBIS model Genibis Atmel circuit diagram of inverting adder ambit rev 7
Text: ( FastScan ), JTAG (BSDArchitect), BIST (MBIST-Architect) FE-ULTRA Cadence Floor-planning, physical


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PDF ATC18RHA ATMEL 644 ATMEL 340 atmel edac virage IO33 ATC18RHA verilog code for half subtractor EIA-644 IBIS model Genibis Atmel circuit diagram of inverting adder ambit rev 7
2001 - ARM dual port SRAM compiler

Abstract: DSPG teaklite ARM9TDMI ARM1020E samsung hdd UART 16C450 STD150 ARM940T ARM926EJ
Text: Insertion and Synopsys BSDCompiler, ATPG Synopsys TetraMax, Mentor Fastscan Static Timing Synopsys


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PDF STD150 STD150 ARM920T/ARM940T, ARM dual port SRAM compiler DSPG teaklite ARM9TDMI ARM1020E samsung hdd UART 16C450 ARM940T ARM926EJ
2004 - MPC8245CE

Abstract: AN2164 MPC8240 MPC8241 MPC8245
Text: No. Problem Description Impact Work Around 1.0 1.1 1.2 1.4 FastScan test , of scan test is not affected. Y - - - Reduced FastScan test coverage 2 , scan chain must be disabled for FastScan testing. Total test coverage is reduced to 25% coverage , memory-read-multiple commands. 1.1 MOTOROLA Freescale Semiconductor, Inc. Error No. 1: Reduced FastScan , disabled for FastScan testing. Total test coverage is reduced to 25% coverage. Projected Impact


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PDF MPC8245CE MPC8245/MPC8241 MPC8245/MPC8241 MPC8245 MPC8241 MPC8245CE AN2164 MPC8240
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