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HI3-0516-5Z Intersil Corporation 16-Channel/Differential 8-Channel, CMOS High Speed Analog Multiplexer; PDIP28; Temp Range: 0° to 70°
DG406DYZ-T Intersil Corporation Single 16-Channel/Differential 8-Channel, CMOS Analog Multiplexers; SOIC28; Temp Range: -40° to 85°C
DG406DYZ Intersil Corporation Single 16-Channel/Differential 8-Channel, CMOS Analog Multiplexers; SOIC28; Temp Range: -40° to 85°C
DG407DYZ-T Intersil Corporation Single 16-Channel/Differential 8-Channel, CMOS Analog Multiplexers; SOIC28; Temp Range: -40° to 85°C
DG407DYZ Intersil Corporation Single 16-Channel/Differential 8-Channel, CMOS Analog Multiplexers; SOIC28; Temp Range: -40° to 85°C
KAD2708C-10Q68 Intersil Corporation 8-Bit, 105MSPS Single-Channel ADC, LVCMOS Outputs; QFN68; Temp Range: -40° to 85°C

eMIOS channel is set up to drive the eTPU Datasheets Context Search

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2007 - eMIOS channel is set up to drive the eTPU

Abstract: MPC5554 AN2851 MPC5554 Memory mpc5554 emios timebase IC emios MPC5500 AN2864 UINT32
Text: the eTPU , and an eMIOS channel is set up to drive the eTPU channel using Single Action Output Compare , engine; 0b00001000 would link to Channel 8 on the current eTPU engine.) · link2 (uint32_t): This is a , up the eMIOS module, and initializes the eTPU according to the information in the my_etpu_config , number of counts for a specified eTPU channel . The eTPU IC function is based on the TPU IC function , application is dependent, to some extent, upon the service time (latency) of other active eTPU channels. This


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PDF MPC5554 AN2864, eMIOS channel is set up to drive the eTPU AN2851 MPC5554 Memory mpc5554 emios timebase IC emios MPC5500 AN2864 UINT32
2007 - AN2851

Abstract: SPWM IC IC link eTPU capture AN2864 mpc5554 emios MPC5500 MPC5554 eMIOS channel is set up to drive the eTPU emios
Text: function. The eMIOS module is configured to run with the same clock frequency as the eTPU , and an eMIOS channel is set up to drive the eTPU channel using Single Action Output Compare (SAOC) mode. The IC , CPU operation, sets up the eMIOS module, and initializes the eTPU according to the information in the , to other channels on completion of a certain number of counts for a specified eTPU channel . The , the service time (latency) of other active eTPU channels. This is due to the operational nature of


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PDF AN2851 MPC5554 AN2864, AN2851 SPWM IC IC link eTPU capture AN2864 mpc5554 emios MPC5500 eMIOS channel is set up to drive the eTPU emios
2007 - an3396

Abstract: AN2864SW MPC5534 MPC5500 Configuration and Initialization eMIOS channel is set up to drive the eTPU MPC500 MPC5500 MPC5561 decimation mpc5500r19
Text: is then moved back to system RAM. The component parts of the system (eQADC, eDMA, eTPU , and eMIOS , MPC5500 features up to 24 eMIOS channels. Each of the 24 unified channels is identical and can operate independently of the other channels to provide a timed input or output function. Each eMIOS channel pin is , The eMIOS channel 10 output is routed internally to the eQADC module. This is configured in the eQADC , second channel is used to move the eQADC results data to eTPU parameter RAM. This second channel is also


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PDF AN3396 MPC5500: MPC5500 an3396 AN2864SW MPC5534 MPC5500 Configuration and Initialization eMIOS channel is set up to drive the eTPU MPC500 MPC5561 decimation mpc5500r19
2007 - an3396

Abstract: MPC500 MPC5500 MPC5534 MPC5561 MPC5500 Configuration and Initialization eMIOS channel is set up to drive the eTPU emios
Text: prescaler and the channel prescaler to be 1. The period of the OPWFM signal is set to be 400 counts of the , is executed by the micro-engine in response to an eTPU channel requesting service. One means of , used to move the eQADC results data to eTPU parameter RAM. This second channel is also used to copy , . The component parts of the system (eQADC, eDMA, eTPU , and eMIOS ) as they pertain to the decimation , channels to provide a timed input or output function. Each eMIOS channel pin is multiplexed with


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PDF MPC5500: MPC5500 MPC5534 an3396 MPC500 MPC5561 MPC5500 Configuration and Initialization eMIOS channel is set up to drive the eTPU emios
2013 - 4/MPC5674F manual

Abstract: No abstract text available
Text: necessary to set the eMIOS counters to known values, configure each eMIOS channel for General Purpose Input , them allows both eMIOS and eTPU timebases to start running simultaneously. When the timebases are , (EMIOS_CCRn[UCPREN] = 1) to re-enable the unified channel prescaler. 7- Set the GTBE and GPREN bits in the , Queued Analog-to-Digital Converter (eQADC). If the eTPU clock is configured to be twice the frequency of , ) contains a single watchdog status bit for each of the 32 eTPU channels per engine. When this bit is set


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PDF MPC5674F 3M17W 3M17W MPC5674F 4/MPC5674F manual
2011 - ana610

Abstract: eMIOS channel is set up to drive the eTPU
Text: GPIO I/O P EMIOS1 eMIOS channel I/O A1 ETPUA1 eTPU A channel O A2 â , , Rev. 1 I/O P EMIOS3 eMIOS channel I/O A1 ETPUA3 eTPU A channel O — — — GPIO182 GPIO I/O P EMIOS4 eMIOS channel I/O A1 ETPUA4 eTPU , eMIOS channel I/O A1 ETPUA6 eTPU A channel O — — — GPIO185 GPIO I/O P EMIOS7 eMIOS channel I/O A1 ETPUA7 eTPU A channel O — — â


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PDF PXR40 PXR40 32-bit e200z7) 16-bit ana610 eMIOS channel is set up to drive the eTPU
2011 - MPXR4030VVU264

Abstract: GPIO144 ana610 ETPUB22 H4128 GPIO81 ETPUA18 iec 512-6 test 12d e200z7 instruction
Text: (eTPU2) Table 1 displays the PXR40 feature set . eMIOS eTPU eTPU_A eTPU_B PXR40 Microcontroller , A1 A2 G EMIOS0 ETPUA0 - GPIO179 EMIOS1 ETPUA1 - GPIO180 eMIOS channel eTPU A channel - GPIO eMIOS channel eTPU A channel - GPIO I/O O - I/O I/O O - I/O MH VDDEH4 -/WKPCFG - , EMIOS7 ETPUA7 - GPIO186 eMIOS channel eTPU A channel - GPIO eMIOS channel eTPU A channel - GPIO eMIOS channel eTPU A channel - GPIO eMIOS channel eTPU A channel - GPIO eMIOS channel eTPU A channel


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PDF PXR40 PXR40 32-bit e200z7) 16-bit MPXR4030VVU264 GPIO144 ana610 ETPUB22 H4128 GPIO81 ETPUA18 iec 512-6 test 12d e200z7 instruction
2008 - eMIOS channel is set up to drive the eTPU

Abstract: No abstract text available
Text: peripheral, CPU, or eDMA channel request Each eDMA channel can optionally send an interrupt request to the , -bit data bus, up to 22-bit address bus Selectable drive strength Configurable bus speed modes Bus monitor , Hardware Triggers ­ ­ Supports 4 external 8- to -1 muxes which can expand the input channel number , ) may have a separate supply in the 1.8 V to 3.3 V range (+/- 10%). 3. Terminology is O - output, I - , function on this pin is enabled when the NEXUSCFG pin is high and Nexus is configured to full port mode. On


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PDF SPC563M60L5 SPC563M60B2 32-bit eMIOS channel is set up to drive the eTPU
2004 - dspic spi

Abstract: MPC5500 Configuration and Initialization CTAR1 MPC55XX JTAG MPC5500 MC33394 IRQ14-15 CH11 CH10 mpc5554 emios
Text: ) functionality is selected, the DSPI module is configured to serialize eTPU and eMIOS output channels and , bus is routed internally to the inputs of the eTPU , eMIOS , or SIU interrupts. The data to be routed , is routed through to the eTPU , eMIOS channels, or to the SIU interrupts, as illustrated in Figure 14 , , eMIOS , and SIU interrupt signals. The purpose of serialization/ deserialization is to allow functional , Interface), and CSI (Combined Serial Interface) functionality. The SPI is a high speed ( up to system


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PDF AN2867 MPC5500 MPC55xx MPC55xx dspic spi MPC5500 Configuration and Initialization CTAR1 MPC55XX JTAG MC33394 IRQ14-15 CH11 CH10 mpc5554 emios
2005 - MPC5554 instruction set

Abstract: mpc5554 emios mpc5554 MPC5554P eMIOS channel is set up to drive the eTPU MPC5554 GPIO MPC5500 MPC5554 ADC mpc5554 ebi nexus 5001
Text: DSPI DSPI eMIOS 24 channel DSPI 3K Data eTPU eTPU RAM 32 32 channel 16K Code , from the customer power supply chip. POR block - Provides initial reset condition up to the voltage , Product Brief The MPC5554 is the first member of a family of next generation microcontrollers based on , applications. It is 100% user mode compatible (with floating point library) with the classic PowerPC instruction set . This document provides an overview of the MPC5554 microcontroller features, including the


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PDF MPC5554PB MPC5554 32-bit e200z6 64-channel MPC5554 instruction set mpc5554 emios MPC5554P eMIOS channel is set up to drive the eTPU MPC5554 GPIO MPC5500 MPC5554 ADC mpc5554 ebi nexus 5001
2005 - MPC5554 instruction set

Abstract: mpc5554 emios MPC5554 MPC5554 flexCAN MPC5554 "pin compatible" Nexus S JTAG pins MPC5500 nexus 5001 MPC5554 GPIO MPC5554P
Text: eSCI eTPU FMPLL SRAM eMIOS 24 channel DSPI 3K Data eTPU eTPU RAM 32 32 channel 16K , from the customer power supply chip. POR block - Provides initial reset condition up to the voltage , Product Brief The MPC5554 is the first member of a family of next generation microcontrollers based on , applications. It is 100% user mode compatible (with floating point library) with the classic PowerPC instruction set . This document provides an overview of the MPC5554 microcontroller features, including the


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PDF MPC5554PB MPC5554 32-bit e200z6 64-channel MPC5554 instruction set mpc5554 emios MPC5554 flexCAN MPC5554 "pin compatible" Nexus S JTAG pins MPC5500 nexus 5001 MPC5554 GPIO MPC5554P
2004 - dspic spi

Abstract: mpc551x SPI MPC55XX JTAG MPC5533 MPC5565 MPC5553 MPC5534 MPC5500 MPC5500 Configuration and Initialization mpc5554 ebi
Text: data received from the SPI bus is routed internally to the inputs of the eTPU , eMIOS , or SIU , Deserialized Mode Data from a received SPI frame is routed through to the eTPU , eMIOS channels, or to the , ) functionality. The SPI is a high speed ( up to system frequency/4), full-duplex, four-wire synchronous interface , modules is selected, the number of bits to be transferred can be up to 64. The SPI bus is a master/slave , serialize eTPU and eMIOS output channels and deserialize received data by routing it to the eTPU , eMIOS , or


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PDF AN2867 MPC5500 MPC55xx MPC55xx MPC551x MPC5533 MPC5534 MPC5553 MPC5554, dspic spi mpc551x SPI MPC55XX JTAG MPC5565 MPC5500 Configuration and Initialization mpc5554 ebi
2013 - e200z7

Abstract: MPC5674
Text: 0). 5- If it is necessary to set the eMIOS counters to known values, configure each eMIOS channel , following steps in sequence to synchronize the time base between the eTPU and the eMIOS : Mask Set Errata , out of the HALT state and return to normal operation. e818: EMIOS / ETPU : Global timebases not , EMIOS_CCRn register for each of the eMIOS channels (EMIOS_CCRn[UCPREN] = 1) to re-enable the unified channel , to peripherals does not work if the ratio of eTPU clock to peripheral clock is 2:1. Errata type


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PDF MPC5674F 3M17W 3M17W MPC5674F e200z7 MPC5674
2008 - MPC5674

Abstract: SPC5674F ANA14 ETPUA10 SPC5674 AN33 PPC5674F SPC5674FF3MVR3 MPC5674FRM MPC5674F manual
Text: = power dissipation in the package (W) The junction to ambient thermal resistance is an industry , . Which value is closer to the application depends on the power dissipated by other components on the , resistance is expressed as the sum of a junction to case thermal resistance and a case to ambient thermal , Enhanced modular input output system supporting 32 unified channels ( eMIOS ) with each channel capable of , numbers for sample parts. Refer to the product summary page on http://www.freescale.com for production


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PDF MPC5674F MPC5674F MPC5673F 32-bit e200z7) 16-bit MPC5674 SPC5674F ANA14 ETPUA10 SPC5674 AN33 PPC5674F SPC5674FF3MVR3 MPC5674FRM MPC5674F manual
2006 - MPC5566MZP80

Abstract: mpc5566mzp132 MPC500 MPC5500 MPC5566 MPC565 AN3816 MPC5566MVR132 10Mdc
Text: and undershoot of the input voltages of up to +/­ 2.0 volts is permitted for a cumulative duration of , frequency falls below f LOR. This frequency is measured on the CLKOUT pin with the divider set to , 82 -40° C to 125° C Speed is the nominal maximum frequency. Max Speed is the maximum speed , most useful for packages with heat sinks where some 90% of the heat flow is through the case to the , substantial amount of heat is dissipated from the top of the package. The junction to board thermal


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PDF MPC5566 MPC5566 MPC5566MZP80 mpc5566mzp132 MPC500 MPC5500 MPC565 AN3816 MPC5566MVR132 10Mdc
2009 - SC6672

Abstract: SPC5642 MPC5634 MPC5634M SC667 SPC5642AF2MLU3 MPC5642A SPC5642AF2MLU1 efp2 Reaction Module REACM
Text: serialize either eTPU channels, eMIOS channels or GPIO signals. The DSPI can be configured to serialize data , channel , 128 message objects, ECC · 1 eMIOS ­ 24 unified channels · 1 eTPU2 (second generation eTPU ) -32 , characteristics, refer to the device reference manual. 1.2 Description This microcontroller is a 32 , from the assertion of the interrupt request from the peripheral to when the processor is executing the , provides the capability to generate or measure events in hardware. The eMIOS module features include: ·


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PDF MPC5642A MPC5642A e200z4 SC6672 SPC5642 MPC5634 MPC5634M SC667 SPC5642AF2MLU3 SPC5642AF2MLU1 efp2 Reaction Module REACM
2012 - SPC5676

Abstract: e200z TMS 3617 npn transistor RCA 467 MPC567 N3305 MPC5676R GPIO456 MPC5676RRM UP-K26
Text: . There is no limit to how long after VDD powers up before VDDE/VDDEH must power up . The rise times on the , top-level block diagram of the MPC5676R. The purpose of the block diagram is to show the general , TEPBGA, these values can be different by a factor of two. Which value is closer to the application , to ambient thermal resistance (oC/W) RJC is device related and cannot be influenced by the user. The , down for power n-MOS gate 4.6 · · Power Up /Down Sequencing When VDDREG is tied to a nominal


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PDF MPC5676R MPC5676R 32-bit e200z7) 16-bit SPC5676 e200z TMS 3617 npn transistor RCA 467 MPC567 N3305 GPIO456 MPC5676RRM UP-K26
2009 - Not Available

Abstract: No abstract text available
Text: module (V2.1) up to 10 Mbit/s w/dual or single channel , 128 message objects, ECC • 1 eMIOS – 24 , serialize either eTPU channels, eMIOS channels or GPIO signals. The DSPI can be configured to serialize data , SIU to select either GPIO, eTPU or eMIOS bits for serialization The DSPI module can generate and , STM channels 1 Software Watchdog eMIOS 24 channels eTPU 32- channel eTPU2 Code memory , intervention from the core. Enhanced modular input-output system ( eMIOS ) Provides the functionality to


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PDF MPC5642A e200z4 MPC5642A
2011 - MPC5676R

Abstract: SPC5676R SPC5676 PPC5676R SMD transistor n25 npn transistor RCA 467 RCA 467 UH IR7353 VADC14 w25 transistor smd
Text: meet the current injection specification. There is no limit to how long after VDD powers up before VDDE , 2 shows a top-level block diagram of the MPC5676R. The purpose of the block diagram is to show the , values can be different by a factor of two. Which value is closer to the application depends on the power , thermocouple wire is placed flat against the package case to avoid measurement errors caused by cooling effects , Power Up /Down Sequencing When VDDREG is tied to a nominal 3.3V supply, VDD33 and VDDSYN must be both


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PDF MPC5676R MPC5676R 32-bit e200z7) 16-bit SPC5676R SPC5676 PPC5676R SMD transistor n25 npn transistor RCA 467 RCA 467 UH IR7353 VADC14 w25 transistor smd
2011 - MPC5676R

Abstract: No abstract text available
Text: the next paragraph. If VDD is powered up first, then all pads are loaded through the drain diodes to , is to show the general interconnection of functional modules through the crossbar switch and from , dissipation in the package (W) The junction to ambient thermal resistance is an industry standard value that , There is no power sequencing required among power sources during power up and power down in order to , , excessive current spikes, etc., the state of the I/O pins during power up /down varies according to Table 11


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PDF MPC5676R MPC5676R 32-bit e200z7) 16-bit
2005 - MPC5643A

Abstract: e200z4 MPC5644A gasoline direct injector e200z4 interrupt controller mpc5643 MPC5642A knock detection 176-QFP gasoline direct injection
Text: 192 KB 2-ch. FlexRay 3-ch. FlexCAN 32-ch. eTPU 24-ch. eMIOS Up to 40-ch. 12-bit 324 , -ch. FlexCAN 32-ch. eTPU 24-ch. eMIOS Up to 40-ch. 12-bit 324 TEPBGA 208 MAPBGA 176 LQFP , , FlexCANx3 performance while maintaining the low power SWT MPC564xA supports up to 300 DMIPS PIT , DEC x2 VGA The Qorivva MPC564xA's key features include a z4 core up to 150 MHz DSP capability , Up to 40-ch. 12-bit 324 TEPBGA 208 MAPBGA 176 LQFP cache, up to 192 KB SRAM, 32- channel


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PDF 32-bit MPC564xA 64-ch. e200z4 MPC563xM, 208MAP 176QFP MPC564xAFS MPC5643A e200z4 MPC5644A gasoline direct injector e200z4 interrupt controller mpc5643 MPC5642A knock detection 176-QFP gasoline direct injection
2006 - MPC5554

Abstract: IB23810 Flasher mode discrete test mpc551x MPC5534 MPC5533 HEDS-5640 AN3005 MPC554 motion quadrature encoder chip
Text: processing than the host CPU can achieve. This is partially due to the eTPU implementation, which includes , direct conversion of encoder output to commutation sectors. The conversion is provided by the eTPU . The , parameters of the QD eTPU function are set to values that correspond to sector borders and the position counter is set to zero, see Figure 10. When the motor starts to move, the position counter starts to , voltage vector is set to be orthogonal to the alignment position. The resultant direction of the voltage


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PDF MPC5554 MPC5554 AN3005 MPC551x MPC5533 MPC5534 MPC5553 MPC5554, MPC5565 IB23810 Flasher mode discrete test mpc551x HEDS-5640 AN3005 MPC554 motion quadrature encoder chip
2012 - SPC564A70

Abstract: SPC564A74 SPC564A80B4 SPC563M64 INTERRUPT VECTORS SPC564A74B4 SPC564A SPC56 manual e200z448
Text: FlexRay module (V2.1) up to 10 Mbit/s with dual or single channel and 128 message objects and ECC , FlexCAN with 64 messages each 1 × FlexRay module (V2.1) up to 10 Mbit/s with dual or single channel and , as part of a triggered data acquisition protocol EVTO pin is used to communicate to the external tool , (TCD) for the channels. This implementation is utilized to minimize the overall block size. The eDMA , requests, the time from the assertion of the interrupt request from the peripheral to when the processor is


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PDF SPC564A74B4, SPC564A74L7 SPC564A80B4, SPC564A80L7 32-bit e200z4 24-entry SPC564A70 SPC564A74 SPC564A80B4 SPC563M64 INTERRUPT VECTORS SPC564A74B4 SPC564A SPC56 manual e200z448
2008 - 416-ball

Abstract: A1K10 MPC 5674F MPC5674F instruction set SPC5674F
Text: one figure. The same information is shown split into to halves in Figure 4 through Figure 5. 1 A VSS , factor of two. Which value is closer to the application depends on the power dissipated by other , , the thermal resistance is expressed as the sum of a junction to case thermal resistance and a case to , is measured per JESD51-2 specification using a 40 gauge type T thermocouple epoxied to the top center , wire extending from the junction. The thermocouple wire is placed flat against the package case to


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PDF MPC5674F MPC5674F MPC5673F 32-bit e200z7) 16-bit 416-ball A1K10 MPC 5674F MPC5674F instruction set SPC5674F
2006 - TCD42

Abstract: 0x05d0 TE 2395 TM 1812 mpc5554 emios e200z6 pt 2399 echo MPC565 MPC5554 circuit diagram of half adder
Text: LDCForFreescaleSemiconductor@hibbertgroup.com Information in this document is provided solely to enable system and software implementers to , hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Freescale Semiconductor reserves the right to make changes without further notice , components in systems intended for surgical implant into the body, or other applications intended to support , /2007 How to Reach Us: Home Page: www.freescale.com E-mail: support@freescale.com USA/Europe or


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PDF MPC5565 MPC5565 CH370 MPC5565RM TCD42 0x05d0 TE 2395 TM 1812 mpc5554 emios e200z6 pt 2399 echo MPC565 MPC5554 circuit diagram of half adder
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