The Datasheet Archive

Top Results (6)

Part Manufacturer Description Datasheet Download Buy Part
LTC5541IUH#PBF Linear Technology LTC5541 - 1.3GHz to 2.3GHz High Dynamic Range Downconverting Mixer; Package: QFN; Pins: 20; Temperature Range: -40°C to 85°C
LTC4400-2EMS8 Linear Technology LTC4400 - RF Power Controllers with 450kHz Loop BW and 45dB Dynamic Range; Package: MSOP; Pins: 8; Temperature Range: -40°C to 85°C
LTC1758-2EMS#PBF Linear Technology LTC1758-1 - RF Power Controllers with 250kHz Control Loop Bandwidth and 40dB Dynamic Range; Package: MSOP; Pins: 10; Temperature Range: -40°C to 85°C
LTC4401-2EMS8#TRPBF Linear Technology LTC4401-2 - RF Power Controllers with 250kHz Loop BW and 45dB Dynamic Range; Package: MSOP; Pins: 8; Temperature Range: -40°C to 85°C
LTC5505-2ES5#TRPBF Linear Technology LTC5505 - RF Power Detector with Buffered Output and >40dB Dynamic Range; Package: SOT; Pins: 5; Temperature Range: -40°C to 85°C
LT5537EDDB#TRM Linear Technology LT5537 - Wide Dynamic Range RF/IF Log Detector; Package: DFN; Pins: 8; Temperature Range: -40°C to 85°C

dynamic dx pmb2 Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
dynamic dx pmb2

Abstract: wheelchair joystick circuit power wizard 1.1 fault codes FC120N2 dxbus brake failure indicator wheelchair wheelchair circuit circuit diagram of battery operated wheelchair wheelchair motor 24v
Text: No. 63824, Issue 2. July 1998 TM DX Power Module (PMB, PMB1, PMB2 , PMB-S) Installation , installation; ! The DX Hand Held Programmer ( DX HHP) Manual; ! The Dynamic Wizard Installation , programming. This Programming section, the DX HHP Manual, and the Dynamic Wizard Manual/On-line Help must be , generally best for Dynamic to supply DX Modules with a standard set up, and for the wheelchair , are available, the Wizard and the DX HHP. Dynamic Wizard The Wizard is a PC based tool suited to


Original
PDF GBK63824 259th dynamic dx pmb2 wheelchair joystick circuit power wizard 1.1 fault codes FC120N2 dxbus brake failure indicator wheelchair wheelchair circuit circuit diagram of battery operated wheelchair wheelchair motor 24v
2007 - MARKING EA1 sot-23

Abstract: SOT-23 EA1 EA2 SOT-23 "Shunt Regulator" e43a sot 23 EA1 E43B SOT23 voltage regulator 10V MARKING CODE EA1 sot ea1 EA1 sot-23
Text: () Fig.10- Dynamic Impedance vs. Frequency Frequency f (Hz) Rev. A/ DX 2007-06-04 , operating current range of 1.0 to 100mA with a typical dynamic impedance of 0.15 to 0.22. The , Low Dynamic Output Impedance: 0.15 to 0.22 Typical Operating Current from 1.0mA to 100mA Low Output , )-TAITRON (800)-824-8766 (800)-TAITFAX (800)-824-8329 (661)-257-6060 (661)-257-6415 Rev. A/ DX , -89 Rev. A/ DX 2007-06-04 www.taitroncomponents.com Page 2 of 14 Shunt Regulator LM431 Block


Original
PDF LM431 LM431A LM431B 100mA MARKING EA1 sot-23 SOT-23 EA1 EA2 SOT-23 "Shunt Regulator" e43a sot 23 EA1 E43B SOT23 voltage regulator 10V MARKING CODE EA1 sot ea1 EA1 sot-23
CY7C954DX

Abstract: CY7C924DX CY7C924DX-AC CY7C9689 cypress part marking
Text: Cypress Semiconductor Qualification Report QTP# 99041 VERSION 1.0 November, 1999 HOTLINK DX , DX Family - R42LHDHA, Fab 4 Device: CY7C924DX/954DX/9689 Package: 100-pin TQFP QTP# 99041, V , Hotlink DX family (CY7C954DX and CY7C9689), fabricated in Fab 4 using RAM42LHDHA technology. Marketing , /R42LHDHA Cypress Semiconductor, Inc. HOTLink DX Family - R42LHDHA, Fab 4 Device: CY7C924DX/954DX/9689 , packages availability. Cypress Semiconductor, Inc. HOTLink DX Family - R42LHDHA, Fab 4 Device


Original
PDF CY7C924DX CY7C954DX CY7C9689 R42LHDHA, CY7C924DX/954DX/9689 100-pin CY7C924DX CY7C954DX 30C/60 CY7C924DX-AC CY7C924DX-AC CY7C9689 cypress part marking
1997 - 20K potentiometer

Abstract: TS10K AS1503 AS1502 AS1501-T AS1501 AS1500-T AS1500 27BSC "Digital Potentiometer"
Text: VIL = 0V, VCC = 5.5V 8 (CMOS) Dynamic Characteristics BW_10k Conditions Resistor Noise , result in minimum power dissipation. 9. All dynamic characteristics are guaranteed by design and not subject to production test. All dynamic characteristics use VCC=5V. AS1502 / AS1503 ­ SPECIFICATIONS , Supply Current (TTL) Power Dissipation 8 (CMOS) Power Supply Suppression Ratio Dynamic , dissipation. 9. All dynamic characteristics are guaranteed by design and not subject to production test. All


Original
PDF AS1500/AS1501/AS1502/AS1503 AS1500 10MHz. AS1501 AS1502 AS1503 20K potentiometer TS10K AS1501-T AS1500-T 27BSC "Digital Potentiometer"
1997 - Not Available

Abstract: No abstract text available
Text: µW dB dB -52 -25 Dynamic Characteristics BW_10k BW_20k THDW tS_10k tS_20k eNWB_10k eNWB , result in minimum power dissipation. 9. All dynamic characteristics are guaranteed by design and not subject to production test. All dynamic characteristics use VCC=5V. AS1502 / AS1503 ­ SPECIFICATIONS , ni PSSR ch Power Supply Suppression Ratio 9 VCC = 5V+0.5VP sine wave @ 1kHz Dynamic , dynamic characteristics are guaranteed by design and not subject to production test. All dynamic


Original
PDF AS1500/AS1501/AS1502/AS1503 AS1500 10MHz. AS1501 AS1502 AS1503
imsg171

Abstract: inmos IMSG171 adv7146kn66 ADV7146KN50 ADV478 ADV476 ADV7146 htv 873 bt478 ADV7148
Text: -Bit True Color Performance Dynamic Palette Load (DPL) Function Plug-in Upgrade for Standard VGA RAM-DACs , a combination of the antialiasing function and a unique dynamic palette load FUNCTIONAL BLOCK , Parts 50 & 35 MHz Parts Typically 200 mA f = 1 kHz, COMP = 0.1 tiF DYNAMIC PERFORMANCE Clock and Data , palette can also be reserved for the DPL op code. The dynamic palette further expands the number of colors , CopyRight 2003 ADV7141 /AD V7146/ADV7148 DYNAMIC PALETTE LOADING (DPL) The two Advanced CEG encoding


OCR Scan
PDF V7141 V7146/ADV7148* 24-Bit ADV478/AD ADV476 171/176T 8514/At RS-343A/RS-170 03C9h imsg171 inmos IMSG171 adv7146kn66 ADV7146KN50 ADV478 ADV476 ADV7146 htv 873 bt478 ADV7148
2013 - Not Available

Abstract: No abstract text available
Text: Storage System The Economy Storage ETERNUS DX S2 DISK STORAGE SYSTEMS Fujitsu’s second generation of ETERNUS DX disk storage systems, ETERNUS DX S2, are The Flexible Data Safe for Dynamic , to ensure business continuity is maintained. ETERNUS DX S2 models are comprehensive disk storage , operation across the entire ETERNUS DX range. In virtualized IT environments in particular, ETERNUS SF perfectly integrates the powerful ETERNUS DX disk storage with minimal administration effort. Page 1 of


Original
PDF
Not Available

Abstract: No abstract text available
Text: 0.25 Dynamic Power Supply Current3 mA/ MHz Vcc= MAX, O ne Input Toggling, 50% Duty Cycle, O , = 3 4V) D h = Duty Cycle for TTL Inputs High Nt = Number of TTL Inputs at Dh lC D = Dynamic , in milliamps and all frequencies are in megahertz. = ^ u ie s c e n t * I nputs + ^ q dynamic , €” — — — — ns ns *S Dx to PCLK MODE to PCLK Yx to DCLK MODE to DCLK SDÌ to , ns D C LK to Dx ns 8 5 ‘ PL Z ÜÊŸto Yx DCLK to Dx — — 20 35 â


OCR Scan
PDF CY29FCT818T AM29818 T818T Y29FC IL-STD-883, 818AT 818BT AE1710
dx 400

Abstract: BE2000 AQRS 2910A
Text: Supplies: + 12V, + 5V, - 5 V 78dB Dynamic Range, with Resolution Equivalent to 12-Bit Linear Conversion , Switching Systems -Subscriber Carrier/Concentrators The wide dynamic range of the 2910A (78dB) and the , Dx No Connects Ground Output Ground return common to the logic power supply, Vcc. Output of the , signal goes low while the Codec is transmitting an 8-bit PCM word on the Dx lead. (Timeslot information used for diagnostic purposes and also to gate the data on the Dx lead.) Open drain output. + 5V ± 5


OCR Scan
PDF 12-Bit dx 400 BE2000 AQRS 2910A
2013 - Not Available

Abstract: No abstract text available
Text: Storage System The Flexible Data Safe for Dynamic Infrastructures. ETERNUS DX S2 DISK STORAGE SYSTEMS Fujitsu’s second generation of ETERNUS DX disk storage systems, ETERNUS DX S2, are The Flexible Data Safe for Dynamic Infrastructures. Enterprise-proven capabilities protect data assets across all types , the highest system reliability to ensure business continuity is maintained. ETERNUS DX S2 models , point administration, easy data protection and efficient operation across the entire ETERNUS DX range


Original
PDF
2013 - Not Available

Abstract: No abstract text available
Text: Storage System The Flexible Data Safe for Dynamic Infrastructures. ETERNUS DX S2 DISK STORAGE SYSTEMS Fujitsu’s second generation of ETERNUS DX disk storage systems, ETERNUS DX S2, are The Flexible Data Safe for Dynamic Infrastructures. Enterprise-proven capabilities protect data assets across all types , the highest system reliability to ensure business continuity is maintained. ETERNUS DX S2 models , upgrades lead seamlessly to the next higher ETERNUS DX system, thus ensuring flexibility and investment


Original
PDF
CL-PD6729

Abstract: No abstract text available
Text: management fea tures, including Low-power Dynamic mode, Suspend mode, and control of PCMCIA socket power. Low-power Dynamic mode is transparent to the PCI bus. After reset, the CL-PD6729 is configured for Low-power Dynamic mode. This mode can be turned off by setting Misc Control 2 register, bit 1 to a `O '. When in Low-power Dynamic mode, periods of inac tivity (no activity on the PCMCIA bus and system accesses to chip , # Level Suspend Mode (Bit 2) 0 0 Low-Power Dynamic Mode (Bit 1) 1 0 Functionality Low-power


OCR Scan
PDF CL-PD6729 CL-PD6729
dx 400

Abstract: 2911A-1
Text: , +5V, - 5 V 66 dB Dynamic Range, with Resolution Equivalent to 11-Bit Linear Conversion Around Zero 1 , Switching Systems - Subscriber Carrier/Concentrators The wide dynamic range of the 2911A (66 dB) and the , D r , DC Dx . T5x C L K c, C L K X, C L K r FS x, F S r AUTO V BB Vcc V DD PON GRDA GROD NC O "« « , the Dx lead. (Timeslot information used for diagnostic purposes and also to gate the data on the Dx , VFr Output Output 10 11 12 13 NC NC GRDD Dx No Connects Ground Output 14 TSi


OCR Scan
PDF 911A-1 11-Bit 911A-1 dx 400 2911A-1
AQRS

Abstract: PCM encoder pcm highway codec 2911A-1
Text: Supplies: + 12V, + 5V, -5V 66 dB Dynamic Range, with Resolution Equivalent to 11-Bit Linear Conversion , Switching Systems • Concentration — Subscriber Carrier/Concentrators The wide dynamic range of the 2911A , Output Dr. dc Digital Input Dx . T5x Digital Output CLKc, CLKX, CLKr Clock Input fsx, fsr Frame Sync Input , Ground return common to the logic power supply; Vcc- 13 Dx Output Output of the transmit side onto the , low while the Codec is transmitting an 8-bit PCM word on the Dx lead. (Timeslot information used for


OCR Scan
PDF 911A-1 11-Bit AQRS PCM encoder pcm highway codec 2911A-1
G733

Abstract: TOSA Mbps 2910A-4 G711 12V,5 pin RELAY
Text: Dynamic Range, with Resolution Equivalent to 12-Bit Linear Conversion Around Zero ■±5% Power Supplies , The wide dynamic range of the 2910A (78dB) and the minimal conversion time (80)isec minimum) make it , , Vcc- 14 Dx Output Output of the transmit side onto the send PCM highway (serial bus). The 8-bit PCM , while the Codec is transmitting an 8-bit PCM word on the DX lead. (Timeslot information used for diagnostic purposes and also to gate the data on the Dx lead.) TTL Interface, open drain output. 16 vcc


OCR Scan
PDF 910A-4 12-Bit G733 TOSA Mbps 2910A-4 G711 12V,5 pin RELAY
G711

Abstract: G733
Text: % Power Supplies: +12V, +5V, -5V 78dB Dynamic Range, with Resolution Equivalent to 12-Bit Linear , Office Switching Systems • Concentration —Subscriber Carrier/Concentrators The wide dynamic range , transmitting an 8-bit PCM word on the Dx lead. (Timeslot information used for diagnostic purposes and also to gate the data on the Dx lead.) Open drain output. 16 Vcc Power + 5V ±5%, referenced to GRDD. 17 CLKr , bit of the PCM word on the Dx lead, on signaling frames. TTL interface. 22 Vbb Power —5V± 5


OCR Scan
PDF 12-Bit G711 G733
1994 - OPT101W

Abstract: 00E-6 OPT101 OPT101P 9E-12
Text: dynamic behavior * * * * Behavior that is not modeled includes: * Changes in parameters over , capacitance dc vout 53 dx de 54 vout dx dlp 90 91 dx dln 92 90 dx dp 4 vs dx egnd 99 0 poly(2) (vs,0 , vs 4 dc 100u fdrain vs 4 vdrain 1 .model dx D(Is=800.0E-18) .model qx PNP(Is=800.0E-18 Bf


Original
PDF OPT101P 14kHz, 061E9 2E-12 00E-6 100e3 0E-18) 0E-18 OPT101W 00E-6 OPT101 9E-12
2009 - QFn Package tray

Abstract: QFN-64 CDK2307AILP64 CDK2307BILP64 CDK2307CILP64 TQFP-64 CDK2307
Text: , FIN0 = 9.9MHz -105 dB FIN = 2MHz SFDR HD2 HD3 Spurious Free Dynamic Range Second , HD2 HD3 Spurious Free Dynamic Range Second order Harmonic Distortion Third order Harmonic , 70.5 FIN = 40MHz FIN = 8MHz SFDR Spurious Free Dynamic Range 81 dBc FIN = 20MHz 75 , Spurious Free Dynamic Range 69.5 77 dBc FIN = 20MHz 74 78 dBc FIN = 30MHz 78 , recommended to keep the load on output data bits as low as possible to keep dynamic currents and resulting


Original
PDF CDK2307 20/40/65/80MSPS, 12/13-bit 13-bit 20/40/65/80MSPS 30/55/85/102mW 80MSPS 64-pin TQFP-64 CDK2308 QFn Package tray QFN-64 CDK2307AILP64 CDK2307BILP64 CDK2307CILP64 CDK2307
Not Available

Abstract: No abstract text available
Text: Cycle, Outputs Open, One Bit Toggling at f, = 5MHz, OEY = GND. V,N = 3.4V or V1 = GND M Dynamic , L Inputs High Nt • Number of T T L Inputs at DH - Dynamic Current Caused by an Input , PD tS PCLK TO Yx MODE to SDO SDÌ to SDO DCLK to SDO Dx to PCLK MODE to PCLK Yx to DCLK MODE to DCLK SDÌ to DCLK DCLK to PCLK PCLK to DCLK Dx to PCLK MODE to PCLK Yx to DCLK MODE to , — Viz OEYtoYx DCLK to Dx V hZ OEYtoYx DCLK to Dx — OEYtoYx DCLK to Dx â


OCR Scan
PDF P29FCT818T/AT/BT/CT AM29818 MIL-STD-883, 818AT 818BT 818CT AE1710-4
2009 - CDK2307AILP64

Abstract: CDK2307AITQ64 CDK2307BILP64 CDK2307CILP64 CDK2307DILP64 TQFP-64
Text: bits FIN = 2MHz SFDR HD2 HD3 Spurious Free Dynamic Range Second order Harmonic , bits FIN = 2MHz SFDR HD2 HD3 Spurious Free Dynamic Range Second order Harmonic , Signal to Noise and Distortion Ratio 70.5 FIN = 40MHz FIN = 8MHz SFDR Spurious Free Dynamic , Noise and Distortion Ratio FIN = 8MHz SFDR Spurious Free Dynamic Range 69.5 77 dBc , to keep dynamic currents and resulting switching noise at a minimum. CDK2307 Dual, 20/40/65


Original
PDF CDK2307 20/40/65/80MSPS, 12/13-bit 13-bit 20/40/65/80MSPS 30/55/85/102mW 80MSPS 64-pin TQFP-64 CDK2308 CDK2307AILP64 CDK2307AITQ64 CDK2307BILP64 CDK2307CILP64 CDK2307DILP64
2009 - Not Available

Abstract: No abstract text available
Text: dBc FIN 71 FS/ 2 FIN = 20MHz FIN = 2MHz SFDR HD2 Spurious Free Dynamic Range , FIN 71 FS/ 2 FIN = 30MHz FIN = 2MHz SFDR HD2 Spurious Free Dynamic Range Second , Dynamic Range 75 FIN = 20MHz FIN FS/ 2 FIN = 40MHz 77 dBc -95 dBc -95 dBc , Distortion Ratio FIN FS/ 2 FIN = 8MHz SFDR Spurious Free Dynamic Range 78 dBc FIN = , dynamic currents and resulting switching noise at a minimum. © 2009 CADEKA Microcircuits LLC


Original
PDF CDK2307 80MSPS, 13-bit 13-bit 20/40/65/80MSPS 30/55/85/102mW 80MSPS 64-pin TQFP-64 CDK2308
2009 - Not Available

Abstract: No abstract text available
Text: Dynamic mode (12 I/Os + 4 CS) I LQFP64 package I PCM in HI-Z mode LQFP64 The PCM , dynamic mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . , VDD 9 40 CAP DR 10 39 VFRO1 DX 11 38 VFXI1 TSX 12 37 VCC1 , VEE3 VFRO2 FS/FS0 MCLK TSX DX D98TL405 STLC5046 Block diagram and pin connection , as bit clock and it is used to shift data into and out of the DR and DX pins. 13 MCLK DI


Original
PDF STLC5046 LQFP64 LQFP64
2009 - tip ff 0401

Abstract: E-STLC5046 D311 transistor LQFP64 STLC3080 STLC5046 st chn d29
Text: loopbacks SLIC control port Static mode (16 I/Os) Dynamic mode (12 I/Os + 4 CS , application circuit with STLC3080 without metering pulse injection and I/O pins in dynamic mode. . . . . . . , CAP DR 10 39 VFRO1 DX 11 38 VFXI1 TSX 12 37 VCC1 MCLK 13 , FS/FS0 MCLK TSX DX D98TL405 STLC5046 Block diagram and pin connection 1.1 Pin , into and out of the DR and DX pins. 13 MCLK DI 12 TSX ODO Transmit time slot


Original
PDF STLC5046 LQFP64 LQFP64 tip ff 0401 E-STLC5046 D311 transistor STLC3080 STLC5046 st chn d29
2009 - CDK2307

Abstract: No abstract text available
Text: FIN = 8MHz 71 11.7 bits FIN = 2MHz SFDR HD2 HD3 Spurious Free Dynamic Range , Dynamic Range Second order Harmonic Distortion Third order Harmonic Distortion FIN = 8MHz 75 , = 40MHz FIN = 8MHz SFDR Spurious Free Dynamic Range 81 dBc FIN = 20MHz 75 84 , Ratio 69.5 FIN = 8MHz SFDR Spurious Free Dynamic Range 77 dBc FIN = 20MHz 74 78 , . However, it is recommended to keep the load on output data bits as low as possible to keep dynamic


Original
PDF CDK2307 20/40/65/80MSPS, 12/13-bit 13-bit 20/40/65/80MSPS 30/55/85/102mW 80MSPS 64-pin CDK2308 CDK2307
dx 400

Abstract: 2911A-1
Text: On-Chip Time-Slot Computation Simple Direct Mode Interface When Fixed Timeslots Are Used 66 dB Dynamic , Systems Concentration - Subscriber Carrier/Concentrators The wide dynamic range of the 2911A (66 dB , C O N F IG U R A T IO N BLOCK D IA G R AM CAP I*. CAP 2* VFn Db 0 c Dx . îâ * CLKC.C L K , CLKr , -bit PCM word on the Dx lead. (Timeslot information used for diagnostic purposes and also to gate the data on the Dx lead.) TTL interface, open drain output. + 5 V ± 5%, referenced to GRDD. Master receive


OCR Scan
PDF 911A-1 11-Bit 911A-1 dx 400 2911A-1
Supplyframe Tracking Pixel