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DC1513B-AD Linear Technology BOARD EVAL LTM9004-AD
LTC1746IFW#TR Linear Technology IC ADC SMPL 14BIT 25MSPS 48TSSOP
LTC1742CFW#TR Linear Technology IC ADC SMPL 14BIT 65MSPS 48TSSOP
LTC1290CCJ Linear Technology IC 12-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, CDIP20, CERDIP-20, Analog to Digital Converter
LTC2632-LMI8#TRPBF Linear Technology IC 8-BIT DAC, PDSO8, PLASTIC, LEAD FREE, MO-193, TSOT-8, Digital to Analog Converter
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digital code lock schematic diagram Datasheets Context Search

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ICAR capacitors

Abstract:
Text: DETECTOR DIGITAL INNER LOOP I2C-BUS lock Fig.9 Schematic diagram of the carrier recovery. 1996 , HALF NYQUIST FILTER I2C-BUS I2C-BUS I2C-BUS MGG168 Fig.4 Schematic diagram of the , input data rate is twice the symbol rate. The schematic diagram of this detector is illustrated in Fig , MGG172 Fig.11 Schematic diagram of the clock recovery. 1996 Nov 19 15 Philips Semiconductors , a range of ±20 dB in gain variance. A schematic diagram of the AGC is illustrated in Fig


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PDF TDA8046 ICAR capacitors receiver QAM schematic diagram receiver QAM schematic diagram on tda8046 BER SER 32QAM modulation icar capacitor ldt0 MGG170 "digital baseband" receiver demodulator LPF amplifier ADC compensate AN96048 icar capacitor datasheet
receiver QAM schematic diagram

Abstract:
Text: i2c-bus half nyquist filter half nyquist filter i2c-bus Fig.4 Schematic diagram of the quadrature , i i l2c-bus MGG171 Fig.9 Schematic diagram of the carrier recovery. 1996 Nov 19 13 Philips , the symbol rate. The schematic diagram of this detector is illustrated in Fig. 11. The clock , <*v—«J ► to vcxo from vcxo Fig. 11 Schematic diagram of the clock recovery. 1996 Nov 19 15 , in gain variance. A schematic diagram of the AGC is illustrated in Fig.13. If the SAW filter does


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PDF TDA8046 receiver QAM schematic diagram AD B1 demodulator Demodulator 256 QAM tv schematic diagram PHILIPS QFP64 ICAR capacitors equalizer lms digital clock and carrier recovery ath4 AG01
receiver QAM schematic diagram

Abstract:
Text: filter "TT i2c-bus Fig.4 Schematic diagram of the quadrature demodulator and half Nyquist filter , .9 Schematic diagram of the carrier recovery. 1996 Jul 23 ■711üflEb GlGb353 ITT 13 Philips , . Consequently, the input data rate is twice the symbol rate. The schematic diagram of this detector is , slope. For characteristics see Chapter 13. Fig.11 Schematic diagram of the clock recovery. 1996 Jul , control the AGC loop. The implemented AGC covers a range of ±20 dB in gain variance. A schematic diagram


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PDF TDA8046 receiver QAM schematic diagram 16 qam demodulator 16 QAM receiver block diagram deModulator 128 QAM AN96048 32QAM BER SER 32QAM modulation D10B34 tv schematic diagram PHILIPS 25 Demodulator 256 QAM
2013 - AK1590

Abstract:
Text: Board Schematic 32 Block Diagram by Power Supply , . This is called digital lock detect. 5.1 Analog Lock Detect In analog lock detect, the phase detector , output Fig. 7 Analog Lock Detect Operation MS1478-E-00 15 2012/10 [AK1590] 5.2 Digital Lock Detect In the digital lock detect, the [LD] pin outputs "Low" every time when the frequency is set , formula, the digital lock detect cannot be used. In such case, the analog lock detect should be used


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PDF AK1590] AK1590 AK1590 1000MHz. 18-bit 1000MHz MS1478-E-00
rj11 plug wiring diagram

Abstract:
Text: analog and digital processing 20 Relevant information 5.1 Microcode download Figure 5.0 I2C compatible PC interface wiring diagram 21 22 4.3 5.0 Schematic Information 4.1.1 EVAL-ADV7174/79 , 2-1 Board-Level Block Diagram Table 2-1 EVAL-ADV7174/79EBM output options System-Level Description Figure 2-2 System-Level Block Diagram 7 8 9 Hardware Configuration 10 3.1 10 Hardware , Requirements 11 12 13 14 Schematics 15 4.1 15 4.2 16 Schematic Diagrams 4.2.1


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PDF ADV7174/79 EVAL-ADV7174/79 EVAL-ADV7174/79EBM rj11 plug wiring diagram Analog devices marking Information rj11 plug wiring diagram to bnc adu812 rgb led video colour display marking J1 RJ11 to RS232 RJ11 p2 encoder 421 configuration J10B
2010 - AK1543

Abstract:
Text: TEST3 18bit LOCK DETECT PULSE SWALLOW COUNTER TEST2 Fig. 1 Block Diagram , is called digital lock detect. 4.1 Analog Lock Detect In analog lock detect, the phase detector , [AK1543] 4.2 Digital Lock Detect {LD} in is set to "0 {LDCKSEL[1:0]} in is set to "00" In the digital lock detect, the [LD] pin outputs is "Low" every time when the frequency is , Fig. 8 Digital Lock Detect Operation MS1206-E-00 15 2010/6 [AK1543] Unlock([LD]="Low"


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PDF AK1543] AK1543 1300MHz AK1543 1300MHz. 18-bit MS1206-E-00 schematic diagram of person counter TlE40 AKM SEMICONDUCTOR digital code lock schematic diagram schmidt trigger
2010 - AK1541

Abstract:
Text: set to "0", the lock detect signal is output according to the on-chip logic. This is called digital , Fig. 7 Analog Lock Detect Operations MS1043-E-03 14 2010/11 [AK1541] 4.2 Digital Lock , dividing ratio 6.) In the digital lock detect, the [LD] pin outputs is "Low" every time when the , frequency. However, if the VCO frequency does not satisfy either of the following formula, the digital lock , , 33.6MHz / (2+1) x 7 = 78.4MHz As a result, the digital lock detect cannot be used if the VCO frequency is


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PDF AK1541] AK1541 600MHz AK1541 20MHz 600MHz. 18-bit MS1043-E-03 digital code lock schematic diagram 20MH electronic lock schematic diagram MS1043-E-03
2010 - tcl 110011 ic

Abstract:
Text: is called digital lock detect. 4.1 Analog Lock Detect In analog lock detect, the phase detector , ] 4.2 Digital Lock Detect In the digital lock detect, the [LD] pin outputs is "Low" every time when the , ] 0100 LDCNTSEL[1:0] : Counter value for lock detect The counter value for digital lock detect can be , : Selects analog or digital for Lock Detect. D13 Function 0 Digital lock detect mode 1 , power-saving features On-chip lock detection feature of PLL: Direct output to the PFD (Phase frequency


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PDF AK1542] AK1542 600MHz AK1542 MS1065-E-01 tcl 110011 ic IC 1691 AI CIRCUIT DIAGRAM 7415 ic pin details 4558 PIN AKM 4558 TLE 4943 IC 4558 CIRCUIT DIAGRAM ic 4558 pin diagram 4558 schematic diagram
2013 - AK1542

Abstract:
Text: Filter Schematic ". The [SWIN] pin could be open when the fast Lock Up feature is not used. Note 3 , logic. This is called " digital lock detect". 4.1 Analog Lock Detect In analog lock detect, the phase , Digital Lock Detect In the digital lock detect, the [LD] pin outputs is "Low" every time when the , , LD outputs "High" LD output Fig. 8 Digital Lock Detect Operations MS1399-E-00 - 15 - , value for lock detect The counter value for digital lock detect can be set. D18 0 0 1 1 D17 0 1 0 1


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PDF AK1542A] AK1542A 600MHz AK1542A MS1399-E-00 AK1542
phase*detector

Abstract:
Text: Mblt/s Using (1,7) Code . • VM5327 Operates At Data Rates Up To 15 Mbit/s Using (2,7) Code . â , best suited for (1,7) RLL code . The VM5327 requires a 4T preamble field and is best suited for (2,7) RLL code . The VM5317/VM5327 uses the CBP high speed bipolar process. The circuit contains the , , divider, data standardizes and synchronization control block. Refer to the block diagram . CIRCUIT OPERATION SYNC CONTROL The data separator has three modes of operation: lock to reference oscillator, lock


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PDF VM5317/VM5327 VM5317 VM5327 44-Pin VM5317/VM5327 phase*detector VM5317PLK
2013 - Not Available

Abstract:
Text: Board Schematic 32 Block Diagram by Power Supply , output according to the internal logic. This is called digital lock detect. 4.1 Analog Lock Detect In , 2011/11 [AK1544] 4.2 Digital Lock Detect In the digital lock detect, the [LD] pin outputs is , ] : Counter value for lock detect The counter value for digital lock detect can be set. D18 0 0 1 1 D17 0 1 0 , digital for Lock Detect. D13 0 1 Function Digital lock detect mode Analog lock detect mode


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PDF AK1544] AK1544 1300MHz AK1544 MS1350-E-00
2014 - AK1541

Abstract:
Text: logic. This is called digital lock detect. 4.1 Analog Lock Detect In analog lock detect, the phase , [AK1541] 4.2 Digital Lock Detect The accuracy of the phase detect is set by {LDCKSEL[1:0]}. , (This cannot be used for the reference dividing ratio ≤ 6.) In the digital lock detect, the [LD] pin , satisfy either of the following formula, the digital lock detect cannot be used. In such case, the analog , digital lock detect cannot be used if the VCO frequency is equivalent to or smaller than 78.4MHz


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PDF AK1541] AK1541 600MHz AK1541 600MHz. 18-bit 24-VSOP AK2346A AK2347B
2013 - Not Available

Abstract:
Text: logic. This is called digital lock detect. 4.1 Analog Lock Detect In analog lock detect, the phase , [AK1541] 4.2 Digital Lock Detect The accuracy of the phase detect is set by {LDCKSEL[1:0]}. , (This cannot be used for the reference dividing ratio ≤ 6.) In the digital lock detect, the [LD] pin , satisfy either of the following formula, the digital lock detect cannot be used. In such case, the analog , digital lock detect cannot be used if the VCO frequency is equivalent to or smaller than 78.4MHz


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PDF AK1541] AK1541 600MHz AK1541 600MHz. 18-bit MS1043-E-05
Not Available

Abstract:
Text: logic. This is called digital lock detect. 4.1 Analog Lock Detect In analog lock detect, the phase , [AK1541] 4.2 Digital Lock Detect The accuracy of the phase detect is set by {LDCKSEL[1:0]}. , (This cannot be used for the reference dividing ratio ≤ 6.) In the digital lock detect, the [LD , satisfy either of the following formula, the digital lock detect cannot be used. In such case, the analog , digital lock detect cannot be used if the VCO frequency is equivalent to or smaller than 78.4MHz


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PDF AK1541] AK1541 600MHz AK1541 600MHz. 18-bit MS1043-E-05
CP/2014

Abstract:
Text: Operation MS1399-E-02 2014/4 - 14 - [AK1542A] 4.2 Digital Lock Detect In the digital lock , outputs “High” LD output Fig. 8 Digital Lock Detect Operations MS1399-E-02 2014/4 - 15 , FAST[12:0] 0100 LDCNTSEL[1:0] : Counter value for lock detect The counter value for digital lock , : Selects analog or digital for Lock Detect. D13 Function 0 Digital lock detect mode 1 , to 5.5V (CPVDD pin)  On-chip power-saving features  On-chip lock detection feature


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PDF AK1542A] AK1542A 600MHz AK1542A MS1399-E-02 CP/2014
2014 - AK1542A

Abstract:
Text: Operation MS1399-E-02 2014/4 - 14 - [AK1542A] 4.2 Digital Lock Detect In the digital lock , outputs “High” LD output Fig. 8 Digital Lock Detect Operations MS1399-E-02 2014/4 - 15 , FAST[12:0] 0100 LDCNTSEL[1:0] : Counter value for lock detect The counter value for digital lock , : Selects analog or digital for Lock Detect. D13 Function 0 Digital lock detect mode 1 , to 5.5V (CPVDD pin)  On-chip power-saving features  On-chip lock detection feature


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PDF AK1542A] AK1542A 600MHz AK1542A 24-VSOP AK2346A AK2347B AK2347A CP/2014
2013 - Not Available

Abstract:
Text: ] 5.2 Digital Lock Detect In digital lock detect, [LD] pin outputs ”Low” when the frequency is set , following formula, the digital lock detect is not available. In such case, the analog lock detect should be , , the digital lock detect is not available if the VCO frequency is equivalent to or smaller than , €œ01”; 33.6MHz / (1+1) × 4 = 67.2MHz As a result, the digital lock detect is not available if the VCO frequency , example {DITH} = D[14] in is set to “1” (DITH ON): Digital Lock Detect Available


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PDF AK1590] AK1590 AK1590 1000MHz. 18-bit 1000MHz MS1478-E-01
2013 - Not Available

Abstract:
Text: Operation MS1399-E-00 2012/3 - 14 - [AK1542A] 4.2 Digital Lock Detect In the digital lock , outputs “High” LD output Fig. 8 Digital Lock Detect Operations MS1399-E-00 2012/3 - 15 , FAST[12:0] 0100 LDCNTSEL[1:0] : Counter value for lock detect The counter value for digital lock , : Selects analog or digital for Lock Detect. D13 Function 0 Digital lock detect mode 1 , to 5.5V (CPVDD pin)  On-chip power-saving features  On-chip lock detection feature


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PDF AK1542A] AK1542A 600MHz AK1542A MS1399-E-00
2014 - AK1544

Abstract:
Text: is output according to the internal logic. This is called digital lock detect. 4.1 Analog Lock , MS1350-E-01 14 2013/03 [AK1544] 4.2 Digital Lock Detect In the digital lock detect, the [LD , value for digital lock detect can be set. D18 D17 Function 0 0 Counter value = 7 0 , Fig. 11 Charge Pump Output Polarity LD: Selects analog or digital for Lock Detect. D13 Function 0 Digital lock detect mode 1 Remarks Analog lock detect mode For detailed


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PDF AK1544] AK1544 1300MHz AK1544 24-VSOP AK2346A AK2347B AK2347A
2013 - Not Available

Abstract:
Text: is output according to the internal logic. This is called digital lock detect. 4.1 Analog Lock , MS1350-E-01 14 2013/03 [AK1544] 4.2 Digital Lock Detect In the digital lock detect, the [LD , value for digital lock detect can be set. D18 D17 Function 0 0 Counter value = 7 0 , Fig. 11 Charge Pump Output Polarity LD: Selects analog or digital for Lock Detect. D13 Function 0 Digital lock detect mode 1 Remarks Analog lock detect mode For detailed


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PDF AK1544] AK1544 1300MHz AK1544 MS1350-E-00
2014 - AK1543

Abstract:
Text: PLL lock detect feature: Direct output to the PFD (Phase Frequency Detector) or digital filtering , according to the on-chip logic. This is called digital lock detect. 4.1 Analog Lock Detect In analog , MS1206-E-02 14 2013/03 [AK1543] 4.2 Digital Lock Detect {LD} in is set to “0 {LDCKSEL[1:0]} in is set to “00” In the digital lock detect, the [LD] pin outputs is , Valid Valid Invalid Invalid Valid Fig. 8 Digital Lock Detect Operation MS1206-E


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PDF AK1543] AK1543 1300MHz AK1543 1300MHz. 18-bit 24-VSOP AK2346A AK2347B
Not Available

Abstract:
Text: . This is called digital lock detect. 4.1 Analog Lock Detect In analog lock detect, the phase , ] 4.2 Digital Lock Detect In the digital lock detect, the [LD] pin outputs is ”Low” every time when , ] : Counter value for lock detect The counter value for digital lock detect can be set. D18 D17 , Lock Detect. D13 Function 0 Digital lock detect mode 1 Remarks Analog lock detect , pin)  On-chip power-saving features  On-chip lock detection feature of PLL


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PDF AK1544] AK1544 1300MHz AK1544 MS1350-E-00
Not Available

Abstract:
Text: PLL lock detect feature: Direct output to the PFD (Phase Frequency Detector) or digital filtering , logic. This is called digital lock detect. 4.1 Analog Lock Detect In analog lock detect, the phase , [AK1543] 4.2 Digital Lock Detect {LD} in is set to “0 {LDCKSEL[1:0]} in is set to “00” In the digital lock detect, the [LD] pin outputs is ”Low” every time when the , Invalid Valid Fig. 8 Digital Lock Detect Operation MS1206-E-02 15 2013/03 [AK1543


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PDF AK1543] AK1543 1300MHz AK1543 1300MHz. 18-bit MS1206-E-02
2013 - Not Available

Abstract:
Text: PLL lock detect feature: Direct output to the PFD (Phase Frequency Detector) or digital filtering , according to the on-chip logic. This is called digital lock detect. 4.1 Analog Lock Detect In analog , MS1206-E-02 14 2013/03 [AK1543] 4.2 Digital Lock Detect {LD} in is set to “0 {LDCKSEL[1:0]} in is set to “00” In the digital lock detect, the [LD] pin outputs is , Valid Valid Invalid Invalid Valid Fig. 8 Digital Lock Detect Operation MS1206-E


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PDF AK1543] AK1543 1300MHz AK1543 1300MHz. 18-bit MS1206-E-02
2003 - 125M-1995

Abstract:
Text: ( lock ) time is less than 75 µs @ 270 Mbps. Device Operation The CLC020 SMPTE 259M Digital Video , . Values with 3 significant digits are 1%; with 2 digits 5%. FIGURE 8. SD020EVK Schematic Diagram , CLC020 SMPTE 259M Digital Video Serializer with Integrated Cable Driver General Description Features The CLC020 SMPTE 259M Digital Video Serializer with Integrated Cable Driver is a monolithic integrated circuit that encodes, serializes and transmits bit-parallel digital data conforming to SMPTE


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PDF CLC020 CLC020 10-bit 125M-1995 PAL PATTERN GENERATOR color pal transistor pattern generator schematic CLC018 CLC016 CLC014 CLC006 267M SMPTE 267M
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