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Part Manufacturer Description Datasheet Download Buy Part
LTC2450CDC-1#TRMPBF Linear Technology LTC2450-1 - Easy-to-Use, Ultra-Tiny 16-Bit Delta Sigma ADC; Package: DFN; Pins: 6; Temperature Range: 0°C to 70°C
LTC2450IDC#PBF Linear Technology LTC2450 - Easy-to-Use, Ultra-Tiny 16-Bit Delta Sigma ADC; Package: DFN; Pins: 6; Temperature Range: -40°C to 85°C
LTC2450CDC#TRPBF Linear Technology LTC2450 - Easy-to-Use, Ultra-Tiny 16-Bit Delta Sigma ADC; Package: DFN; Pins: 6; Temperature Range: 0°C to 70°C
LTC2450CDC-1#PBF Linear Technology LTC2450-1 - Easy-to-Use, Ultra-Tiny 16-Bit Delta Sigma ADC; Package: DFN; Pins: 6; Temperature Range: 0°C to 70°C
LTC2450IDC-1#TRMPBF Linear Technology LTC2450-1 - Easy-to-Use, Ultra-Tiny 16-Bit Delta Sigma ADC; Package: DFN; Pins: 6; Temperature Range: -40°C to 85°C
LTC2450CDC-1#TRPBF Linear Technology LTC2450-1 - Easy-to-Use, Ultra-Tiny 16-Bit Delta Sigma ADC; Package: DFN; Pins: 6; Temperature Range: 0°C to 70°C

digital clock using logic gates Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
2009 - full adder circuit using nor gates

Abstract: free transistor equivalent book Verilog code for 2s complement of a number verilog code for four bit binary divider 16 bit carry select adder verilog code hex to 7 segment decoder BASYS+3
Text: gates : AND, OR, and NOT. In fact, we will see that any digital logic circuit can be made using only , design involving the drawing of logic diagrams when the digital circuit may contain thousands of gates , gates ? As programmable logic devices replaced TTL chips in new designs a new approach to digital design , editor to draw logic circuits using basic gates . When you compile these block diagrams Active-HDL will , Introduction to Digital Design Using Digilent FPGA Boards ─ Block Diagram / Verilog Examples


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2001 - verilog code 8 bit LFSR in descrambler

Abstract: verilog code 8 bit LFSR in scrambler XAPP288 vhdl code for 4 bit barrel shifter SDI descrambler SDI scrambler vhdl code 4 bit LFSR verilog code of 4 bit comparator barrel shifter using verilog parallel scrambler 24 bit lfsr
Text: implementation also requires the availability of a bit-rate clock for the FPGA. By using Virtex-II devices, a , next clock cycle. Ten 3-input XOR gates form the SDI descrambler. These gates generate the ten , clock cycles. The offset logic block generates the trs, nsp, and out_rdy outputs. The out_rdy signal is , of the bits of the bit_cntr. If downstream logic requires more setup time, the clock cycle when , detection logic examines. A series of ten-bit wide AND and NOR gates examine the 39-bit input vector to


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PDF XAPP288 259M-1997 525-line, 625-line, XAPP298: XAPP299: verilog code 8 bit LFSR in descrambler verilog code 8 bit LFSR in scrambler XAPP288 vhdl code for 4 bit barrel shifter SDI descrambler SDI scrambler vhdl code 4 bit LFSR verilog code of 4 bit comparator barrel shifter using verilog parallel scrambler 24 bit lfsr
2008 - SDHC specification

Abstract: SD host controller vhdl tsmc 0.18um vhdl code for memory card GPS clock code using VHDL digital clock using logic gates GPS clock code using verilog MMC version 4 AMBA BUS vhdl code sdio memory
Text: Interface Unit Communicates with SD/SDIO/MMC cards using the SD bus interface. It contains card clock , ), and software reset for DAT (clears the datapath logic ). Configurability Area & Speed (clk clock , . The silicon area is below 16k gates for the simple single-slot version without DMA, or as little as 37k gates for the fully-featured 4slot version. Each slot can be individually controlled through the , . Applications Digital cameras and camcorders, storing images and video Digital audio players and cellular


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2009 - 32 bit carry select adder in vhdl

Abstract: No abstract text available
Text: gates : AND, OR, and NOT. In fact, we will see that any digital logic circuit can be made using only , design involving the drawing of logic diagrams when the digital circuit may contain thousands of gates , gates ? As programmable logic devices replaced TTL chips in new designs a new approach to digital design , block diagram editor to draw logic circuits using basic gates . When you compile these block diagrams , Introduction to Digital Design Using Digilent FPGA Boards ─ Block Diagram / VHDL Examples


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PDF mux21a 32 bit carry select adder in vhdl
2009 - SDXC

Abstract: digital clock using logic gates sd card soc
Text: less silicon area (working in single-buffer mode only). SYN ­ Synchronization Logic Cross clock , Dual-Port RAM. The core is competitive in its use of silicon space, requiring under 33K gates for a simple single-slot configuration without DMA, or 69K gates for a 4-slot version with Advanced DMA. The , devices such as digital cameras, camcorders, digital audio players, GPS receivers, cellular phones, and , wireless modems, digital TV tuners, and fingerprint recognition cards. Block Diagram compliant -


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PDF 8/16/32-bit 32-bit SDXC digital clock using logic gates sd card soc
2002 - Xilinx usb cable Schematic

Abstract: SPARTAN-II xc2s200 pq208 DS-KIT-95XL DS-KIT-95XL-XPLA3-PAK COOLRUNNER-II examples DS-KIT-95XL-PAK DS-KIT-2S300E DS-KIT-2C64 XC9572XL XCR3064XL
Text: 1.8V 128 Macrocells (3,200 Gates ), 9 I/O Standards, Slew Rate Control, Clock Doubler, Clcok Divider , , TQ144 1.8V 256 Macrocells (6,400 Gates ), 9 I/O Standards, Slew Rate Control, Clock Doubler, Clcok , TQ144, PQ208 1.8V 384 Macrocells (9,600 Gates ), 9 I/O Standards, Slew Rate Control, Clock Doubler , MHz PQ208 1.8V 512 Macrocells (12,800 Gates ), 9 I/O Standards, Slew Rate Control, Clock , designs at any time. With our unique Internet Reconfigurable Logic (IRLTM) capability, you can remotely


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PDF QS9000 Xilinx usb cable Schematic SPARTAN-II xc2s200 pq208 DS-KIT-95XL DS-KIT-95XL-XPLA3-PAK COOLRUNNER-II examples DS-KIT-95XL-PAK DS-KIT-2S300E DS-KIT-2C64 XC9572XL XCR3064XL
1998 - VHDL code for generate sound

Abstract: vhdl code for spartan 6 XAPP119 XCS30 XCS40 The ten commandments
Text: transferred to FPGAs. Using good digital design techniques can prevent such problems. Wherever logic lies , resources, resulting in efficient logic utilization and high performance. Using cores to replace HDL code , general idea which Spartan device has sufficient logic resources to hold the design, count "system gates , density of ASICs is commonly measured using a " logic gate count", which is the total number of two-input NAND gates (four transistors per gate) in the design. One logic gate is equivalent to two system


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PDF XAPP119 VHDL code for generate sound vhdl code for spartan 6 XCS30 XCS40 The ten commandments
1998 - vhdl code for spartan 6

Abstract: The ten commandments digital clock using logic gates XAPP119 XCS30 XCS40 hdl3
Text: transferred to FPGAs. Using good digital design techniques can prevent such problems. Wherever logic lies , resources, resulting in efficient logic utilization and high performance. Using cores to replace HDL code , general idea which Spartan device has sufficient logic resources to hold the design, count "system gates , density of ASICs is commonly measured using a " logic gate count", which is the total number of two-input NAND gates (four transistors per gate) in the design. One logic gate is equivalent to two system


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PDF XAPP119 vhdl code for spartan 6 The ten commandments digital clock using logic gates XCS30 XCS40 hdl3
1999 - digital clock using logic gates

Abstract: uart vhdl fpga virtex 6 design 12 Hour Digital Clock using multiplexer XCV600 XCV50 XCV400 XCV300 XCV200 XCV150 XCV100
Text: , digital designers for the first time can use an FPGA to perform not only familiar logic functions, but , transistors. The Virtex XCV1000 doubles the density of programmable logic previously available to digital , CLB implements logic using four independent four-input lookup tables, four independent set/reset , digital designers with continuously higher levels of logic density and performance while offering more , MHz, digital designers cannot tolerate long clock-tooutput times, input set-up times, or on-chip clock


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2001 - toshiba satellite laptop battery pinout

Abstract: samsung plasma tv schematic diagram toshiba laptop schematic diagram powerline ethernet adapter schematic diagram XILINX vhdl code download REED SOLOMON temperature controlled fan project using 8051 circuit diagram bluetooth based home automation TUTORIALS xilinx FFT samsung laptop battery pinout NEC plasma tv schematic diagram
Text: programmable logic devices (PLDs) much faster than they could by using traditional methods, such as , solutions, design tools, and IP cores · Internet Configurable Logic (IRL): Field upgradeability using , The third method connects the gates by using software-controlled switches within the PLD Once the , risks. IP cores implement predefined logic functions such as digital signal processing (DSP), bus , is based on a CMOS chain of gates as the base building block for CPLD logic . The primary benefit of


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PDF WP129 toshiba satellite laptop battery pinout samsung plasma tv schematic diagram toshiba laptop schematic diagram powerline ethernet adapter schematic diagram XILINX vhdl code download REED SOLOMON temperature controlled fan project using 8051 circuit diagram bluetooth based home automation TUTORIALS xilinx FFT samsung laptop battery pinout NEC plasma tv schematic diagram
2002 - Not Available

Abstract: No abstract text available
Text: the four PIOs per PIC is counted as 16 gates (three FFs, fast-capture latch, output logic , CLK, and I , cycle for input clock rates from 5 MHz to 120 MHz. The PCM may be combined with FPGA logic to create , supply voltage for speed and compatibility. Up to 340,000 usable gates in 0.25 µm. Up to 612 user I/Os , , selectable on a per-pin basis, when using 3.3 V I/O supply.) Twin-quad programmable function unit (PFU , byte-wide functions. Allows for mixed arithmetic and logic functions in a single PFU. Nine user registers


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PDF 16-bit 208-Pin 240-Pin 352-Pin 432-Pin 680-Pin OR3L165B OR3L225B PN00-012FPGA PN99-053FPGA)
verilog code for cdma transmitter

Abstract: verilog code for matrix inversion 15-bit* pn sequence digital mixer verilog code code for pn generator in digital PN generator circuit 4 bit pn sequence generator pn sequence generator verilog code verilog code cdma digital radio verilog code
Text: conditions are minimized. 2. The logic maps efficiently into the CPLD architecture. To perform digital , . Since most CPLDs have a regular structure consisting of LOGIC GATES -> REGISTER, it makes for efficient , levels of asynchronous logic continue to add in series and limit the maximum clock speed that can be , 4.8kHz. The modular PN generator uses more logic gates , as the EXOR operation is performed in parallel , combines a high-density programmable logic device, a crystal oscillator, and a pair of matched low-pass


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PDF 9152MHz CY37256 com/an918 MAX2361: AN918, APP918, Appnote918, verilog code for cdma transmitter verilog code for matrix inversion 15-bit* pn sequence digital mixer verilog code code for pn generator in digital PN generator circuit 4 bit pn sequence generator pn sequence generator verilog code verilog code cdma digital radio verilog code
2001 - 4-bit GTL to LVTTL transceiver

Abstract: digital clock using gates ORLI10G TRCV0110G TTRN0110G write operation using ram in fpga
Text: gates . The line interface includes logic to divide the data rate down to 167 MHz or less (1/4 line , -192/STM-48), 10 Gbits/s optical transport networks (OTN) using digital wrapper and strong FEC, or 10 , gates (three FFs, fast-capture latch, output logic , CLK, and I/O buffers). PFUs used as RAM are counted , gates are used for each PLL and 50k gates for the embedded system bus and microprocessor interface logic , -bit LVDS data interface for each) with a separate clock for each for transfer to the FPGA logic . s


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PDF ORLI10G ORLI10G 16-bit PB01-048NCIP PB01-021NCIP) 4-bit GTL to LVTTL transceiver digital clock using gates TRCV0110G TTRN0110G write operation using ram in fpga
2002 - OTN SWITCH

Abstract: ORLI10G STM-16 STM-64 STM 64 FRAMER WITH OTN
Text: FPGA gates . The line interface includes logic to divide the data rate down to 1/4 line rate or 1/8 , -192/STM-48), 10 Gbits/s optical transport networks (OTN) using digital wrapper and strong FEC, or 10 , System Chip (FPSC) which combines a high-speed line interface with a flexible FPGA logic core. Built on , line-side and system-side data rates, and a programmable logic interface at the system end for use with SONET/SDH, Ethernet, or OTN/ digital wrapper with strong Forward Error Correction (FEC) system device


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PDF ORLI10G 10Gbits/sec ORLI10G OIF-SFI401 16-bit 10GbE OC-192 1-800-LATTICE OTN SWITCH STM-16 STM-64 STM 64 FRAMER WITH OTN
2000 - design a 4-bit arithmetic logic unit using xilinx

Abstract: OC192 ORLI10G TRCV0110G TTRN0110G 4-bit GTL to LVTTL transceiver
Text: usable FPGA gates . The line interface includes logic to divide the data rate down to 167 MHz or less (1 , 10 Gbits/s SONET/SDH (OC-192/STM-48), 10 Gbits/s optical transport networks (OTN) using digital , groups are counted as 16 gates (three FFs, fast-capture latch, output logic , CLK, and I/O buffers). PFUs , each) with a separate clock for each for transfer to the FPGA logic . POS-PHY4 interface for 10 , Block Diagram EMBEDDED CORE FPGA LOGIC (400K GATES ) TRANSMIT PLLs 10 Gbit TXCLK 64:16


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PDF ORLI10G ORLI10G 16-bit PB01-021NCIP design a 4-bit arithmetic logic unit using xilinx OC192 TRCV0110G TTRN0110G 4-bit GTL to LVTTL transceiver
2009 - QN108

Abstract: CORE8051 ACTEL FUSION AFS1500
Text: . Actel Fusion devices are the most comprehensive single-chip analog and digital programmable logic , implemented in the FPGA logic using Designer and Libero IDE software tool support. Two channels of the 32 , distribute low-skew clock signals or for rapid distribution of high-fanout nets. Digital I/Os with , Programming (ISP) and Security High-Performance Reprogrammable Flash Technology Advanced Digital I/O , Logic ® Soft ARM CortexTM-M1 Fusion Devices (M1) · ARM Cortex-M1­Enabled (without debug) On-Chip


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PDF 128-Bit 130-nm, QN108 CORE8051 ACTEL FUSION AFS1500
ferranti ula

Abstract: ula ferranti ferranti ula flip flop Ferranti semiconductors ttl product guide ULA100DS ferranti array ferranti ECL 901 SERIES ula6ds
Text: Manufacturer DIGITAL AND LINEAR MACROS A wide range of fully characterised elements, from logic gates and , 100MHz and complexities from 500 to 10,000 gates . *DS' Series of ULAs for 100 MHz Digital ASIC Systems , Logic ' flip-flop: clock to output delay 1.5ns clock frequency 250MHz Gate delay: Ins virtually independent of fan-out, supply voltage and clock frequency LOW POWER PERFORMANCE 'Differential Logic , stacked across the supply rail (Fig. 1). Many complex and elegant logic functions can be implemented using


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PDF 100MHz 165//W ferranti ula ula ferranti ferranti ula flip flop Ferranti semiconductors ttl product guide ULA100DS ferranti array ferranti ECL 901 SERIES ula6ds
2000 - SANYO 35CV10gX

Abstract: PPG SENSOR PRICE TL082D anFT18 light sensor LM358 CCD output buffer ir sensor circuit diagram using LM358 brf92 TL082 PHILIPS EPF8282ALC84-4
Text: .21 Horizontal Clock Shaping Logic , delays. Operating the CCD at its limits, using a 40MHz pixel clock , makes it very difficult to generate , a digital CCD camera with true 12-bit performance. © Philips Electronics N.V. 2000 All rights , . Besides some CCD theory it provides very useful information on how to design a high performance digital , applications including digital photography, broadcast and medical imaging. Chapter 6 summarizes all critical


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PDF ANFT18 12-bit SANYO 35CV10gX PPG SENSOR PRICE TL082D anFT18 light sensor LM358 CCD output buffer ir sensor circuit diagram using LM358 brf92 TL082 PHILIPS EPF8282ALC84-4
Not Available

Abstract: No abstract text available
Text: can use multiple cells ■Digital features in s gate delays Differential logic giving , per column Columns Matrix cells Matrix gates 2 ( Logic ) Analog cells Bond pads 16 14 1 224 , logic gates and functions with d iffering complexities, functionality and speed/power attributes. The , transistors and 2 resistors. Gates with effective delays to below 1ns, and 1.5ns clock to output flip-flops , voltage and clock frequency. ^ T m 5 ^Tme ^ T m 7 Vs = internal logic supply rail Fig 4. DF


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PDF 37bfiS25 100MHz.
MLF24

Abstract: MLF-24 photodiode germanium M02063 TQFP32 M02069
Text: Note Using logic gates for shunting laser current 0206x-APP-002-A 0206x , digital pots by controlling the modulation current using a fixed resistor at RMODSET and adjustment of , if the clock inputs are not used. In this case the data inputs only need to be held in the logic 0 , the laser: either a inverting logic gate or a PMOS FET. It is not difficult to find logic gates with , gate is driven with a 50 source impedance. Using gates such as those specified above will result in a


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PDF 0206x-APP-002-A M02063/6/7/8/9 M02063, M02069, M02066, CX02067, CX02068) -26ns MLF24 MLF-24 photodiode germanium M02063 TQFP32 M02069
Not Available

Abstract: No abstract text available
Text: macros Complex macros can use multiple cells H Digital features 1ns gate delays Differential logic , column Columns Matrix cells Matrix gates 2 ( Logic ) Analog cells Bond pads 16 14 1 224 448 32 , configured into a range of logic gates and functions with differing complexities, functionality and speed , , comprising of 8 transistors and 2 resistors. Gates with effective delays to below 1ns, and 1 5ns clock to , fan-out, supply voltage and clock frequency. Tms ^ *|T m 6 * ^ ^ T m 7 Vs = Internal logic


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PDF 100MHz.
LU380A

Abstract: full subtractor circuit using nand gates LU380 full subtractor circuit using nor gates LU321A LU322B LU370A LU306 LU333A utilogic
Text: .7 Characteristic UTI LOGIC II NOR GATES AND EXPANDER , LOGIC II AND Gates The UTI LOGIC II AND gates 305 and 306 are fabricated from the same basic chip, and , Schematic diagrams of the UTI LOGIC II AND gates are shown in Figures 1 and 2. The multiple-emitter input , the supply voltage. The input impedance of UTI LOGIC II AND gates OUTÔ Ô0UT 14 13 12 11 10 ô GND 1 , collector logic configurations. However, outputs of AND gates may be connected to increase fan-out if the


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PDF 380ign LU380A full subtractor circuit using nand gates LU380 full subtractor circuit using nor gates LU321A LU322B LU370A LU306 LU333A utilogic
2008 - ACTEL FUSION AFS1500

Abstract: FlashPro3 AFS250 M-LVDS M1AFS1500 PQ208 QN108 QN180 rc oscillator
Text: logic designs. Two examples are using an on-chip soft processor to implement a fully functional Flash MCU and using high-speed FPGA logic to offer system and power supervisory capabilities. Live at , systems using existing ASIC or FPGA design flows and tools. The family has up to 1.5 M system gates , are programmable and implemented in the FPGA logic using Designer and Libero IDE software tool , ® to Secure FPGA Contents Advanced Digital I/O Embedded Flash Memory · 1.5 V, 1.8 V, 2.5 V


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PDF 130-nm, 128-Bit ACTEL FUSION AFS1500 FlashPro3 AFS250 M-LVDS M1AFS1500 PQ208 QN108 QN180 rc oscillator
1999 - tms320cxx architecture

Abstract: FPGA implementation of IIR Filter AT6002 AT6010 TMS320CXX 16 bit array multiplier VERILOG verilog code for iir filter digital IIR Filter verilog code
Text: DSP Acceleration Using a Reconfigurable Coprocessor FPGA Digital signal processors (DSPs), like , contains a D-type register and about 12 gates of logic . The specified data shift frequency for the , columns, for a total of 1,024 cells. This device can implement between 2,000 and 4,000 gates of logic , implement in excess of 20,000 gates of logic . The AT6000 family is completely symmetrical, enabling logic , Component Generators Figure 6. Cache Logic Summary By using cache logic FPGAs, specialized


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PDF 0724B 09/99/xM tms320cxx architecture FPGA implementation of IIR Filter AT6002 AT6010 TMS320CXX 16 bit array multiplier VERILOG verilog code for iir filter digital IIR Filter verilog code
1997 - tms320cxx architecture

Abstract: digital IIR Filter verilog code verilog code for iir filter verilog code for 16*16 multiplier FPGA implementation of IIR Filter 16*16 array multiplier VERILOG AT6002 image edge detection verilog code TMS320CXX AT6010
Text: Array By Joel Rosenberg Programmable Logic Marketing & Applications Manager Digital signal , datapath logic functions using similar pipelining and bit-serial processing techniques as those found in , exclusive-OR, is the basic logic element for building compare functions. The AT6010 has 6,400 XOR gates . The , cells as shown in figure 4. Each cell contains a D-type register and about 12 gates of logic . The , using pipelining. The single level logic delays of the AT6000 FPGA are 2ns, and the input buffer delay


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PDF AT6000 tms320cxx architecture digital IIR Filter verilog code verilog code for iir filter verilog code for 16*16 multiplier FPGA implementation of IIR Filter 16*16 array multiplier VERILOG AT6002 image edge detection verilog code TMS320CXX AT6010
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