The Datasheet Archive

Top Results (6)

Part Manufacturer Description Datasheet Download Buy Part
LTC4304IDD#TR Linear Technology LTC4304 - Hot Swappable 2-Wire Bus Buffer with Stuck Bus Recovery; Package: DFN; Pins: 10; Temperature Range: -40°C to 85°C
LTC4303CDD#TRPBF Linear Technology LTC4303 - Hot Swappable 2-Wire Bus Buffer with Stuck Bus Recovery; Package: DFN; Pins: 8; Temperature Range: 0°C to 70°C
LTC4304CMS#TRPBF Linear Technology LTC4304 - Hot Swappable 2-Wire Bus Buffer with Stuck Bus Recovery; Package: MSOP; Pins: 10; Temperature Range: 0°C to 70°C
LTC4307IDD#TRPBF Linear Technology LTC4307 - Low Offset Hot Swappable 2-Wire Bus Buffer with Stuck Bus Recovery; Package: DFN; Pins: 8; Temperature Range: -40°C to 85°C
LTC4308IDD#TRPBF Linear Technology LTC4308 - Low Voltage, Level Shifting Hot Swappable 2-Wire Bus Buffer with Stuck Bus Recovery; Package: DFN; Pins: 8; Temperature Range: -40°C to 85°C
LTC4303IMS8 Linear Technology LTC4303 - Hot Swappable 2-Wire Bus Buffer with Stuck Bus Recovery; Package: MSOP; Pins: 8; Temperature Range: -40°C to 85°C

digital clock and carrier recovery Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
2001 - digital clock and carrier recovery

Abstract:
Text: Q I/P Analog AGC control · · · · I2C bus microprocessor interface All digital clock and carrier recovery On-chip PLL clock generation using low cost 10 to 15 MHz crystal 3.3V , Fully digital timing and phase recovery loops High level software interface for minimum development , MBaud demodulator and channel decoder for digital satellite television transmissions to the European , Conforms to EBU specification for DVB-S and DirecTV specification for DSS On-chip digital filtering


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PDF VP310 VP310 digital clock and carrier recovery DS5155
2006 - digital clock and carrier recovery

Abstract:
Text: microprocessor interface All digital clock and carrier recovery On-chip PLL clock generation using low cost 10 , · · · Up to ± 15 MHz LNB frequency tracking Fully digital timing and phase recovery loops , Preliminary Information The VP310 is a QPSK/BPSK 1 to 45 MBaud demodulator and channel decoder for digital , Trace back depth 128 · Extensive SNR and BER monitors Timing recovery Matched filter Phase , convenience only. For more information on Zarlink's obsolete products and replacement product lists, please


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PDF VP310 VP310 digital clock and carrier recovery VP310/CG/GQ1N directv descrambler DS5155 philips master replacement guide zarlink VP310
2004 - digital clock and carrier recovery

Abstract:
Text: · Dual square-root Nyquist matched filters (a=0.2-0.35) · All digital clock and carrier recovery · , QPSK ® SUMMARY OF BENEFITS · A universal digital transmission solution for DVB, DSS, and DigiCipher , S_SYNC P_DATA[7:0] Deinterleaver RAM AGC_CTRL Acquisition/Tracking Loops and Clock Generation JTAG , converters, a phase/ frequency recovery block, variable rate digital filters, square-root Nyquist matched , digital transmission standard, and DigiCipher II ITU-R 217/11 digital transmission standard. Analog


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PDF BCM4201 80-pin 85-Mbps BCM4201 4201-PB04-R digital clock and carrier recovery Digicipher block diagram of integrated satellite system oqpsk receiver direcTV viterbi Viterbi Decoder Broadcom RECEIVER block diagram of receiver synchronization ITU-R bcm420
2001 - Not Available

Abstract:
Text: PC applications · · · · · · · I2C bus microprocessor interface All digital clock and carrier recovery , GQ1N · · · · Up to ± 15 MHz LNB frequency tracking Fully digital timing and phase recovery loops , MBaud demodulator and channel decoder for digital satellite television transmissions to the European , specification for DVB-S and DirecTV specification for DSS On-chip digital filtering supports 1 to 45 MBaud , recovery DVB DSS FEC MPEG/ DSS Packets Analog AGC control Clock Generation Acquisition


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PDF VP310 VP310
2003 - digital clock and carrier recovery

Abstract:
Text: Q I/P Analog AGC control · · · · I2C bus microprocessor interface All digital clock and carrier recovery On-chip PLL clock generation using low cost 10 to 15 MHz crystal 3.3V , Fully digital timing and phase recovery loops High level software interface for minimum development , MBaud demodulator and channel decoder for digital satellite television transmissions to the European , Conforms to EBU specification for DVB-S and DirecTV specification for DSS On-chip digital filtering


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PDF VP310 VP310 digital clock and carrier recovery directv descrambler DS5155 zarlink VP310
2002 - digital clock and carrier recovery

Abstract:
Text: Q I/P Analog AGC control · · · · I2C bus microprocessor interface All digital clock and carrier recovery On-chip PLL clock generation using low cost 10 to 15 MHz crystal 3.3V , Fully digital timing and phase recovery loops High level software interface for minimum development , MBaud demodulator and channel decoder for digital satellite television transmissions to the European , Conforms to EBU specification for DVB-S and DirecTV specification for DSS On-chip digital filtering


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PDF VP310 VP310 digital clock and carrier recovery BPSK demodulator DS5155 lnb analog tv
2003 - Not Available

Abstract:
Text: -bit A/D converters • Dual square-root Nyquist matched filters (a=0.2-0.35) • All digital clock and carrier recovery • Integrated PLLs DVB/DIRECTV/Digicipher II-compliant FEC decoder • 64 , , DSS and Digicipher II systems • An integrated solution enabling low complexity/low cost digital , Acquisition/Tracking Loops and Clock Generation AGC_CTRL JTAG Interface LNB_CTRL The BCM4201 , /OQPSK receiver, dual 8-bit A/D converters, a phase/frequency recovery block, variable rate digital


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PDF BCM4201 BCM4201 64-state PB03-R-06
2000 - Digicipher

Abstract:
Text: All digital clock and carrier recovery · Integrated PLLs cost digital satellite IRDs · Variable , A universal digital transmission solution for DVB, receiver for DIRECTV , DVB and DigicipherTM II digital satellite reception · RECEIVER DSS and Digicipher II systems · An integrated solution , Acquisition/Tracking Loops and Clock Generation JTAG Interface LNB_CTRL The BCM4201 Universal Satellite , , dual 8-bit A/D converters, a phase/frequency recovery block, variable rate digital filters


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PDF BCM4201 BCM4201 PB01-R-05 Digicipher jtag block diagram dvb direcTV viterbi oqpsk receiver block diagram satellite transponder satellite phone system digital clock and carrier recovery bcm4201dvb qpsk receiver
2002 - digital clock and carrier recovery

Abstract:
Text: /D converters · Dual square-root Nyquist matched filters (=0.2-0.35) · All digital clock and carrier recovery · Integrated PLLs · An integrated solution enabling low complexity/low DVB/DIRECTV , digital transmission solution for DVB, DSS and Digicipher II systems digital satellite reception , phase/frequency recovery block, variable rate digital filters, square-root Nyquist matched filters , , the DIRECTV digital transmission standard and Digicipher II ITU-R 217/11 digital transmission


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PDF BCM4201 BCM4201DVB PB02-R-4 digital clock and carrier recovery satellite phone system direcTV viterbi Digicipher integrated satellite receiver DVB BCM7020 BCM4201 BCM3440 Viterbi Decoder, QPSK
BCM4200

Abstract:
Text: square-root Nyquist matched filters (GC=0.2-0.35) · All digital clock and carrier recovery · Integrated PLLs , solution enabling low complexity/low cost digital satellite IRDs * Variable data rates support ail satellite systems worldwide * Integrated A/D converters reduce system manufacturing costs and complexities * A universal digital transmission solution for DVB and DSS systems * Demodulation up to 45 MBaud for , CTRL Acquisition/Tracking Loops and Clock (Generation JTAG Interface LNB Control Deinterleaver


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PDF BCM4200 BCM4200 1PB2/97 digital clock and carrier recovery
2003 - directv descrambler

Abstract:
Text: clock and carrier recovery On-chip PLL clock generation using low cost 10 to 16 MHz crystal Low power , phase recovery are all digital and the only feed-back to the analogue front-end is for automatic gain , compensation, frequency offset compensation, decimation filtering, carrier recovery , symbol recovery and , ZL10312 is a QPSK/BPSK 1 - 45 MSps demodulator and channel decoder for digital satellite television , channel decoder for digital satellite television transmissions compliant to both DVB-S and DSS standards


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PDF ZL10312 directv descrambler viterbi algorithm
2003 - PHILIPS television tuner schematic

Abstract:
Text: tuner · · All digital clock and carrier recovery Reed Solomon · On-chip PLL clock , 1 - 45 MSps. Frequency, timing and carrier phase recovery are all digital and the only feed-back to , compensation, decimation filtering, carrier recovery , symbol recovery and matched filtering. The decimation , specification for DVB-S and DirecTV specification for DSS · On-chip digital filtering supports 1 - 45 , recovery Matched filter Phase recovery Acquisition Control Clock Generation DVB DSS FEC 2


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PDF ZL10312 ZL10312QCG 64-pin ZL10312UBH PHILIPS television tuner schematic digital clock and carrier recovery schematic diagram receiver satellite service manual of philips PC satellite receiver ZL10312
2003 - ZL10312QCG

Abstract:
Text: digital clock and carrier recovery Reed Solomon · On-chip PLL clock generation using low cost 10 , . Frequency, timing and carrier phase recovery are all digital and the only feed-back to the analogue , filtering, carrier recovery , symbol recovery and matched filtering. The decimation filters give continuous , specification for DVB-S and DirecTV specification for DSS · On-chip digital filtering supports 1 - 45 , 45 MSps demodulator and channel decoder for digital satellite television transmissions to the


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PDF ZL10312 ZL10312QCG ZL10312QCF ZL10312QCG1 ZL10312UBH ZL10312QCG digital clock and carrier recovery ZL10312QCF ZL10312 schematic diagram receiver satellite lnb schematic DVB-S Demodulator digital tv schematic diagram DiSEqC 1.3 diseqc 1.0 ZL10312UBH
2003 - digital clock and carrier recovery

Abstract:
Text: tuner · · All digital clock and carrier recovery Reed Solomon · On-chip PLL clock , 1 - 45 MSps. Frequency, timing and carrier phase recovery are all digital and the only feed-back to , compensation, decimation filtering, carrier recovery , symbol recovery and matched filtering. The decimation , specification for DVB-S and DirecTV specification for DSS · On-chip digital filtering supports 1 - 45 , Description The ZL10312 is a QPSK/BPSK 1 - 45 MSps demodulator and channel decoder for digital satellite


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PDF ZL10312 digital clock and carrier recovery direcTV viterbi diseqc viterbi algorithm ZL10312
qam circuit

Abstract:
Text: The fully digital clock and carrier recovery elim inates the need to im plem ent external VCOs and , Root Raised Cosine Receive Filtering, Carrier Recovery and Digital Gain Control, Equalization (Linear , . Carrier Recovery - Fine Tuning The carrier recovery block allows the acquisition and track ing of a , Recovery Variable Symbol Rate Recovery Anti-aliasing Continuously Variable Digital Filtering with Symbol Rate Adaptive Bandwidth (1 to 18.75 Mbaud at the Same Sampling Frequency) Fully Digital Carrier


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PDF /ETS300 100-pin AT76C651 qam circuit QAM-256 QAM16
receiver qpsk schematic diagram

Abstract:
Text: interface. • All digital clock and carrier recovery . • On-chip PLL clock generation using low cost 10 , . Frequency, timing and carrier phase recovery are all digital and the only feed-back to the analog front-end , €¢ Fully digital timing and phase recovery loops. • High level software interface for minimum , filtering, carrier recovery , symbol recovery and matched filtering. The decimation filters give continuous , €¢ Conforms to EBU specification for DVB-S and DirecTV specification for DSS. • On-chip digital filtering


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PDF VP310 DS5155 VP310 45MBaud 90MHz 15MHz MS-022 418/ED/51210/016 receiver qpsk schematic diagram transmitter qpsk schematic diagram Single Chip zero IF L-band Tuner DVB Satellite qpsk schematic diagram Viterbi Decoder schematic diagram receiver satellite diseqc DVB-S receiver single chip qpsk transmitter FR 310
2003 - digital clock and carrier recovery

Abstract:
Text: microprocessor interface with separate interface to tuner. All digital clock and carrier recovery . On-chip PLL , . Frequency, timing and carrier phase recovery are all digital and the only feed-back to the analogue , filtering, carrier recovery , symbol recovery and matched filtering. The decimation filters give continuous , 2003 Conforms to EBU specification for DVB-S and DirecTV specification for DSS. On-chip digital , demodulator and channel decoder for digital satellite television transmissions to the European Broadcast


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PDF ZL10312 90MHz 22MHz ZL10312QCclude digital clock and carrier recovery receiver qpsk schematic diagram diseqc* LNB POWER DVB-S Demodulator digital tv schematic diagram ZL10312 ZL10312QCG
2003 - ZL10312

Abstract:
Text: microprocessor interface with separate interface to tuner. All digital clock and carrier recovery . On-chip PLL , anti-alias filtering for all symbol rates from 1 - 45 MS/s. Frequency, timing and carrier phase recovery are , , frequency offset compensation, decimation filtering, carrier recovery , symbol recovery and matched filtering , specification for DVB-S and DirecTV specification for DSS. On-chip digital filtering supports 1 - 45 MS/s symbol , filter Phase recovery DVB DSS FEC MPEG/ DSS Packets Analog AGC Control Clock Generation


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PDF ZL10312 90MHz 22MHz ZL10312QCG 64-pin DVB-S Demodulator digital tv schematic diagram viterbi algorithm
1999 - reed 108 R12

Abstract:
Text: Features · I²C bus microprocessor interface. · All digital clock and carrier recovery . · On-chip PLL , 45Mbaud. Frequency, timing and carrier phase recovery are all digital and the only feed-back to the , compensation, decimation filtering, carrier recovery , symbol recovery and matched filtering. The decimation , specification for DVB-S and DirecTV specification for DSS. · On-chip digital filtering supports 1 to 45MBaud , and code rate acquisition. · Up to ± 15MHz LNB frequency tracking. · Fully digital timing and phase


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PDF VP310 DS5155 VP310 45MBaud 90MHz 15MHz 20MBaud reed 108 R12 diseqc 1N4445 Reed Solomon encoder IC receiver qpsk schematic diagram lnb schematic lnb analog tv FR310 DVB-S front end receiver
2000 - QAM-512

Abstract:
Text: digital clock and carrier recovery eliminates the need to implement external VCOs and VCXOs and thus , receive filtering, carrier recovery and digital gain control and equalization (linear and decision , the lock signals of the carrier recovery , the equalizer and the timing recovery , which is the full , Timing Recovery Variable Symbol Rate Recovery Anti-aliasing Continuously Variable Digital Filtering with Symbol Rate Adaptive Bandwidth (1 to 18.75M Baud at the Same Sampling Frequency) Fully Digital Carrier


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PDF /ETS300 429/ITU-T 10-bit 07/00/0M QAM-512 QAM-1024 QAM-128 dvb-c demultiplexer pin diagram jtag dvb QAM-256 schematic DVB-C modulator
2000 - 32 QAM

Abstract:
Text: anti-aliasing filtering, square root raised-cosine receive filtering, carrier recovery and digital gain control , "Timing Waveforms" on page 35). Oscillator and Phase Locked Loop The fully digital clock and carrier , Digital Carrier Recovery (Coherent or Differential for QPSK) Robust Equalizer Acquisition Selectable , . The carrier recovery block allows the acquisition and tracking of a frequency offset as high as 12% of , device without modifying the content of I2C registers. All recovery loops (AGC, timing, carrier ) and the


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PDF /ETS300 429/ITU-T 1293D 10/00/0M 32 QAM carrier recovery 1024 QAM modulator demodulator QAM-32 1293D-10 QAM16 i2c tuner MPEG-TS stream digital clock and carrier recovery Tuner ts pinout
2000 - Car Central lock system

Abstract:
Text: , carrier recovery and digital gain control and equalization (linear and decision feedback dual structure). , "Timing Waveforms" on page 35). Oscillator and Phase Locked Loop The fully digital clock and carrier , 18.75M baud at the Same Sampling Frequency) Fully Digital Carrier Recovery (Coherent or Differential for , Integrated Clock Reference for Tuner, Especially Designed for NIU in CAN Two AGCs: Analog and Digital Gains , of I2C registers. All recovery loops (AGC, timing, carrier ) and the equalizer restart from their


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PDF /ETS300 429/ITU-T 1293C 06/00/0M Car Central lock system dvb-c demodulator dvb-c demultiplexer dvb-c top set box pin diagram jtag dvb strong QAM-256
1999 - DVB-C receiver schematic diagram

Abstract:
Text: anti-aliasing filtering, square root raised cosine receive filtering, carrier recovery and digital gain control , clock and carrier recovery eliminates the need to implement external VCOs and VCXOs and thus reduces , Digital Carrier Recovery (Coherent or Differential for QPSK) Robust Equalizer Acquisition Selectable , Recovery ­ Fine Tuning The carrier recovery block allows the acquisition and tracking of a frequency , registers. All recovery loops (AGC, timing, carrier ) and the equalizer restart from their initial value


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PDF /ETS300 1293B 11/99/0M DVB-C receiver schematic diagram circuit diagram of car central lock system Tuner I2C program sat Car Central lock system tv schematic diagram PHILIPS receiver QAM schematic diagram pin diagram jtag dvb strong tms 980 qpsk demod dvb t receiver
directv descrambler

Abstract:
Text: digital clock and carrier recovery . · On-chip PLL clock generation using low cost 10 to 15MHz crystal. · , ing and carrier phase recovery are all digital and the only feed-back to the analog front-end is for , 15MHz LNB frequency tracking. · Fully digital timing and phase recovery loops. · High level software , , decim ation filtering, carrier recovery , symbol recovery and matched filtering. The decim ation filters , to 45MBaud demodulator and channel decoder for digital satellite television transmissions to the


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PDF VP310 VP310 45MBaud 90MHz 15MHz 45MBaudon directv descrambler QPSK application receiver philips fr 310
2000 - 1293D

Abstract:
Text: anti-aliasing filtering, square root raised-cosine receive filtering, carrier recovery and digital gain control , "Timing Waveforms" on page 35). Oscillator and Phase Locked Loop The fully digital clock and carrier , Digital Carrier Recovery (Coherent or Differential for QPSK) Robust Equalizer Acquisition Selectable , modifying the content of I2C registers. All recovery loops (AGC, timing, carrier ) and the equalizer , carrier recovery , the equalizer and the timing recovery , which is the full demodulator. IRQMASK: 0x0B


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PDF /ETS300 429/ITU-T 1293D 10/00/0M 1293D-10 1024 QAM modulator demodulator QAM-128 offset QAM DVB-C receiver schematic diagram dvb-c demultiplexer dvb-c demodulator AT76C651 32QAM
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