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LTC3880EUJ#TRMPBF Linear Technology LTC3880 - Dual Output PolyPhase Step-Down DC/DC Controller with Digital Power System Management; Package: QFN; Pins: 40; Temperature: E
LTC3880EUJ-1#TRPBF Linear Technology LTC3880 - Dual Output PolyPhase Step-Down DC/DC Controller with Digital Power System Management; Package: QFN; Pins: 40; Temperature Range: -40°C to 85°C
LTC3880IUJ-1#PBF Linear Technology LTC3880 - Dual Output PolyPhase Step-Down DC/DC Controller with Digital Power System Management; Package: QFN; Pins: 40; Temperature Range: -40°C to 85°C
LTC3880EUJ#PBF Linear Technology LTC3880 - Dual Output PolyPhase Step-Down DC/DC Controller with Digital Power System Management; Package: QFN; Pins: 40; Temperature Range: -40°C to 85°C
LTC3880IUJ-1#TRPBF Linear Technology LTC3880 - Dual Output PolyPhase Step-Down DC/DC Controller with Digital Power System Management; Package: QFN; Pins: 40; Temperature Range: -40°C to 85°C
LTC3880EUJ-1#PBF Linear Technology LTC3880 - Dual Output PolyPhase Step-Down DC/DC Controller with Digital Power System Management; Package: QFN; Pins: 40; Temperature Range: -40°C to 85°C

digital FIR Filter verilog code polyphase Datasheets Context Search

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1999 - digital FIR Filter verilog code

Abstract:
Text: filter , you can use the output files with MATLAB, VHDL, or Verilog HDL simulation tools. The FIR , . Download the FIR compiler function from the Internet. Generate a custom filter using the FIR compiler , coefficient quantization in the frequency domain, generates FIR filter hardware structures and performs , integrated finite impulse response ( FIR ) filter development environment Highly optimized for Altera® device , FIR filter is a weighted, tapped delay line (see Figure 1). The filter design process involves


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PDF -UG-FIRCOMPILER-01 digital FIR Filter verilog code verilog code for interpolation filter FIR FILTER implementation in c language FIR Filter matlab verilog code for fir filter FIR filter matlaB design digital FIR Filter VHDL code verilog code for fixed point adder 16 QAM modulation verilog code verilog code for linear interpolation filter
2011 - verilog code for interpolation filter

Abstract:
Text: filter 8. Multi-channel decimation direct-form FIR filter The design files include Verilog HDL code to , interpolation FIR filter structure that the Quartus II software infers from the Verilog HDL example code , code to ensure the Quartus II Fitter utilizes the appropriate DSP block features for your FIR filter , application note contain HDL code for examples of the following different FIR filter variations: 1 , Table 3. Table 2. FIR Filter Top Level Signals Verilog Signal VHDL Direction Name Width


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PDF AN639: AN-639-1 27-bit verilog code for interpolation filter VHDL code for polyphase decimation filter using D 16 bit Array multiplier code in VERILOG 32 bit adder vhdl code 8 tap fir filter verilog systolic multiplier and adder vhdl code verilog code for decimation filter verilog code for parallel fir filter vhdl code for 8-bit signed adder
2001 - digital FIR Filter verilog code

Abstract:
Text: Data Width 1 Specifications The FIR compiler generates four polyphase filters. Each filter , . After you have created a custom FIR filter , you can use the output files with MATLAB, VHDL, or Verilog , .39 Generate a FIR Filter .39 Variable-Coefficient FIR Filter .42 Fixed-Coefficient FIR Filter


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2003 - verilog code for fir filter using DA

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Text: .0) March 28, 2003 Product Specification Distributed Arithmetic FIR Filter v8.0 The polyphase segments , 0 Distributed Arithmetic FIR Filter v8.0 DS240 (v1.0) March 28, 2003 0 0 Features , response ( FIR ), half-band, Hilbert transform, interpolated filters, polyphase decimator, polyphase , · The Xilinx filter Core is a highly parameterizable, area-efficient high-performance FIR filter , ) a(N-1) y(n) Figure 1: Conventional Tapped-Delay Line FIR Filter Mechanization © 2003 Xilinx


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PDF DS240 32-bit verilog code for fir filter using DA 4 tap fir filter based on mac vhdl code polyphase interpolator design in verilog verilog code for interpolation filter verilog code for decimation filter image video procesing code VHDL code for polyphase decimation filter using D VHDL code for polyphase decimation filter verilog code for decimator fir vhdl code
2000 - xilinx logicore core dds

Abstract:
Text: ARITHMETIC FIR FILTER 5.5 Polyphase Decimator The polyphase decimation filter option implements the , Distributed Arithmetic FIR Filter V4.0.0 November 3 2000 Product Specification Xilinx, Inc , impulse response ( FIR ), half-band, Hilbert transform, interpolated filters, polyphase decimator , FIR filter . Several highly optimized filters can be realized with the filter Core Generator , FIR FILTER The conventional single-rate FIR version of the core computes the convolution sum


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PDF 2-to-1024 1-to-32 1-to-32 xilinx logicore core dds matched filter in vhdl polyphase interpolator design in verilog 8 tap fir filter vhdl fir compiler v4 fir compiler xilinx fir compiler FIR FILTER implementation xilinx hilbert OPTIMIZED FPGA IMPLEMENTATION OF MULTI-RATE FIR F
ipad

Abstract:
Text: polyphase FIR filters, one for I and one for Q. Each filter takes a 1-bit input stream and generates four , 0-3. These are the outputs of an M=4 polyphase FIR filter . IY2[9:0], IY3[9:0] QY0[9:0], QY1[9:0 , o Verilog Source Code · All o o User Guide Test Bench Synthesis and Simulation , MC-ACT-DVBMOD Digital Video Broadcast Modulator April 23, 2004 Datasheet v1.2 3721 , Baseband Shaping block · 204/188 Reed-Solomon Outer Coder · Selectable convolutional code rates


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2014 - verilog code for interpolation filter

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Text: . The core is available as a register transfer level (RTL) code of the filter , both in Verilog and VHDL , an example of using a FIR filter . Digital samples to be filtered enter the filter input and filtered , . 30 Polyphase Interpolation Filter , . 42 Polyphase Decimation Filter , ) filter is one of the most essential building blocks in digital signal processing (DSP) systems. Digital


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2006 - VHDL code for polyphase decimation filter using D

Abstract:
Text: this application note reviews polyphase decimating filter architectures and discusses the fractional , .1) March 5, 2007 www.xilinx.com 2 R Polyphase Decimating Filter Architectures Polyphase , ) operation can be implemented in a polyphase architecture by breaking the N-tap low pass filter in Figure 3 , subfilters only operates at 1/Dth the input sample rate, a single FIR filter structure (that is N/D taps , inefficient decimating filter of Figure 3, the polyphase implementation cuts the computational workload (or


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PDF XAPP936 xapp936 VHDL code for polyphase decimation filter using D verilog code for decimation filter VHDL code for polyphase decimation filter 16 QAM modulation verilog code 16 QAM modulation matlab vhdl code for qam qpsk modulation VHDL CODE verilog code for decimator SDR baseband modulation demodulation DSP48
2011 - digital FIR Filter verilog HDL code

Abstract:
Text: clock-cycle-accurate FIR filter models (also known as bit-true models) in the Verilog HDL and VHDL languages and in the , provides a fully integrated finite impulse response ( FIR ) filter development environment optimized for use , FIR Compiler The structure of a FIR filter is a weighted, tapped delay line as shown in Figure 1­2. Figure 1­2. Basic FIR Filter xin Z -1 Z -1 Z -1 Z -1 Tapped Delay Line C0 C1 C2 C3 , . A fully parallel, pipelined FIR filter implemented in an FPGA can operate at very high data rates


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2010 - digital FIR Filter verilog code

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Text: clock-cycle-accurate FIR filter models (also known as bit-true models) in the Verilog HDL and VHDL languages and in , support Features The Altera® FIR Compiler implements a finite impulse response ( FIR ) filter MegaCore , impulse response ( FIR ) filter development environment optimized for use with Altera FPGA devices. You , FIR Compiler includes a coefficient generator. Many digital systems use signal filtering to remove , filters more computationally expensive. The structure of a FIR filter is a weighted, tapped delay line as


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2000 - vhdl code for 16 prbs generator

Abstract:
Text: identical 4x interpolating polyphase FIR filters, one for I and one for Q. Each filter takes a 1-bit input , Filter Out, phases 0-3: These are the outputs of an M=4 polyphase FIR filter . All four buses are updated , Filter test input: Similar to IBIT_IN but drives Q-Channel input to Nyquist filter . Code Rate Select , Experience For the source code version, users should be familiar with Verilog HDL entry, synthesis , convolutional code rates of: 1/2, 2/3, 3/4, 5/6, and 7/8 · Supports uncoded (1/1) operation · DC to 45+ MHz


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2009 - 3 tap fir filter based on mac vhdl code

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Text: The Altera® FIR Compiler implements a finite impulse response ( FIR ) filter MegaCore function and , Description The Altera FIR Compiler provides a fully integrated finite impulse response ( FIR ) filter , finite impulse response ( FIR ) filters and infinite impulse response (IIR) filters. Typical filter , . The structure of a FIR filter is a weighted, tapped delay line as shown in Figure 1­1. Figure 1­1. Basic FIR Filter xin Z -1 C0 Z C1 -1 Z -1 C2 Z C3 -1 Tapped Delay


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1999 - verilog hdl code for encoder

Abstract:
Text: It is basically two identical 4x interpolating polyphase FIR filters, one for I and one for Q. Each , Filter test input: Similar to IBIT_IN but drives Q-Channel input to Nyquist filter . Code Rate Select , register in the core. I-Channel Nyquist Filter Out, phases 0-3: These are the outputs of an M=4 polyphase FIR filter . All four buses are updated once per symbol clock, CLK. External logic commutates values on , Selectable convolutional code rates of: 1/2, 2/3, 3/4, 5/6, and 7/8 Supports uncoded (1/1) operation DC to 45


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2003 - pulse shaping FILTER implementation xilinx

Abstract:
Text: area efficient FIR filter . Single-rate polyphase decimators and interpolators are supported. Multiple , MAC FIR filter would be in a Digital Down Converter (DDC). Figure 14 illustrates a simple block , -3 FPGAs High-performance single-rate finite impulse response ( FIR ), polyphase decimator and interpolator , representation of a FIR filter is shown in Figure 1. x(n) z-1 z-1 a(0) a(1) z-1 a(2) z , ., edge detection and general 2-D convolution · Matched filter (with sample rate change) in a digital


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PDF DS245 32-bit 74-bit pulse shaping FILTER implementation xilinx xilinx logicore core dds FIR FILTER implementation xilinx CIC interpolation Filter structure interpolation CIC Filter XIP162 DS245 fir filter spartan 3 implementation of 16-tap fir filter using fpga polyphase decimation filter
2006 - Polyphase Filter Banks

Abstract:
Text: , Hilbert transform, polyphase filter bank, and interpolated filter implementations · , channels generally and up to 1024 for polyphase filter bank implementations · Product Specification , IP LogiCORE FIR Compiler v5.0 Overview A wide range of filter types can be implemented in the , Delay Line FIR Filter Representation Feature Support Matrix The FIR Compiler implements three , shows the classes of filters that are supported for the FIR Compiler core. Table 2: Filter


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PDF DS534 Polyphase Filter Banks non integer rate sampling rate converter verilog XC6SLX150-2FGG484 fir compiler v4 direct-form FIR Filter verilog polyphase how example make fir filter in spartan 3 vhdl system generator matlab ise Harris Microwave Semiconductor Division fir compiler xilinx DSP48
2008 - Altera CIC interpolation Filter

Abstract:
Text: note discusses the polyphase filter design. Polyphase Modulation In modern digital communication , finite impulse response ( FIR ) filter . The interpolated digital signal is then modulated by IF sinusoidal , rate CIC filter . Note that the polyphase FIR filters are single rate; therefore, the upsampling , I FIR 2 FIR /CIC X I Polyphase FIR0 Sub-DUC0 X cos NCO Phase0 + sin Q FIR 2 FIR /CIC X Q Polyphase FIR0 Sub-DUC1 X LVDS Serializer DAC Sub-DUC2


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matlab code for half subtractor

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Text: , and interpolation and decimation polyphase FIR filters. An introduction to the complex FIR filter is , , Volume 2 Finite Impulse Response ( FIR ) Filters FIR Filter Background Digital communications , four-multiplier adder mode can be used for FIR filter and complex FIR filter applications. The DSP block combines , implement an entire 18-bit FIR filter with up to four taps. For FIR filters larger than four taps, you can , Figure 6­15. Input Shift Registers Configured for a FIR Filter Data A D Q ENA A[n] × B[n] (to


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FIR Filter matlab

Abstract:
Text: decimation polyphase FIR filters. An introduction to the complex FIR filter is also presented in this , Impulse Response ( FIR ) Filters FIR Filter Background Digital communications systems use FIR filters , interpolation filter is efficiently implemented with a polyphase FIR filter . DSP systems frequently use , Handbook, Volume 2 Finite Impulse Response ( FIR ) Filters Polyphase Interpolation Filter , 60MHz. Polyphase Interpolation Filter Design Example Download the Interpolation FIR Filter


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PDF S52007-1 FIR Filter matlab fft matlab code using 16 point DFT butterfly matlab code using 8 point DFT butterfly matlab programs for impulse noise removal circuit diagram for iir and fir filters Recursive Filter Basic z transform DECIMATION IN FREQUENCY DSP decimation filters binary 4 bit serial subtractor
2005 - baseband processor simulink

Abstract:
Text: the polyphase modem design: · 4x Interpolation FIR Filter · 8x Interpolation FIR Filter · Polyphase FIR Filter · Polyphase NCO · NIOS Interface nc o0_ph[23:0] nco1_cos[ 17: 0] G oto6 wri , polyphase modem, the high clock speed is exploited to reduce the resource constraints of a FIR filter , q_rdy Q_rdy fi r_8x dem ux Polyphase FIR Filter I0[ 17: 0] 1 [fi r_8x_d one] st , Polyphase FIR Filter I 0[17:0] 1 [ fir _8x_done] start Q0[17:0] z From 24 I 1[17:0


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types of binary multipliers

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Text: decimation polyphase FIR filters. An introduction to the complex FIR filter is also presented in this , Impulse Response ( FIR ) Filters FIR Filter Background Digital communications systems use FIR filters , www.altera.com. Polyphase FIR Interpolation Filters An interpolation filter can be used to increase sample rate. An interpolation filter is efficiently implemented with a polyphase FIR filter . DSP systems , web site at www.altera.com. Polyphase FIR Decimation Filters A decimation filter can be used to


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PDF S52007-1 types of binary multipliers FIR Filter matlab FIR filter design using cordic algorithm fir filter coding for gui in matlab fft matlab code using 16 point DFT butterfly EP1S60 DECIMATION IN FREQUENCY DSP c code for interpolation and decimation filter binary 4 bit serial subtractor APPLICATION circuit diagram fir filters
matlab code for half subtractor

Abstract:
Text: , and interpolation and decimation polyphase FIR filters. An introduction to the complex FIR filter is , Handbook, Volume 2 Finite Impulse Response ( FIR ) Filters FIR Filter Background Digital , four-multiplier adder mode can be used for FIR filter and complex FIR filter applications. The DSP block combines , implement an entire 18-bit FIR filter with up to four taps. For FIR filters larger than four taps, you can , Figure 18­15. Input Shift Registers Configured for a FIR Filter Data A D Q ENA A[n] × B[n] (to


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2010 - vhdl code for FFT 4096 point

Abstract:
Text: impulse response ( FIR ), polyphase decimator, polyphase interpolator, half-band, half-band decimator and , -1 a(N-1) y(n) Figure 1: Conventional Tapped Delay Line FIR Filter Representation DS795 October , . Table 2: Filter Configuration Support Matrix Filter Configuration Conventional Single-rate FIR Half-band FIR Hilbert Transform [Ref 3] Interpolated FIR [Ref 4] [Ref 5] Polyphase Decimator Polyphase , also optional is available. Table 3 defines the FIR filter port names and port functional descriptions


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PDF DS795 ZynqTM-7000, vhdl code for FFT 4096 point verilog code for fir filter using DA AMBA AXI4 verilog code VHDL code for polyphase decimation filter using D VHDL code for polyphase decimation filter P6421 p4826 FIR FILTER implementation on fpga FDATOOL DSP48 spartan 6
2002 - fir filter coding for gui in matlab

Abstract:
Text: polyphase FIR filters. An introduction to the complex FIR filter is also presented in this section. FIR Filter Background Digital communications systems use FIR filters for a variety of functions, including , efficiently implemented with a polyphase FIR filter . DSP systems frequently use polyphase filters because , filter is efficiently implemented with a polyphase FIR filter . DSP systems frequently use polyphase , finite impulse response ( FIR ) filter , infinite impulse response (IIR) filter , fast fourier transform


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1997 - cic filter

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Text: Costas Loop (DCL) chips support NCO driven polyphase resampling filtering when the HSP43168 Dual FIR , to use. © Harris Corporation 1997 7-127 Application Note 9661 PolyPhase Filter Design The , the data into the external FIR filter . This selection of the Programmable Divider determines the , . Note that the input sample clock (CLK) is the clock that should be used to clock the FIR filter input. The DATARDY signal will be used to enable the FIR filter input data sampling at the decimated rate


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PDF AN9661 HSP50110 HSP50210 HSP43168 HSP50110 HSP50210 HSP43168 cic filter C224 C193 C192 C160 C159 C128 C127 8 bit dff with output enable X band 5-bit phase shifter
1996 - Not Available

Abstract:
Text: polyphase filter bank model, the stored FIR filter coefficients are thought of as the impulse response of a , the FIR polyphase filter can be greater than 20 kHz. The cutoff frequency of the FIR filter during , source is narrowband because the digital servo control loop averages the polyphase filter selection , Million 22-Bit FIR Filter Coefficients Stored On-Chip Automatic Output Mute Flexible Four Wire Serial , rating conditions for extended periods may affect device reliability. DIGITAL FILTER CHARACTERISTICS


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PDF AD1890) 22-Bit P-28A 28-Lead C1820
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