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LT1126CJ8 Linear Technology IC DUAL OP-AMP, 200 uV OFFSET-MAX, 65 MHz BAND WIDTH, CDIP8, 0.300 INCH, HERMETIC, CERAMIC, DIP-8, Operational Amplifier
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LTC2301CDE#TRPBF Linear Technology LTC2301 - 1-Channel, 12-Bit ADCs with I2C Compatible Interface; Package: DFN; Pins: 12; Temperature Range: 0°C to 70°C

diagram of IC 74161 Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
IC 74161

Abstract:
Text: (see Figure B). For conventional operation of 74160, 74161 and 74163, the following transitions should , Count (HHHH for '161 and HLLH for ' 160). (b) The HIGH-to-LOW transition of CEP or CET on the 74161 and , e tta b le d e ca de (74160, 74LS160A, 74LS162A) and 4-bit ( 74161 , 74LS161A, 74163, 74LS163A , operation is pro vided by having all flip-flops clocked simultaneously on the positive-going edge of the clock. The Clock input is buffered. The outputs of the counters may be preset to HIGH or LOW level. A


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PDF 74LS160A, 74LS162A) 74LS161A, 74LS163A) 54LS/74LS IC 74161 lm 74161 IC 74160 IC 74160 decade counter diagram ic 74163 74163 74161/74160 function table IC 74160 for decade counter 74160 pin LM 74160
ic 74160

Abstract:
Text: enable the next cascaded stage (see Figure B). For conventional operation of 74160, 74161 and 74163, the , Terminal Count (HHHH for '161 and HLLH for '160). (b) The HIGH-to-LOW transition of CEP or CET on the 74161 , transition of PE on the 74161 and 74160 should only occur while CP is HIGH for conventional operation. (d , Signetics 74160, 74161 , 74163, LS160A, LS161A, LS162A, LS163A Counters Logic Products '160 , -bit ( 74161 , 74LS161 A, 74163, 74LS163A) counters feature an internal carry look ahead and can be used for


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PDF LS160A, LS161A, LS162A, LS163A 74LS160A, 74LS162A) 74LS161 74LS163A) 54LS/74LS F08270S ic 74160 IC 74160 decade counter diagram ic 74163 IC 74161 pin diagram of ic 74163 lm 74161 diagram of IC 74160 of 74160 ic LM 74160 diagram of IC 74161
74160 pin description

Abstract:
Text: transition of PE on the 74161 and 74160 should only occur while CP is HIGH for conventional operation. (d , decade (74160, 74LS160A, 74LS162A) and 4-bit ( 74161 , 74LS161A, 74163, 74LS163A) counters feature an , having all flip-flops clocked simultaneously on the positive-going edge of the clock. The Clock input is buffered. The outputs of the counters may be preset to HIGH or LOW level^A LOW level at the Parallel , into the counter on the positive-going edge of the clock (providing that the set-up and hold


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PDF 74LS160A, 74LS162A) 74LS161A, 74LS163A) LS160A, LS161A, LS162A, LS163A 74160 pin description 74160 pin diagram of 74163 74160 function table LS161A 74161 logic diagram of 74160 74163 74163 four bit binary counter LS161
74163 four bit binary counter

Abstract:
Text: conventional operation of 74160, 74161 and 74163, the following transitions should be avoided. 1. 2 , transition of CEP or CET on the 74161 and 74160 should only occur while CP is HIGH for conventional operation. (c)The LOW-to-HIGH transition of on the 74161 and 74160 should only occur while CP is HIGH for , S ig n e tic s 74160, 74161 , 74163, LS160A, LS161A, LS162A, LS163A Counters Logic Products , , 74LS162A) and 4-bit ( 74161 , 74LS161A, 74163, 74LS163A) counters feature an internal carry lookahead and can


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PDF LS160A, LS161A, LS162A, LS163A 74LS160A, 74LS162A) 74LS161A, 74LS163A) 54LS/74LS S4LS/74LS 74163 four bit binary counter LS162A 74163 pin configuration 162 bcd pin diagram of 74163 74160 function table pin diagram of 74160 counter diagram 74161 74160 counter LS160A
pin diagram of 74160

Abstract:
Text: transition of PE on the 74161 and 74160 should only occur while CP is HIGH for conventional operation. (d , Signetics 74160, 74161 , 74163, LS160A, LS161A, LS162A, LS163A Counters Logic Products , ) and 4-bit ( 74161 , 74LS161 A, 74163, 74LS163A) counters feature an internal carry look-ahead and can be , simultaneously on the positive-going edge of the clock. The Clock input is buffered. The outputs of the counters , edge of the clock (providing that the set-up and hold requirements for PE are met). Preset takes place


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PDF LS160A, LS161A, LS162A, LS163A 74LS160A, 74LS162A) 74LS161 74LS163A) 54ls/74ls pin diagram of 74160 74160 function table pin diagram of 74163 74160 pin 74163 pin configuration 74ls161 counter pin configuration 74160 logic diagram of 74160 logic diagram 74160 74160 counter
Not Available

Abstract:
Text: PE inputs are HIGH at or before the transi­ tion. For conventional operation of 74160, 74161 , (b)The HIGH-to-LOW transition of CEP or CET on the 74161 and 74160 should only occur while CP is HIGH for conventional operation. (c )T h e LOW-to-HiGH transition of PE on the 74161 and 74160 should only , 1 74160, 74161 , 74163, LS160A, LS161A, LS162A, LS163A S ig n e lic s Counters Logic , s e tta b le d e c a d e (74160, 74LS160A, 74LS162A) and 4-bit ( 74161 , 74LS161A, 74163, 74LS163A


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PDF LS160A, LS161A, LS162A, LS163A 32MHz 74LS160A 74LS163A 74LS160tput S4LS/74LS
Truth Table 74160

Abstract:
Text: . The LOW -to-HIGH transition of SPE on the 54/ 74161 and 54/74160 should only occur w hile CP is high , to a standard flow intended to meet the cost and shorter lead-time needs of large volume satellite , (SEU) Immunity < 2 x 10"9 Errors/Bit-Day (Typ) level of reliability. The Harris HCTS160T is a , the low-to-high transition of the clock. A low level on the synchronous parallel enable input, SPE , discharge; follow proper IC Handling Procedures. 1-800-4-H AR R IS | C opyright © Harris C orporation 1999


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PDF HCTS160T MIL-PRF-38535 100kRAD HCTS160T 1-800-4-HARRIS Truth Table 74160 Truth Table 74161
Truth Table 74161

Abstract:
Text: ark of Harris C orporation. HCTS160T Functional Diagram PO P1 P2 P3 TRUTH TABLE , HLLH for 160). 2. The H IG H-to-LO W transition of PE or TE on the 54/ 74161 and 54/74160 should only , devices are processed to a standard flow intended to meet the cost and shorter lead-time needs of large , - Single Event Upset (SEU) Immunity < 2 x 10"9 Errors/Bit-Day (Typ) level of reliability. The , accomplished synchronously with the low-to-high transition of the clock. A low level on the synchronous


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PDF HCTS160T MIL-PRF-38535 100kRAD HCTS160T 1-800-4-HARR Truth Table 74161
Truth Table 74160

Abstract:
Text: atellite A pplications FlowTM (SAF) is a tradem ark of Harris C orporation. HCTS160T Functional Diagram , transition of PE or TE on the 54/ 74161 and 54/74160 should only occur while CP is high for conventional operation. 3. The LOW -to-HIGH transition of SPE on the 54/ 74161 and 54/74160 should only occur w hile CP is , intended to meet the cost and shorter lead-time needs of large volume satellite manufacturers, while maintaining a high level of reliability. The Harris HCTS160T is a Radiation Hardened High Speed Presettable


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PDF HCTS160T 100kRAD HCTS160T 1-800-4-HARR Truth Table 74160 IC 74160 IC 74161 Truth Table 74161
2002 - IC 74160

Abstract:
Text: . The HIGH-to-LOW transition of PE or TE on the 54/ 74161 and 54/74160 should only occur while CP is high for conventional operation. 3. The LOW-to-HIGH transition of SPE on the 54/ 74161 and 54/74160 should , standard flow intended to meet the cost and shorter lead-time needs of large volume satellite manufacturers, while maintaining a high level of reliability. The Intersil HCTS160T is a Radiation Hardened , low-to-high transition of the clock. A low level on the synchronous parallel enable input, SPE, disables


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PDF HCTS160T FN4626 MIL-PRF-38535 100kRAD HCTS160T IC 74160 Truth Table 74161 ic 74161 Truth Table 74160 IC 74160 decade counter diagram IC 74160 DATA SHEET logic diagram of 74160 data sheet IC 74161 HCTS160KTR IC 74160 decade counter
1999 - Truth Table 74160

Abstract:
Text: trademark of Intersil Corporation. HCTS160T Functional Diagram P0 P1 3 P2 4 P3 5 6 , HLLH for 160). 2. The HIGH-to-LOW transition of PE or TE on the 54/ 74161 and 54/74160 should only occur while CP is high for conventional operation. 3. The LOW-to-HIGH transition of SPE on the 54/ 74161 , standard flow intended to meet the cost and shorter lead-time needs of large volume satellite manufacturers, while maintaining a high level of reliability. The Intersil HCTS160T is a Radiation Hardened


Original
PDF HCTS160T MIL-PRF-38535 100kRAD HCTS160T Truth Table 74160 IC 74160 ic 74161 Truth Table 74161 IC 74160 DATA SHEET IC 74160 decade counter diagram data sheet IC 74161 HCTS160KTR HCTS160 CDFP4-F16
sn 74373

Abstract:
Text: graphic and text designs S chem atic captu re with Valid Logic's V alidG KD or V iew log ic 's V iew d ra w , relational operations Full A lte ra /V a lid Logic and A l te r a /V ie w lo g ic cro ss-com patibility via , V ie w log ic V iew sim chip- and board-level sim ulators or with Logic A u to m a tio n 's S m artM , , Valid L ogic and V iew logic library 9 Figure 1. PLS-WS/SN Block Diagram Valid Logic/Viewlogic , are entered either with V a lid G E D by Valid Logic or with V ie w d raw by V iew log ic (see Figure


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PDF
74191, 74192, 74193 circuit diagram

Abstract:
Text: a rd w a re Figure 1. PLS-WS/HP Block Diagram Device Simulation Board Simulation - Shading , pplications for the most up-to-date list of m appings. Table 2. Mentor Graphics Library Mapping File-Macrofunctions (P arti of 3) Mentor Graphics 74LSTTL Function 74LS00 74LS02 74LS04 74LS08 74LS10 74LS11 74LS20 , /HP Data Sheet Table 2. Mentor Graphics Library Mapping File-Macrofunctions (Part 2 of 3 , 74147 74148 74151 74153 74154 74155 74156 74157 74158 74160 74161 74162 74163 74164 74165 74166 74168


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PDF HP400 QIC-24, 60-Mbytetape 74191, 74192, 74193 circuit diagram Truth Table 74161 IC 7402, 7404, 7408, 7432, 7400 counter schematic diagram 74161 7408, 7404, 7486, 7432 74244 uses and functions counter 74168 truth table of ic 7495 A 74191, 74192, 74193 schematic diagram for the IC of 7411
Not Available

Abstract:
Text: terminal count (HHHH for 161 and HLLH for 160) 2. The HIGH-to-LOW transition of PE or T E o n the 54/ 74161 , transition of SPE on the 54/ 74161 and 54/74160 should only occur while CP is high for conventional operation , are accomplished synchro­ nously with the low-to-high transition of the clock. A low level on the , device is a member of radiation hardened, high-speed, CMOS/SOS Logic Family. The HCTS160MS is supplied , I.C . Handling Procedures. Copyright © H arris C orporation 1992 _ 7-351 File Number


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PDF HCTS160MS MIL-STD-1835 CDIP2-T16,
1998 - MSM6999

Abstract:
Text: MSM6996H/6996V/6997H/6997V/6998/6999 Example of Multi-Channel Connections (8ch) +5 V 74161 (1) 2 1 , CMOS ICs containing filters for A/D and D/A converting of the voice signal ranging from 300 Hz to 3400 , /MSM6997V/MSM6999 : m-law · Capable of independent operation of transmission and reception · Transmission clock in the range of 64 kHz to 2048 kHz · Adjustable transmit gain · 600 W drive for analog output , ) 1/21 ¡ Semiconductor MSM6996H/6996V/6997H/6997V/6998/6999 BLOCK DIAGRAM MSM6996H/V


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PDF E2U0010-28-81 MSM6996H/6996V/6997H/6997V/6998/6999 SM6996V/MSM6997H/MSM6997V/MSM6998/MSM6999 MSM6996H/MSM6996V/MSM6998 MSM6997H/MSM6997V/MSM6999 MSM6996H/MSM6996V/MSM699 OP24-P-430-1 MSM6999 74164 with ic PIN DIAGRAM IC 74164 IC 74161 ic 74164 data sheet pin diagram of ic 74164 V74161 MSM6999AS PLL 4049
1998 - MSM6999

Abstract:
Text: .3 No.8 Example of Multi-Channel Timing 74161 (1) QC Output 74161 (2) QB Output QA 74164 Output , CMOS ICs containing filters for A/D and D/A converting of the voice signal ranging from 300 Hz to 3400 , /MSM6997V/MSM6999 : m-law · Capable of independent operation of transmission and reception · Transmission clock in the range of 64 kHz to 2048 kHz · Adjustable transmit gain · 600 W drive for analog output , ) 1/21 ¡ Semiconductor MSM6996H/6996V/6997H/6997V/6998/6999 BLOCK DIAGRAM MSM6996H/V


Original
PDF E2U0010-28-81 MSM6996H/6996V/6997H/6997V/6998/6999 SM6996V/MSM6997H/MSM6997V/MSM6998/MSM6999 MSM6996H/MSM6996V/MSM6998 MSM6997H/MSM6997V/MSM6999 MSM6996H/MSM6996V/MSM699 OP24-P-430-1 MSM6999 IC 74164 pin diagram of ic 74164 74161 MSM6999AS MSM6997 M4520 IC 74161 74164 with ic PIN DIAGRAM V74161
16CUDSLR

Abstract:
Text: PL D s H ierarch ical d esig n entry m eth o d s for b oth g rap h ic and text d esig n s M u , , arithm etic and relational op eration s D elay p red iction and tim ing an aly sis fo r g ra p h ic an d , create, verify, and program com p lex logic d esig n s. Figure 1 sh o w s a b lock d iagram of M A X +P L U S . Figure 1. MAX+PLUS Block Diagram MAX+PLUS Design Processing (Compiler) T h e P L D S-M , ith a variety of d esign entry m ethods. M A X +P L U S su p p orts hierarch ical en try o f b oth G


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PDF 7400-series 486-b 16CUDSLR alu 74382 7474 D flip flop free pin diagram of ic 74190 sn 74373 counter schematic diagram 74161 HFJV1 ALU IC 74381 MUX 74151 IC 74373 truth table
74160 pin layout

Abstract:
Text: HIGH-to-LOW transition of PE or TE on the 54/ 74161 and 54/74160 should only occur while CP is high for conventional operation 3. The LOW-to-HIGH transition of SPE on the 54/ 74161 and 54/74160 should only occur , parallel presetting are accomplished synchro nously with the iow-to-high transition of the clock. A low , achieve high-speed operation. This device is a member of radiation hardened, high-speed, CMOS/SOS Logic , . Users should follow p roper I.C . Handling Procedures. Copyright © H arris C orporation 1992 7 351


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PDF HCTS160MS MIL-STD-1835 CDIP2-T16, 05A/cm2 74160 pin layout
IC 74160

Abstract:
Text: -to-HIGH transition of SPE on the 54/ 74161 and 54/74160 should only occur while CP is high for conventional , static burn-in 2. Each pin except VCC and GND will have a resistor of 1 K ii ± 5% for dynam ic burn-in , Pinouts 16 LEAD CERAM IC DUAL-IN-LINE METAL SEAL PACKAGE (SBDIP) M IL-STD-1835 CDIP2-T16, LEAD FINISH C , Input Logic Levels -VIL = 30% of VCC Max -VIH = 70% of VCC Min · Input Current Levels li < 5 ^ @ VOL , . Counting and parallel presetting are accomplished synchronously with the lowto-high transition of the clock


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PDF HCS160MS IL-STD-1835 CDIP2-T16, IC 74160
Truth Table 74161

Abstract:
Text: . The LOW-to-HIGH transition of SPE on the 54/ 74161 and 54/74160 should only occur while CP is high for , . Counting and parallel presetting are accomplished synchronously with the lowto-high transition of the clock , high-speed operation. This device is a member of radiation hardened, high-speed, CMOS/SOS Logic Family. The H C T S 16 0M S is s u p p lie d in a 16 lead C e ra m ic fla tp a c k (K su ffix) or a S BD IP P , electrostatic discharge. Users should tollow proper I.C . Handling Procedures. Copyright ©Harris Corporation 1995


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PDF HCTS160MS MIL-STD-1835 CDIP2-T16 CTS160 HCTS160 TA14445A. Truth Table 74161 74161 pin diagram and truth table
74160 pin layout

Abstract:
Text: Duration of tha Mi ort circuit tast tfiouM not axcaad on* mcckvJ. 6. içc to masaurad «vitti aU outputs , multiplanar*. DEFINITION OF FUNCTIONAL TERMS ICj, 2Cj Data Inputs. The four data inputs to each multiplexer ¡ = 0,1,2, and 3. 1Y,2Y Multiplexer Outputs. The output of each four-input multiplexer. A, B Select Inputs. The inputs used to determine which of the four inputs are selected for the output. G , regardless of the other inputs. LOADING RULES (In Unit Loads) Fan-out Output Output Input/Output Pin No 's


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PDF 150ft Am74163 Am64153 74160 pin layout am7416 IC 74160 DATA SHEET ic 74163 AM-7416 pin diagram of ic 74163 pin diagram of 74163 pins and their function in ic 74163 7416l data sheet IC 74161
IC 74160 decade counter diagram

Abstract:
Text: ). (b) The HIGH-to-LOW transition of PE or TE on the 54/ 74161 and 54/74160 should only occur while CP is HIGH for conventional operation. (c) The LOW-to-HIGH transition of SPE on the 54/ 74161 and 54 , High-Speed CMOS Logic FUNCTIONAL DIAGRAM PO PI P2 PÎ Presettable Counters C D 54/74H C /H C T160 CD54 , negative-to-positive transition of the clock. _ A low level on the synchronous parallel enable input, SPE, disables , each counter are pro vided for n-bit cascading. In all counters reset action occurs regardless of the


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PDF CD54/74HC/HCT160, CD54/74HC/HCT161 CD54/74HC/HCT162, CD54/74HC/HCT163 54/74H CD54/74H CT161 IC 74160 decade counter diagram 74163 four bit binary counter 92C540 CD74HC160 counter diagram 74161 IC 74160 for decade counter ND06 pin diagram of ic 74163
Not Available

Abstract:
Text: 161 and HLLH for 160) 2. The HIGH-to-LOW transition of PE or TE on the 54/ 74161 and 54/74160 should , transition of the c lock. A low level on the synchronous parallel enable input, SPE, disables counting and , CMOS/SOS technology to achieve high-speed operation. This device is a member of radiation hardened, high-speed, CMOS/SOS Logic Family. The H C T S 1 6 0 M S is s u p p lie d in a 16 lead C e ra m ic fla tp a , v ic e s a re s e n s itiv e to e le c tro s ta tic d is c h a rg e . U s e rs s h o u ld fo llo w p


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PDF HCTS160MS 05A/cm HCTS160 isTA14445A.
CD74HCT160

Abstract:
Text: count as shown in state diagram . The look-ahead carry feature simplifies serial cascading of the , transition of PE or TE on the 54/ 74161 and 54/74160 should only occur while CP is HIGH for conventional operation. (c) The LOW-to-HIGH transition of SPE on the 54/ 74161 and 54/74160 should only occur while CP is , /74HC/HCT163 High-Speed CMOS Logic FUNCTIONAL DIAGRAM PO PI PZ P3 Presettable Counters C D54 , presetting are both accomplished synchronously with the negative-to-positive transition of the clock. A low


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PDF CD54/74HC/HCT160, CD54/74HC/HCT161 CD54/74HC/HCT162, CD54/74HC/HCT163 D54/74H CT160 CT162 54/74H CD74HCT160 IC 74160 decade counter diagram pin diagram of ic 74163
Not Available

Abstract:
Text: transition of PE o r TE on the 54/ 74161 and 54/74160 should only occur while CP is high for conventional operation 3. The LOW -to-HIGH transition of SPE on the 54/ 74161 and 54/74160 should only occur while CP is , ND will have a resistor of 1 K ii ± 5% for dynam ic burn-in TABLE 9. IRRADIATION TEST CONNECTIONS , LSTTL ICs • DC Operating Voltage Range: 4.5V to 5.5V • Input Logic Levels -VIL = 30% of VCC Max -VIH = 70% of VCC Min 16 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE (FLATPACK) MIL-STD-1835 CDFP4-F16


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PDF 160MS MIL-STD-1835 CDIP2-T16, x1012 HCS160MS 05A/cm2
Supplyframe Tracking Pixel