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Part Manufacturer Description Datasheet Download Buy Part
LTC2400I Linear Technology IC 1-CH 24-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO8, 0.150 INCH, PLASTIC, SO-8, Analog to Digital Converter
LTC1966MPMS8#PBF Linear Technology LTC1966 - Precision Micropower, Delta Sigma RMS-to-DC Converter; Package: MSOP; Pins: 8; Temperature Range: -55°C to 125°C
LTC2451ITSB#TRMPBF Linear Technology IC 1-CH 16-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO8, LEAD FREE, PLASTIC, MO-193, TSOT-23, 8 PIN, Analog to Digital Converter
LTC1966IMS8#PBF Linear Technology LTC1966 - Precision Micropower, Delta Sigma RMS-to-DC Converter; Package: MSOP; Pins: 8; Temperature Range: -40°C to 85°C
LTC2420IS8#TRPBF Linear Technology LTC2420 - 20-Bit µPower No Latency Delta-Sigma ADC in SO-8; Package: SO; Pins: 8; Temperature Range: -40°C to 85°C
LTC2450CDC-1#TRPBF Linear Technology LTC2450-1 - Easy-to-Use, Ultra-Tiny 16-Bit Delta Sigma ADC; Package: DFN; Pins: 6; Temperature Range: 0°C to 70°C

delta v dcs Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
2003 - gsm module 900

Abstract: delta v dcs B100 DLT3201 GSM900 NL-5928
Text: +6 V Input RF Power +12 dBm Control Voltage +3.5 V Storage Temperature -55 , Bottom View 4 5 6 7 0.9 1 10 DLT3201 PIN-OUT CONFIGURATION VCC 1 14 DCS /PCS i DCS /PCS 2 13 GND DCS /PCS 3 12 GND GND 4 11 VCC GSM Vpc 5 , 12 13 14 27 Description Power supply for the driver stage of the DCS /PCS band DCS /PCS RF in 50 ohm RF input of DCS /PCS band DCS /PCS Vpc Power control for the DCS /PCS band GND Package


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PDF DLT3201 GSM900 DCS1800/PCS1900 GSM900; DCS1800/PCS1900 DLT3201 NL-5928 FIN-00101, gsm module 900 delta v dcs B100
2004 - Not Available

Abstract: No abstract text available
Text: 1880 DCS BAND (Pin = 5.0 to 11 dBm, Vdd = 3.2 Vdc, VAPC = 0.1 to 2.2 V pulsed, 25% duty cycle , applications, functioning over the GSM850, EGSM, DCS , and PCS transmit and receive frequency bands. It is , controlled through 0/2.8 V logic inputs. Ordering Information Device Operating Temperature Package , (GSM850, EGSM, DCS , and PCS) power amplifier module. VDD3_HB VDDB_HB, VDD1_HB VDD2_HB RX_CEL , Drain Supply Voltages Vdd 7.0 V RF Input Power Pin 11 dBm Operating (Case


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PDF MMM6025 MMM6025 GSM850,
2004 - MMM6025

Abstract: MMM6025R2
Text: ) without RF], and Delta (25°C)= [Vdiff(25°C) with RF] - [Vdiff(25°C) without RF] Table 6. DCS Band , , DCS , and PCS transmit and receive frequency bands. It is compatible with GSM/GPRS Class 12 operating , Front-End Module. Transmit/receive path and enable functions are controlled through 0/2.8 V logic inputs , Diagram Figure 1 is a functional block diagram of the quad-band (GSM850, EGSM, DCS , and PCS) power , Table 1. Maximum Ratings Rating Symbol Value Unit Drain Supply Voltages Vdd 7.0 V


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PDF MMM6025 MMM6025R2 MMM6025 GSM850, MMM6025R2
2004 - Not Available

Abstract: No abstract text available
Text: Max Unit DCS BAND (Pin = 5.0 to 11 dBm, Vdd = 3.2 Vdc, VAPC = 0.1 to 2.2 V pulsed, 25% duty cycle , the GSM850, EGSM, DCS , and PCS transmit and receive frequency bands. It is compatible with GSM/GPRS , /2.8 V logic inputs. This document contains information on a new product. Specifications and , functional block diagram of the quad-band (GSM850, EGSM, DCS , and PCS) power amplifier module. VDD3_HB , 7.0 11 ­20 to 70 ­40 to 125 125 Unit V dBm °C °C °C Drain Supply Voltages RF Input Power Operating


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PDF MMM6025 MMM6025 MMM6025R2
2012 - DCS12S0A0S06

Abstract: No abstract text available
Text: technology and manufacturing - Delta Electronics, Inc. The DCS series provides a programmable output voltage from 0.59 V to 5.5V using an external resistor and has flexible and programmable tracking features to , Canada) CE mark meets 73/23/EEC and 93/68/EEC directives Delphi DCS , Non-Isolated Point of Load DC/DC Power Modules: 4.5~14Vin, 0.59-5.5V/6Aout The Delphi Series DCS , 4.5-14V input, single output , max 85 125 14.0 4.4 3.2 0.4 Units V V V V V A mA mA 1 A2S mAp-p %Vo,set V %Vo,set mV mV mV %Vo,set


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PDF 12Vin, 59Vdc QS9000, OHSAS18001 73/23/EEC 93/68/EEC 14Vin, DC/D31 x6220 DCS12S0A0S06PFA DCS12S0A0S06
2012 - Not Available

Abstract: No abstract text available
Text: manufacturing - Delta Electronics, Inc. The DCS series provides a programmable output voltage from 0.6V to 3.3V , facility UL/cUL 60950-1 (US & Canada) Delphi DCS , Non-Isolated Point of Load DC/DC Power Modules: 2.4-5.5Vin, 0.6-3.63V/6Aout OPTIONS The Delphi Series DCS , 2.4-5.5V input, single output, non-isolated Point , Min. -0.3 -0.3 -40 -55 Typ. Max. 6 Vin,max 85 125 5.5 2.2 2.0 Units Vdc Vdc °C V V V A mA mA A2S mAp-p dB +1.5 3.63 0.4 10 10 5 0.4 +3.0 25 10 0 35 15 6 1 200 % Vo,set V % Vo,set mV mV mV % Vo,set % Vo


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PDF DCS04S0A0S06NFA QS9000, OHSAS18001 x6220 DCS04S0A0S06NFA
Not Available

Abstract: No abstract text available
Text: Delphi DCS , Non-Isolated Point of Load DC/DC Power Modules: 4.5~14Vin, 0.59-5.0V/6Aout The Delphi Series DCS , 4.5-14V input, single output, non-isolated Point of Load DC/DC converters are the latest offering from a world OPTIONS leader in power systems technology and manufacturing - Delta  Negative/Positive on/off logic Electronics, Inc. The DCS series provides a programmable output  Tracking feature voltage from 0.59 V to 5.0V using an external resistor and has flexible and


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PDF 12Vin, 59Vdc QS9000, OHSAS18001 73/23/EEC 93/68/EEC DCS12S0A0S06NFA
Not Available

Abstract: No abstract text available
Text: leader in power systems technology and manufacturing - Delta Electronics, Inc. The DCS series provides , & Canada) Delphi DCS , Non-Isolated Point of Load DC/DC Power Modules: 2.4-5.5Vin, 0.6-3.63V/6Aout OPTIONS The Delphi Series DCS , 2.4-5.5V input, single output, non-isolated Point of Load DC/DC , ,max 85 125 Vdc Vdc ℃ °C 2.4 5.5 V 2.2 2.0 15 5 (5Hz to 20MHz, 1μH source , Line V V A mA mA A2S Vin=2.4V to 5.5V, Io=Io,max Vin=5V Vin=5V Input Ripple Rejection


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PDF DCS04S0A0S06NFA QS9000, OHSAS18001 DCS04S0A0S06NFA
1998 - tetra system block diagram

Abstract: CMX808AE3 CTCSS dqpsk modulation tetra FX828D2 selcall tetra modulation block diagram dqpsk demodulator VOCODER tetra
Text: 20TSSOP PACKAGE FX828 CTCSS, DCS , SELCALL PROCESSOR · FAST CTCSS TONE DETECTION · FULL 23/24 BIT DCS CODEC , FILTERS, 2 14 BIT SIGMA DELTA DAC AND 2 16 BIT SIGMA DELTA ADC · /4 DQPSK MODULATION AND CAN CONTROL , Family Radio CTCSS `Type 2' Encoder & Decoder CTCSS, DCS , Selcall Processor CTCSS, DCS , Selcall Processor , Volume Control Serial C-Bus Data & Control FX828 Fast CTCSS Selcall DCS Carrier Detect Timer Level


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PDF CMX808A 140ms 251Hz 20TSSOP FX828 FX829 SOIC24 SSOP24 TSSOP20 PLCC44 tetra system block diagram CMX808AE3 CTCSS dqpsk modulation tetra FX828D2 selcall tetra modulation block diagram dqpsk demodulator VOCODER tetra
2010 - 1002-6200-8P0

Abstract: D-Sub 44-pin male Connector B.P.F FM m audio delta 410 pinout pcb 200W audio amplifier ES 5106 V 734 coaxial cable data 62368 cpu aeroflex AC27013
Text: . DCS Decode Meter . , -3 A-4 A-5 A-6 Subject to Export Control, see Cover Page for details. v SERVICE UPON , ) T / R C o n n e c t o r ( d B m / V ) : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 5 0 t o - 1 2 0 d B m / 7 0 7 . 1 t o 0 . 2 V A N T C o n n e c t o r ( d B m / V ) : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .


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PDF
CVSD demodulator

Abstract: No abstract text available
Text: FX429A FX529 FX809 FX829 PROCESSING SIGNALLING SIGNALLING CTCSS DCS FX315 FX365C , : o Non-Predictive Sub-Audio Tone Decoder o Sub-Audio Tone Encoder o Digitally Coded Squelch ( DCS ) Decoder o Digitally Coded Squelch ( DCS ) Encoder o Transmit Level Adjustment o Audio Path with , NRZ DATA Applications: ¨ CTCSS Systems ¨ DCS Systems ¨ Scanning for Trunked Systems  , VBIAS CLOCK GENERATOR plus DCS REPLY DATA NRZ Rx DATA AND BAUD RATE EXTRACTOR TX


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PDF FX803 FX829 FX828 FX429A FX529 FX809 FX315 FX365C CVSD demodulator
STD XTL 200.000KHz

Abstract: EPSON CA-301 20.000M-C
Text: operating range (i.e., outside specified V dd range). This is for information only and devices will operate , 31.3.1 I p d v s . V dd Ipd is the current (I) that the device consum es when the device is in sleep , ­ culated as the base current (everything disabled and in sleep mode) plus all delta currents. Example 31-1 , ) Base Current W DT Delta Current T im e rl Delta Current Total Sleep Current © 1997 Microchip , Typical I pd Figure 31-4: Exam ple Maximum vs. Ip d V dd @ 25°C (W DT Enabled, RC Mode


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PDF DS31031A DS31031 STD XTL 200.000KHz EPSON CA-301 20.000M-C
2003 - Not Available

Abstract: No abstract text available
Text: shown. 3. Unless otherwise noted, resister values are 22 Ohms * S0 connects to DCS and VDD connects , SDRAMs D9-D17 CK0 * S0 connects to DCS and S0 connects to CSR on a Register, S1 connects to DCS and S0 , otherwise noted, resister values are 22 Ohms * S0 connects to DCS of Register1, CSR of Register2. CSR of register 1 and DCS of register 2 connects to VDD * RESET, PCK7 and PCK7 connects to both Registers. Other , SDA V / V RS1-> CS : DDR2 SDRAMs D18-D35 D0 - D35 DD DDQ WP A0 A1 A2 RBA0-RBA1 -> BA0-BA1 : DDR2 SDRAMs


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PDF 512MB, 240pin 512Mb 72-bit M393T6553BG0-CE6/D5/CC M393T6553BG0-LE6/D5/CC M393T2953BG0-CEered
1997 - TPS5908

Abstract: TPS5910 TPS5910A TLV431 TPS5908A linear opto coupler
Text: EN60065/IEC 65 ­ EN60950/IEC 950 ­ VDE 0884, Level 4 (6000- V Insulation) DCS OR P PACKAGE (TOP VIEW , TEMPERATURE Vref / VI(LED) ­ Ratio of Delta Reference Voltage to Delta LED Voltage ­ V 1.250 VO(COMP) = , REVISED JANUARY 1998 D D D D D TLV431 Precision Programmable Reference (1.24 V ) and an , , TPS5910 100% to 400% TPS5908A, TPS5910A 150% to 300% High Withstand Voltage (WTV), 7500 V Peak for 1 , or in an 8-pin gull-wing surface-mount package ( DCS ). typical application + + VI VO PWM


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PDF TPS5908, TPS5908A, TPS5910, TPS5910A SOES030B TLV431 TPS5910 TPS5910A TPS5908 TPS5910 TPS5908A linear opto coupler
2007 - ADC12DS065

Abstract: ADC12DS080 ADC12DS080CISQ ADC12DS095 ADC12DS105 ADC12DS105CISQ
Text: / DCS This is a four-state pin controlling the input clock mode and output data format. OF/ DCS = VA, output data format is 2's complement without duty cycle stabilization applied to the input clock OF/ DCS , clock. OF/ DCS = (2/3)*VA, output data is 2's complement with duty cycle stabilization applied to the input clock OF/ DCS = (1/3)*VA, output data is offset binary with duty cycle stabilization applied to , ) (ADC12DS065,ADC12DS080) (ADC12DS095,ADC12DS105) Clock Duty Cycle ( DCS Enabled) ( DCS disabled) VCM


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PDF C12DS065/ADC12DS080/ADC12DS095/ADC12DS105 12-Bit, ADC12DS065, ADC12DS080, ADC12DS095, ADC12DS105 12-bit ADC12DS065 ADC12DS080 ADC12DS080CISQ ADC12DS095 ADC12DS105CISQ
2007 - ADC14DS065

Abstract: ADC14DS080 ADC14DS080CISQ ADC14DS095 ADC14DS105 ADC14DS105CISQ
Text: the DLL. The DLL will lock in several microseconds after Reset_DLL is asserted. OF/ DCS This is a four-state pin controlling the input clock mode and output data format. OF/ DCS = VA, output data format is 2's complement without duty cycle stabilization applied to the input clock OF/ DCS = AGND , / DCS = (2/3)*VA, output data is 2's complement with duty cycle stabilization applied to the input clock OF/ DCS = (1/3)*VA, output data is offset binary with duty cycle stabilization applied to the


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PDF C14DS065/ADC14DS080/ADC14DS095/ADC14DS105 14-Bit, ADC14DS065, ADC14DS080, ADC14DS095, ADC14DS105 14-bit ADC14DS065 ADC14DS080 ADC14DS080CISQ ADC14DS095 ADC14DS105CISQ
1997 - TPS5910A

Abstract: TPS5910 TPS5908
Text: /IEC 950 ­ VDE 0884, Level 4 (6000- V Insulation) DCS OR P PACKAGE (TOP VIEW) LED COMP GND FB 1 , Reference Voltage to Delta LED Voltage ­ V 0 VI(LED) = 3 V to 7 V II(LED) = 10 mA ­ 0.1 REFERENCE VOLTAGE , REVISED JANUARY 1998 D D D D D TLV431 Precision Programmable Reference (1.24 V ) and an Optocoupler , % to 400% TPS5908A, TPS5910A 150% to 300% High Withstand Voltage (WTV), 7500 V Peak for 1 Minute Safety , package ( DCS ). typical application + + VI PWM Control VO TPS5908 TPS5908A TPS5910 TPS5910A 1 2 6 4 3


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PDF TPS5908, TPS5908A, TPS5910, TPS5910A SOES030B TLV431 TPS5910 TPS5908
1997 - TPS5908

Abstract: TPS5910 TPS5910A TPS5908DCS TLV431 TPS5908A
Text: EN60065/IEC 65 ­ EN60950/IEC 950 ­ VDE 0884, Level 4 (6000- V Insulation) DCS OR P PACKAGE (TOP VIEW , TEMPERATURE Vref / VI(LED) ­ Ratio of Delta Reference Voltage to Delta LED Voltage ­ V 1.250 VO(COMP) = , REVISED JANUARY 1998 D D D D D TLV431 Precision Programmable Reference (1.24 V ) and an , , TPS5910 100% to 400% TPS5908A, TPS5910A 150% to 300% High Withstand Voltage (WTV), 7500 V Peak for 1 , or in an 8-pin gull-wing surface-mount package ( DCS ). typical application + + VI VO PWM


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PDF TPS5908, TPS5908A, TPS5910, TPS5910A SOES030B TLV431 TPS5910 TPS5910A TPS5908 TPS5910 TPS5908DCS TPS5908A
2004 - BF96A

Abstract: CY2SSTU32864 Q11A delta v dcs t1 96x M4F4
Text: LVCMOS. All outputs are 1.8- V CMOS drivers that have been optimized to drive the DDR-II DIMM load. The , or it doesn't defaults to the C0 = C1 = 0 state. The device monitors both DCS # and CSR# inputs and will gate the Qn outputs from changing states when both DCS # and CSR# inputs are high. If either DCS # or CSR# input is low, the Qn outputs will function normally. The RESET input has priority over the DCS # and CSR# control and will force the outputs low. If the DCS#-control functionality is not


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PDF CY2SSTU32864 25-bit 14-bit 96-ball CY2SSTU32864 BF96A Q11A delta v dcs t1 96x M4F4
2006 - JESD82-7A

Abstract: No abstract text available
Text: :2) · 1.8V operation · Fully JEDEC-compliant (JESD82-7A) · 96-ball FBGA The device monitors both DCS # and CSR# inputs and will gate the Qn outputs from changing states when both DCS # and CSR# inputs are high. If either DCS # or CSR# input is low, the Qn outputs will function normally. The RESET input has priority over the DCS # and CSR# control and will force the outputs low. If the DCS#-control functionality , for DCS # would be the same as for the other D data inputs. The device supports low-power standby


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PDF CY2SSTU32864 25-bit 14-bit JESD82-7A) 96-ball JESD82-7A
JESD82-7A

Abstract: CY2SSTU32864 Q11A Q13A D1525 delta v dcs BP96A
Text: Delta between Rising/Falling Rates 3 1 ns 4 V /ns 1 4 V /ns ­ 1 V /ns , device monitors both DCS # and CSR# inputs and will gate the Qn outputs from changing states when both DCS # and CSR# inputs are high. If either DCS # or CSR# input is low, the Qn outputs will function normally. The RESET input has priority over the DCS # and CSR# control and will force the outputs low. If , case the set-up time requirement for DCS # would be the same as for the other D data inputs. ·


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PDF CY2SSTU32864 25-bit 14-bit JESD82-7A CY2SSTU32864 Q11A Q13A D1525 delta v dcs BP96A
2005 - JESD82-7A

Abstract: CY2SSTU32864 Q11A Q13A DCS complete notes delta v dcs t4 a4 BA96A
Text: Delta between Rising/Falling Rates 3 1 ns 4 V /ns 1 4 V /ns ­ 1 V /ns , Features The device monitors both DCS # and CSR# inputs and will gate the Qn outputs from changing states when both DCS # and CSR# inputs are high. If either DCS # or CSR# input is low, the Qn outputs will function normally. The RESET input has priority over the DCS # and CSR# control and will force the , , in which case the set-up time requirement for DCS # would be the same as for the other D data inputs


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PDF CY2SSTU32864 25-bit 14-bit CY2SSTU32864 JESD82-7A Q11A Q13A DCS complete notes delta v dcs t4 a4 BA96A
2010 - 201236a

Abstract: SKY77344 SKY77344-21 power amplifier circuit diagram with pcb layout schematic diagram power amplifier free download Power Amplifier Module for GSM cellular phone amplifier power control transistor schematics for a PA amplifier GMSK gsm GSM module circuit diagram
Text: /EGSM_TX EDGE 2.0 V High DCS /PCS_TX EDGE 2.0 V High CEL/EGSM_TX GMSK 2.0 V Low DCS /PCS_TX GMSK 2.0 V Low SKY77344-21 Test Fixture The SKY77344-21 test fixture assembly is , module also contains band select switching circuitry to select GSM (logic 0) and DCS /PCS (logic 1) as , For GMSK operation, set EN input high and MODE low (< 0.5 V ). Select the desired TX band by setting the BS low (CEL/EGSM) or high ( DCS /PCS). VRAMP is a pulsed ramp input that controls the module output


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PDF SKY77344-21 SKY77344 GSM850/900, DCS1800/ PCS1900, 201236a power amplifier circuit diagram with pcb layout schematic diagram power amplifier free download Power Amplifier Module for GSM cellular phone amplifier power control transistor schematics for a PA amplifier GMSK gsm GSM module circuit diagram
1998 - vending machine pic microcontroller

Abstract: FX101L FX829D2 vhf gmsk receiver CMX589A FX614 vhf fsk modem ic FX604D4 EV6020 mixing tank metering pump
Text: IN CTCSS Tx TONE GENERATOR CTCSS/ DCS /Selcall Tx Single 3.0 V to 5.5V supply RX AUDIO , Voiceband Inverter FX818 CTCSS Super Codec FX828 CTCSS + DCS + Selcall Codec FX829 , FX828 Mobile Radio CTCSS + DCS + Selcall Codec FX829 Baseband Signal Processor VHF and UHF , Evaluation Kits CTCSS FX315 FX365C FX805 FX818 FX828 FX805 FX828 CMX017 CMX018 DCS , Squelch ( DCS ) Decoder o Digitally Coded Squelch ( DCS ) Encoder o Transmit Level Adjustment o Audio Path


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PDF FX301L/FX401 FX3090 FX407A/FX507A/407S/507S/607N FX4070A/FX5070A/FX4071A/5071A FX409 FX489 FX501/FX601 FX503 FX503A FX701 vending machine pic microcontroller FX101L FX829D2 vhf gmsk receiver CMX589A FX614 vhf fsk modem ic FX604D4 EV6020 mixing tank metering pump
2004 - CY2SSTU32864

Abstract: Q11A Q13A Q15-25 CY2SSTU32864BVXIT CY2SSTU32864BVXI BA96A t1 96x
Text: are LVCMOS. All outputs are 1.8- V CMOS drivers that have been optimized to drive the DDR-II DIMM , either it does or it doesn't defaults to the C0 = C1 = 0 state. The device monitors both DCS # and CSR# inputs and will gate the Qn outputs from changing states when both DCS # and CSR# inputs are high. If either DCS # or CSR# input is low, the Qn outputs will function normally. The RESET input has priority over the DCS # and CSR# control and will force the outputs low. If the DCS#-control functionality is


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PDF CY2SSTU32864 25-bit 14-bit 96-ball CY2SSTU32864 Q11A Q13A Q15-25 CY2SSTU32864BVXIT CY2SSTU32864BVXI BA96A t1 96x
Supplyframe Tracking Pixel