The Datasheet Archive

Top Results (4)

Part ECAD Model Manufacturer Description Datasheet Download Buy Part
LTC1519IS#PBF LTC1519IS#PBF ECAD Model Analog Devices Inc High Speed, Precision Delay RS485 Quad Line Receivers Visit Analog Devices Inc
LTC1519CS#PBF LTC1519CS#PBF ECAD Model Analog Devices Inc High Speed, Precision Delay RS485 Quad Line Receivers Visit Analog Devices Inc
LTC1519CS#TRPBF LTC1519CS#TRPBF ECAD Model Analog Devices Inc High Speed, Precision Delay RS485 Quad Line Receivers Visit Analog Devices Inc
LTC1519IS#TRPBF LTC1519IS#TRPBF ECAD Model Analog Devices Inc High Speed, Precision Delay RS485 Quad Line Receivers Visit Analog Devices Inc

delay line 100ns Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
Burr Brown part marking

Abstract: KT354 OPA2680 OPA2681 OPA2682 OPA3680 OPA3681 OPA368Q OPA681 OPA682
Text: OV0 Buffered Analog Delay Line ( 100ns ) International A irport Industrial Park · Mailing Address , / 100ns APPLICATIONS · · · · · · · VIDEO LINE DRIVING xDSL LINE DRIVER HIGH-SPEED IMAGING CHANNELS ADC , LINE The diagram on the front page of this data sheet shows an analog delay line using the OPA3680. The first op amp buffers the delay line from the source, and can be used to establish the DC operating point , delay of 100ns . Excellent pulse fidelity will be retained as long as the first 5 harmonics are delayed


OCR Scan
PDF OPA3680 220MHz 150mA 800V/jis 25ns/100ns OPA3680 OPA3680) Burr Brown part marking KT354 OPA2680 OPA2681 OPA2682 OPA3681 OPA368Q OPA681 OPA682
2003 - OPA681

Abstract: OPA682 OPA2680 OPA2681 OPA2682 OPA3680 OPA3681 OPA3682 OPA680
Text: /3 OPA3680 C 330pF Buffered Analog Delay Line ( 100ns ) International Airport Industrial Park , DELAY LINE The diagram on the front page of this data sheet shows an analog delay line using the OPA3680. The first op amp buffers the delay line from the source, and can be used to establish the DC , circuit on the front page gives a delay of 50ns per stage for a total delay of 100ns . Excellent pulse , ) FIGURE 3. Analog Delay Line 's Pulse Response. ® OPA3680 249 VOUT V2 Shorter delays may be


Original
PDF OPA3680 220MHz 150mA 25ns/100ns OPA681 OPA682 OPA2680 OPA2681 OPA2682 OPA3680 OPA3681 OPA3682 OPA680
2000 - delay line 100ns

Abstract: OPA2680 OPA2681 OPA2682 OPA3680 OPA3681 OPA3682 OPA680 OPA681 OPA682
Text: /3 OPA3680 C 330pF Buffered Analog Delay Line ( 100ns ) International Airport Industrial Park , DELAY LINE The diagram on the front page of this data sheet shows an analog delay line using the OPA3680. The first op amp buffers the delay line from the source, and can be used to establish the DC , circuit on the front page gives a delay of 50ns per stage for a total delay of 100ns . Excellent pulse , ) FIGURE 3. Analog Delay Line 's Pulse Response. ® OPA3680 249 VOUT V2 Shorter delays may be


Original
PDF OPA3680 220MHz 150mA 25ns/100ns delay line 100ns OPA2680 OPA2681 OPA2682 OPA3680 OPA3681 OPA3682 OPA680 OPA681 OPA682
2000 - Not Available

Abstract: No abstract text available
Text: R 75.0Ω 49.9Ω 1/3 OPA3680 C 330pF Buffered Analog Delay Line ( 100ns , DELAY LINE The diagram on the front page of this data sheet shows an analog delay line using the OPA3680. The first op amp buffers the delay line from the source, and can be used to establish the DC , (2τ). The circuit on the front page gives a delay of 50ns per stage for a total delay of 100ns , /µs LOW SUPPLY CURRENT: 6.4mA/ch LOW DISABLED CURRENT: 300µA/ch ENABLE/DISABLE TIME: 25ns/ 100ns


Original
PDF OPA3680 220MHz 150mA 800V/Â 25ns/100ns OPA3680
1999 - 1K-250-250

Abstract: No abstract text available
Text: OPA3682 1pF 249 VOUT Buffered Analog Delay Line ( 100ns ) International Airport Industrial Park · , : 300µA/ch ENABLE/DISABLE TIME: 25ns/ 100ns APPLICA TIONS q q q q q q q VIDEO LINE DRIVING xDSL LINE , LINE The diagram on the front page of this data sheet shows an analog delay line using the OPA3680. The first op amp buffers the delay line from the source, and can be used to establish the DC operating point , ). The circuit on the front page gives a delay of 50ns per stage for a total delay of 100ns


Original
PDF OPA3680 220MHz 150mA 25ns/100ns OPA3680 OPA3680) 1K-250-250
delay line 100ns

Abstract: OPA2680 OPA2681 OPA2682 OPA3680 OPA3681 OPA3682 OPA680 OPA681 OPA682
Text: /3 OPA3680 C 330pF Buffered Analog Delay Line ( 100ns ) International Airport Industrial Park , DELAY LINE The diagram on the front page of this data sheet shows an analog delay line using the OPA3680. The first op amp buffers the delay line from the source, and can be used to establish the DC , circuit on the front page gives a delay of 50ns per stage for a total delay of 100ns . Excellent pulse , ) FIGURE 3. Analog Delay Line 's Pulse Response. ® OPA3680 249 VOUT V2 Shorter delays may be


Original
PDF OPA3680 220MHz 150mA 25ns/100ns OPA3680) delay line 100ns OPA2680 OPA2681 OPA2682 OPA3680 OPA3681 OPA3682 OPA680 OPA681 OPA682
2012 - Not Available

Abstract: No abstract text available
Text: concern: Re: PCN for EOL of DL1L5*K delay line series. All DL1L5*K parts, except those in current , manufacturing of its DL1L5*K delay line series. These products are not planning to be replaced by a new part number. The delay line families affected by this change include the products starting with the following , DL02M520.00 Rev E-Page 2 of 3 Product Family: Part Number Series: 4-pin Through Hole Delay Line , : Single-ended (1 delay element) Time delays of 0.1ns to 10.0ns Tolerances as tight as ±0.05ns 50 impedance High


Original
PDF DL02M520 DL1L53K DL1L54K DL1L55K
2000 - UC3843A

Abstract: uc3843an UC3842AN UC3842A UC3843AD uc3842a application UC3842A application note uc3842an smps smps design notes uc3843a applications
Text: With Hysteresis Short Shutdown Delay Time: typ. 100ns High Current Totem-pole Output Output Swing , short shutdown delay time typ. 100ns . The UC3842A has UVLO threshold of 16V(on) and 10V(off). The , up current below 0.3mA and short buy products shutdown delay time typ. 100ns . The technical support , Cycle by Cycle Current Limiting Under Voltage Lock Out With Hysteresis Short Shutdown Delay Time: typ. 100ns , up current below 0.3mA and short buy products shutdown delay time typ. 100ns . The technical support


Original
PDF UC3842A/UC3843A 500KHz 100ns UC3842A/UC3843A UC3842A/ UC3843A 100ns. uc3843an UC3842AN UC3842A UC3843AD uc3842a application UC3842A application note uc3842an smps smps design notes uc3843a applications
Not Available

Abstract: No abstract text available
Text: of DL1L5*K delay line series. All DL1L5*K parts, except those in current inventory , will no longer , delay line series. These products are not planning to be replaced by a new part number. The delay line , versions. RoHS version utilizes exemption 7a. ï‚·ï€ ï‚·ï€ Single-ended (1 delay element) Time delays of 0.1ns to 10.0ns Tolerances as tight as ±0.05ns 50 impedance High volume production suitable for commercial and special applications Description: These 4-pin delay lines offer excellent


Original
PDF DL02M520
2010 - Not Available

Abstract: No abstract text available
Text: Delay Line Components. We may be able to support your last time buy needs, but we would need all orders , 3-Pin, SIP style delay line part numbers that begin with the following characters. DS , .00 Rev H - Page 1 of 2 Product Family: 3-pin Through Hole Delay Line Part Number Series: DS-S , delay element) Time delays of 0.1ns to 10.0ns Tolerances as tight as ±0.05ns 50Ω impedance High , Page 1 of 1 Product Change Notification - EOL of DS* Series, 3-Pin Delay Lines PCN Number


Original
PDF 31-Mar-2014 31-Mar-2014 31-Dec-2014. 125ns DS1L5DJ010S
2010 - marking a00

Abstract: MARKING G 3pin
Text: exemption 7a. Features: Single-ended (1 delay element) Time delays of 0.1ns to 10.0ns Tolerances as , . 250=2.50ns) (A00= 10.0ns ) Delay Type RoHS Indicator DS 1L = 1 5 = 50 DJ = 0.250" VJ = 0.362 , DS02M530.00 Rev G - Page 1 of 2 Product Family: Part Number Series: 3-pin Through Hole Delay Line DS-S Series Construction: High Purity Alumina or Zirconium Substrate Micro-Strip construction , Description: These 3-pin delay lines offer excellent performance and small size. The micro-strip construction


Original
PDF DS02M530 125ns DS1L5DJ010S marking a00 MARKING G 3pin
2010 - marking A00

Abstract: MARKING CODE A00 DS02M530 A00 marking delay line 100ns DS1L5VJA00S DJ marking
Text: DS02M530.00 Rev H - Page 1 of 2 Product Family: 3-pin Through Hole Delay Line Part Number , non-RoHS versions. RoHS version utilizes exemption 7a. Single-ended (1 delay element) Time delays of 0.1ns to 10.0ns Tolerances as tight as ±0.05ns 50 impedance High volume production suitable for commercial and special applications Description: These 3-pin delay lines offer excellent performance and , deskew applications. The performance of these equally distributed capacitance delay lines is


Original
PDF DS02M530 125ns DS1L5DJ010S marking A00 MARKING CODE A00 A00 marking delay line 100ns DS1L5VJA00S DJ marking
Not Available

Abstract: No abstract text available
Text: 5DallasSILICON DELAY LINE ? TAP FEATURES DS1005 14-Pin DIP DS1005M 8-Pin DIP DS1005S 16-Pin SOIC PIN , DS1005 Delay Line Product Family pro­ vides five equally spaced TAPS with delays ranging from 10 ns to , , compatible with ex­ isting delay line products. A space saving 8 pin -DIP is also available. The 14 pin , achieved when compared to older methods using hybrid technology. The DS1005 Delay Line reproduces the , DIAGRAM- SILICON DELAY LINE Figure 2 TERMINOLOGY Period The time elapsed between the leading edge of


OCR Scan
PDF T-47-13 DS1005 14-Pin DS1005M DS1005S 16-Pin DS1005S
74LS

Abstract: DS1005 DS1005-100 DS1005-125 DS1005-150 DS1005-75 DS1005M DS1005S delay line 400ns
Text: 5 TAP SILICON DELAY LINE DS1005 14-Pin DIP DS1005M 8-Pin DIP DS1005S 16-Pin SOIC FEATURES • All , delay line products. A space saving 8 pin -DIP is also available. The 14 pin DIP, the 8 pin -DIP, and , technology. The DS1005 Delay Line reproduces the input logic level at each TAP after the fixed delay , DELAY LINE Figure 2 RISE - IN V. 0.6V-1 IL ■PERIOD -2.4V 2.4V-V 1'5V ' 1.5VN 0,6V 'FALL , SEMICONDUCTOR CORP CHE D | SblMlBO D0QS07T S | T-47-13 Silicon Delay Line DS1005 14-Pin DIP DIM. INCHES


OCR Scan
PDF 2bl413D T-47-13 DS1005 14-Pin DS1005M DS1005S 16-Pin 5bl4130 74LS DS1005-100 DS1005-125 DS1005-150 DS1005-75 delay line 400ns
2010 - marking A00

Abstract: No abstract text available
Text: DL02M520.00 Rev D-Page 1 of 2 Product Family: 4-pin Through Hole Delay Line Part Number , version utilizes exemption 7a. Single-ended (1 delay element) Time delays of 0.1ns to 10.0ns , applications Description: These 4-pin delay lines offer excellent performance and small size. The , performance of these equally distributed capacitance delay lines is significantly better than lumped element delay lines and the physical size is much smaller than delays obtained by using cable. Product


Original
PDF DL02M520 marking A00
2012 - Not Available

Abstract: No abstract text available
Text: . Features: Single-ended (1 delay element) Time delays of 0.1ns to 10.0ns Tolerances as tight as , . 200=2.00ns, A00= 10.0ns ) Delay Type RoHS Indicator DL 1L = 1 5 = 50 S = Single -C = RoHS , DL02M520.00 Rev E-Page 1 of 2 Product Family: Part Number Series: 4-pin Through Hole Delay Line DL1L5, 4-pin Series Construction: High Purity Alumina or Zirconium Substrate 4-pin, through , Description: These 4-pin delay lines offer excellent performance and small size. The micro-strip construction


Original
PDF DL02M520 DL1L53K DL1L54K DL1L55K
0447-0500-09

Abstract: 0447-0070 delay line 400ns DTSHW-3.8N
Text: DELAY LINE SE R IE S 0447 LOW POWER MODULE 20 MA TYP 5 TAP/FIXED DELAY TECHNICAL INFORMATION TEST CONDITIONS 3.2 Volts 3.0 Nsec (10%-90%) 1.2 X Total Delay 4 X Pulse Width Ic c l 20.0 Milliamps max. Supply , Output Voltage 0.5 Volts max. Delay Tolerance From Input To Tap + 2 Nsec or 5 % whichever is greater Delay Tolerance From Tap To Tap ± 2 Nsec or 7 % whichever is greater All specified Performance , Volts Operating Temperature Range 0°C To 70°C Temperature Coefficient Of Total Delay 500PPM/°C Typical


OCR Scan
PDF 13S14E3 D000S05 Co-08 100NS 125NS 150NS 175NS 200NS 250NS 300NS 0447-0500-09 0447-0070 delay line 400ns DTSHW-3.8N
2001 - mosfet discrete totem pole CIRCUIT

Abstract: SMPS Controller
Text: With Hysteresis Short Shutdown Delay Time: typ. 100ns High Current Totem-pole Output Output Swing Limiting: 22V Description The KA3882C/KA3883C are fixed PWM controller for Off Line and DC to DC , short shutdown delay time typ. 100ns . The KA3882C has UVLO threshold of 16V(on) and 10V(off). The , technical information current below 0.3mA and short shutdown delay time typ. 100ns . The KA3882C has UVLO buy , cycle current limiting Under voltage lock out with hysteresis Short shutdown delay time: Typ. 100ns High


Original
PDF KA3882C/KA3883C 500KHz 100ns KA3882C/KA3883C 100ns. KA38er KA3882C KA3882CD mosfet discrete totem pole CIRCUIT SMPS Controller
48LD

Abstract: IR3094MPBF IR3094MTRPBF IR3094PBF
Text: Protection with Delay to prevent false triggering Simplified Powergood provides indication of proper , Separate OVP sense line to sense the output voltage and latched OVP with protection Inductor DCR sensing , -0.3V -0.3V -0.3V -0.3V -0.3V n/a -0.3V -0.3V DC, -2V for 100ns -0.3V -0.3V DC, -2V for 100ns -0.3V -0.3V -0.3V DC, -2V for 100ns -0.3V -0.3V DC, -2V for 100ns -0.3V -0.3V -0.3V DC, -2V for 100ns -0.3V -0.3V DC, -2V for 100ns -0.3V n/a -0.3V -0.3V -0.3V -0.3V -0.3V -0.3V ISOURCE


Original
PDF IR3094PBF IR3094 100KHz 540KHz 48LD IR3094MPBF IR3094MTRPBF IR3094PBF
2000 - AN9895

Abstract: P802 55Mbps P8021
Text: performance of a 2-ray channel model with a " 100ns delay spread." However, notice that the packet error rate , COMPARISON OF A 2-RAY CHANNEL MODEL WITH DELAY SPREADS OF 100ns RMS DELAY (ns) MAXIMUM EXCESS DELAY (ns , delay of 100ns , and the bottom row has an RMS delay of 100ns . We have shown specific examples of two , identical RAKE receiver without equalizer performs dramatically differently at 100ns RMS delay spread for , nontrivial delay spread. In other words, Application Note 9895 even over a short range with a line of


Original
PDF AN9895 AN9895 P802 55Mbps P8021
delay line 400ns

Abstract: A447-0100-09 a447-0150 100NS 25NS A447 A447-0025-09 A447-0050-09 A447-0150-09 050009
Text: bei/ defining a degree of excellence DIGITAL DELAY LINE SERIES A447 LOW POWER MODULE 20 MA TYP 5 TAP/FIXED DELAY TECHNICAL INFORMATION TEST CONDITIONS Pulse Vbltage Rise Time Pulse Width Pulse Period , x Total Delay 4 x Pulse Width 20.0 Milliamps typical 5.0 Volts PERFORMANCE CHARACTERISTICS Delay Tolerance From Input To Tap + 2 Nsec or 5% whichever is greater Delay Tolerance From Tap To Tap ± 2 Nsec or , 0.5'\folts max. Operating Temperature Range 0°C To 70°C Temperature Coefficient Of Total Delay


OCR Scan
PDF /o-90Â A447-0125-08 125NS A447-0020-08 A447-0150-08 150NS A447-0030-08 A447-0175-08 175NS A447-0040-08 delay line 400ns A447-0100-09 a447-0150 100NS 25NS A447 A447-0025-09 A447-0050-09 A447-0150-09 050009
2001 - SMPS CIRCUIT DIAGRAM 12v 5v

Abstract: No abstract text available
Text: With Hysteresis Short Shutdown Delay Time: typ. 100ns High Current Totem-pole Output Output Swing Limiting: 22V Description The KA3882C/KA3883C are fixed PWM controller for Off Line and DC to DC , short shutdown delay time typ. 100ns . The KA3882C has UVLO threshold of 16V(on) and 10V(off). The , current below 0.3mA and short shutdown delay time typ. 100ns . The KA3882C has UVLO buy products threshold , current limiting Under voltage lock out with hysteresis Short shutdown delay time: Typ. 100ns High current


Original
PDF KA3882C/KA3883C 500KHz 100ns KA3882C/KA3883C 100ns. KA38q KA3883C SMPS CIRCUIT DIAGRAM 12v 5v
2001 - KA3843A

Abstract: ka3843a 5v power supply smps power circuit using ka3882c KA3843ACS
Text: With Hysteresis Short Shutdown Delay Time: typ. 100ns High Current Totem-pole Output Output Swing Limiting: 22V Description The KA3882C/KA3883C are fixed PWM controller for Off Line and DC to DC , short shutdown delay time typ. 100ns . The KA3882C has UVLO threshold of 16V(on) and 10V(off). The , current below 0.3mA and short shutdown delay time typ. 100ns . The KA3882C has UVLO buy products threshold , current limiting Under voltage lock out with hysteresis Short shutdown delay time: Typ. 100ns High current


Original
PDF KA3882C/KA3883C 500KHz 100ns KA3882C/KA3883C 100ns. KA38q KA3843A ka3843a 5v power supply smps power circuit using ka3882c KA3843ACS
2000 - Not Available

Abstract: No abstract text available
Text: short shutdown delay time typ. 100ns . The KA3882E has UVLO threshold of 16V(on) and 10V(off). The , Lock Out With Hysteresis Short Shutdown Delay Time: typ. 100ns High Current Totem-pole Output Output , shutdown delay time typ. 100ns . The KA3882E has UVLO threshold of buy products 16V(on) and 10V&#"40;off , Lock Out With Hysteresis Short Shutdown Delay Time: typ. 100ns High Current Totem-pole Output Output , 25°C, IO = 1mA 4.9 5.0 5.1 V Line Regulation RLine VCC = 12V to 25V - 6


Original
PDF KA3882E/KA3883E KA3882E/KA3883E KA3882E/ KA3883E 100ns. KA3882E 100ns
2001 - ka3842a application note

Abstract: circuit ka3842a smps design notes ka3842a KA3842A cross reference ka3842a 84V SMPS
Text: With Hysteresis Short Shutdown Delay Time: typ. 100ns High Current Totem-pole Output Output Swing Limiting: 22V Description The KA3882C/KA3883C are fixed PWM controller for Off Line and DC to DC , short shutdown delay time typ. 100ns . The KA3882C has UVLO threshold of 16V(on) and 10V(off). The , current below 0.3mA and short shutdown delay time typ. 100ns . The KA3882C has UVLO buy products threshold , current limiting Under voltage lock out with hysteresis Short shutdown delay time: Typ. 100ns High current


Original
PDF KA3882C/KA3883C 500KHz 100ns KA3882C/KA3883C 100ns. KA3842A KA3842ACDS ka3842a application note circuit ka3842a smps design notes ka3842a cross reference ka3842a 84V SMPS
Supplyframe Tracking Pixel