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LTC1609ACSW#TR Linear Technology IC ADC SRL 16BIT 200KSPS 20-SOIC
LTC1609AISW#TR Linear Technology IC ADC SRL 16BIT 200KSPS 20-SOIC

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2007 - MPC8321

Abstract: MPC8323e MPC8321E 516-PBGA MPC8321 software MPC8323 DDR1 termination Engine Control Unit diagram multi protocol serial controller
Text: -bit DDR1/ DDR2 16-bit ; up to 66 MHz 32-bit; up to 66 MHz (3) 10/100; MII/RMII Full/low speed Yes Yes , No 266/333 Single RISC 32-bit DDR1/ DDR2 16-bit ; up to 66 MHz 32-bit; up to 66 MHz (3) 10/100 , 16/16 No 266/333 Single RISC 32-bit DDR1/ DDR2 16-bit ; up to 66 MHz 32-bit; up to 66 MHz (3) 10 , MPC8321E e300 16/16 No 266/333 Single RISC 32-bit DDR1/ DDR2 16-bit ; up to 66 MHz 32-bit; up to 66 , -bit double data rate (DDR1/ DDR2 ) Engine subsystem communications engine · Time division multiplexing


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PDF MPC8323E MPC8323E, MPC8323, MPC8321E MPC8321 32-bit MPC8323EPQIIFS MPC8321E 516-PBGA MPC8321 software MPC8323 DDR1 termination Engine Control Unit diagram multi protocol serial controller
2010 - ipic

Abstract: MPC830x MPC8308 Linux ddr2 16bit PowerQUICC WLAN Module MII QUICC Engine MPC8309-KIT eInfochips
Text: -bit DDR2 with ECC 16/32-bit DDR2 with ECC 16-bit DDR2 16-bit DDR2 Local Bus 8/ 16-bit up to 66 MHz 8/ 16-bit up to 66 MHz 8/ 16-bit up to 66 MHz 8/ 16-bit up to 66 MHz PCI Interface , DDR Memory 16-bit DDR2 up to 266/333 MHz (1 Gigabit) 32-bit (w/ECC) DDR2 at 266/333 MHz (2 Gigabit) 16/32-bit DDR/2 up to 266/333 MHz with and without ECC Local Bus 16-bit w/NAND/NOR, I2C boot support (Muxed addr/data bus) 16-bit w/NAND/NOR, I2C boot support 16-bit w/NAND boot


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PDF MPC830x MPC830x-KIT) MPC8306, MPC8308 MPC8309) MPC830x-KIT RJ-45 ipic Linux ddr2 16bit PowerQUICC WLAN Module MII QUICC Engine MPC8309-KIT eInfochips
2010 - E300 programming cable

Abstract: 128 MB DDR2 SDRAM 16-pin JTAG CONNECTOR 6-pin JTAG header "Header, 4-Pin db9 JTAG CONNECTOR 1588 RS232 6 Pin RJ11 Board Jack LTIB rs232 mini project on risc architecture
Text: 32-bit RISC Memory Controller 16/32-bit DDR2 with ECC 16-bit DDR2 16-bit DDR2 Local Bus 8/ 16-bit up to 66 MHz 8/ 16-bit up to 66 MHz 8/ 16-bit up to 66 MHz PCI Interface 32 , connector 16-pin SPI and IEEE 1588 header 16-pin GPIO header 128 MB DDR2 SDRAM 8 MB NOR flash memory 512 MB NAND flash memory 256 KB serial EEPROM 256 MB DDR2 SDRAM 8 MB NOR flash memory 512 MB


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PDF MPC830x MPC830x-KIT) MPC8306/S MPC8309 RS232 MPC830x-KIT Conn70 MPC830XSOMFS E300 programming cable 128 MB DDR2 SDRAM 16-pin JTAG CONNECTOR 6-pin JTAG header "Header, 4-Pin db9 JTAG CONNECTOR 1588 RS232 6 Pin RJ11 Board Jack LTIB rs232 mini project on risc architecture
2010 - mii to hdlc

Abstract: MPC8306S MPC8309 MPC8308 MPC8306 MPC830x power adapter 12v/5a pin Profibus USB RGMI
Text: the ultra low-end MPC830x and a 16-bit DDR2 memory controller running a highly integrated, fully , 16-bit double data rate ( DDR2 ) more efficient operations to be conducted memory controller, 4 x , -bit RISC 32-bit RISC 32-bit RISC Memory Controller 16/32-bit DDR2 16/32-bit DDR2 16-bit DDR2 with ECC with ECC 16-bit DDR2 Local Bus 8/ 16-bit up to 66 MHz 8/ 16-bit up to 66 MHz 8 , SDHC controller, a 16-bit local bus and two direct memory access (DMA) channels. performance


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PDF MPC8306 MPC8306S MPC8306S MPC830x 16-bit MPC8606FSA4 mii to hdlc MPC8309 MPC8308 MPC830x power adapter 12v/5a pin Profibus USB RGMI
2010 - Not Available

Abstract: No abstract text available
Text: Features also include a 16-bit double data rate ( DDR2 ) Core Complex • High-performance , , resulting in a significant performance improvement e300 Core Complex 16 KB D-Cache 16-bit DDR2 , GPIO Interrupt Controller standards • DDR2 memory controller—one 16-bit interface up to 266 , 16-bit DDR2 16-bit DDR2 Local Bus 8/ 16-bit up to 66 MHz 8/ 16-bit up to 66 MHz 8/ 16-bit , Overview Power Architecture® technology, which includes USB 2.0 controller, a 16-bit local bus and


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PDF MPC8306 MPC8306S 16-bit MPC8306S MPC830x 473-pin 489-pin 369-pin
2010 - Not Available

Abstract: No abstract text available
Text: -bit RISC 32-bit RISC Memory Controller 16/32-bit DDR2 with ECC 16/32-bit DDR2 with ECC 16-bit DDR2 16-bit DDR2 Local Bus 8/ 16-bit up to 66 MHz 8/ 16-bit up to 66 MHz 8/ 16-bit up to 66 MHz , applications, 16/32-bit DDR2 Controller including I/O cards for low-end base stations, 16 KB D-Cache , , SPI GPIO, Interrupt Controller Or 16-bit GPIO time to market advantage through cost-effective , data rate ( DDR2 ) memory controller Core Accelerators I/O with ECC support, 4 x CAN, 4 x


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PDF MPC8309 MPC830x 16/32-bit 473-pin 489-pin 369-pin
2010 - MPC8309

Abstract: MPC8309-KIT MPC830x MPC8308 mii to hdlc MPC8306 ipic power adapter 12v/5a pin PowerQUICC MPC8306S
Text: Controller 16/32-bit DDR2 with ECC 16/32-bit DDR2 with ECC 16-bit DDR2 16-bit DDR2 Local Bus 8/ 16-bit , applications, 16/32-bit DDR2 Controller including I/O cards for low-end base stations, 16 KB D-Cache , 2 x DUART 12C, SPI GPIO, Interrupt Controller Or 16-bit GPIO through cost-effective , data rate ( DDR2 ) memory controller Core Accelerators I/O with ECC support, 4 x CAN, 4 x , , low-power and cost- controller, a 32-bit peripheral component interconnect (PCI) controller, a 16-bit


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PDF MPC8309 MPC830x 16/32-bit 473-pin 489-pin 369-pin MPC8309-KIT MPC8308 mii to hdlc MPC8306 ipic power adapter 12v/5a pin PowerQUICC MPC8306S
2010 - mii to hdlc

Abstract: SDHC protocol MPC8308 RGMI MPC830x-KIT power adapter 12v/5a pin MPC830x MPC8309 Profibus UART MPC8306S
Text: evaluation · High-performance, low-power and cost- also include a 16-bit double data rate ( DDR2 , future- e300 Core Complex 16 KB D-Cache 16-bit DDR2 Controller 16 KB I-Cache Up to 2 x , termination to meet evolving protocol standards · DDR2 memory controller-one 16-bit 2x DMA 2 x DUART , 32-bit RISC Memory Controller 16/32-bit DDR2 with ECC 16/32-bit DDR2 with ECC 16-bit DDR2 16-bit DDR2 Local Bus 8/ 16-bit up to 66 MHz 8/ 16-bit up to 66 MHz 8/ 16-bit up to


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PDF MPC8306 MPC8306S 16-bit MPC8306S MPC830x MPC8306FS mii to hdlc SDHC protocol MPC8308 RGMI MPC830x-KIT power adapter 12v/5a pin MPC830x MPC8309 Profibus UART
2008 - 1134 scr

Abstract: 8b 10b m-phy cpu 1558 ddr2 ram MPPS 472 8-2464 TMS320TCI6486 A62221-2 scr connections sdram memory module 1993
Text: bi-directional. · A 32-bit DDR2 -533 SDRAM interface with up to 2133 Mbps of throughput. · A 16-bit multiplexed , memory interface. For a 16-bit DDR2 memory interface with a 533.3-MHz DDR2 data rate, the theoretical , to 32-Bit DDR2 786 786 1503 1504 2133 36.9 36.9 70.5 70.5 16-Bit DDR2 to 16-Bit DDR2 321 321 459 459 1066 30.1 30.1 43 43 16-Bit DDR2 to , to 16-Bit DDR2 708 708 1032 1033 1066 66.4 66.4 96.8 96.8 16-Bit DDR2


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PDF TMS320C6472/TMS320TCI6486 C6472/TCI6486 608KB 768KB 32-bit 533-MHz 512MB 1134 scr 8b 10b m-phy cpu 1558 ddr2 ram MPPS 472 8-2464 TMS320TCI6486 A62221-2 scr connections sdram memory module 1993
2008 - STB6110

Abstract: STi5211 jtag sti5211 dvb-s2 card st231 STI5202 DVB-S2 integrated receiver demodulator diseqc H.264 video over ip SMARTCARD directv
Text: with standard definition (SD) component and composite output Unified DDR2 16-bit interface operating , clocks CPU FDMA ST40-4/300 (x2) PTI DDR-2 SDRAM Memory VDP aux Transport/SEC , WiFi. Figure 1. STi5211 applications 2 x 128 MB DDR2 -333 MHz 16 IR Rx UHF Rx 27


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PDF STi5211 ST40-300 ST231 16-bit 333MHz STB6110 STi5211 jtag sti5211 dvb-s2 card STI5202 DVB-S2 integrated receiver demodulator diseqc H.264 video over ip SMARTCARD directv
2009 - Implementation of DDR2 on AT91SAM9G45 Devices

Abstract: MT47H64M8CF-3 MT47H64M8CF AT91SAM9 DDR2 AT91SAM9g45-EKes ddram AT91SAM9G45-EK at91sam9g45 SAM9G45-EKES DDR2 sdram pcb layout guidelines
Text: : · One multi-port DDR2 controller that supports 16-bit DDR2 or 16-bit LP-DDR memories only · One single-port DDR2 controller that supports 16-bit DDR2 , 16-bit LP-DDR, 16- or 32-bit SDR or LP-SDR memories , (DDR2C) extends the memory capabilities of a chip by providing the interface to an external 16-bit DDR2 , supports byte (8-bit) and half-word ( 16-bit ) accesses. The DDR2 controller supports a read or write burst , by providing the interface to 16-bit DDR2 , 16-bit LP-DDR, 16-bit or 32-bit SDR or LD-SDR external


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PDF AT91SAM9G45 AT91SAM9G45 16-bit 32-bit 22-Sep-09 16-bit Implementation of DDR2 on AT91SAM9G45 Devices MT47H64M8CF-3 MT47H64M8CF AT91SAM9 DDR2 AT91SAM9g45-EKes ddram AT91SAM9G45-EK SAM9G45-EKES DDR2 sdram pcb layout guidelines
2009 - C6748 EDMA

Abstract: OMAP-L138 setup USB interrupts of arm9 edma3 c6748 TMDXOSKL138BET UART Program Examples ARM 32-KBL1D arm sata nand control OMAP-L138 arm9 c674x floating point dsp C6748
Text: / DDR2 16-bit Async EMIF 16-bit MMC/SD (2) Bluetooth Connectivity Pricing: $18.60 @ 1Ku , Floating-Point DSP OMAP-L11x ­ ARM + Co-Processor OMAP-L10x ­ ARM only mDDR/ DDR2 , McASP/McBSP, SATA,UPP , engine and iDMA engine Smaller code size 16-bit compact instructions SPLOOP buffer 100% upward object code compatible w/C6000 fixed & floating C64x+ C64x SPLOOP and 16bit instructions for , memories Advanced fixedpoint instructions Four 16-bit or eight 8-bit MACs Two-level cache FIXED


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PDF C6000 DM644x DM646x OMAP35x C5000 C67x/C64x C674x C2000 MSP430 C6748 EDMA OMAP-L138 setup USB interrupts of arm9 edma3 c6748 TMDXOSKL138BET UART Program Examples ARM 32-KBL1D arm sata nand control OMAP-L138 arm9 c674x floating point dsp C6748
2007 - JESD79-2c

Abstract: P6860 DDR2 Considerations for Designing DDR2 layout guidelines SODIMM ddr2 MCF54455 MT47H64M8 P6880
Text: bus that is four times wider than the external bus. For example, a 16-bit wide DDR2 memory uses a 64 , -bit fetch and loads it into four 16-bit prefetch buffers. During the DDR2 burst cycle these four registers , internal bus. The DDR/ DDR2 /mobile-DDR controller supports converting these 32-bit transactions into 16-bit , chip selects, and a 16-bit wide bus. Table 1. DDR2 Feature Implementation Guide DDR2 Feature/Option , . Correct burst sequence support for burst of 8. Critical word first support included. 144-pin DDR2 16-bit


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PDF AN3522 MCF5445x JESD79-2c P6860 DDR2 Considerations for Designing DDR2 layout guidelines SODIMM ddr2 MCF54455 MT47H64M8 P6880
2009 - mpc8314

Abstract: PSC9131RDB T4240 BSC9130 JESD-207 P3041ds P1022DS PPCEVAL-CDS-8548 P2020AMC-SA MPC8572DS
Text: 2.0 2.0 2.0 2.0 Full/ Low 2.0 2.0 2 x 2.0 2.0 Full/ Low 2.0 Full/ Low 2 x 2.0 2.0 2.0 DDR1/2 Memory 16-bit DDR2 16-bit DDR2 16/32-bit DDR2 16/32-bit DDR2 16/32-bit 16/32-bit 16/32-bit 32-bit 32-bit 32/64-bit 32 , Full/Low 3 x 2.0 Full/Low 1.1 Full/Low 2.0 Full/Low Memory DDR1/2 DDR2 /3 DDR2 /3 DDR1 DDR1 DDR1/2 DDR1/2 DDR1/2 DDR1/2 DDR1/2 DDR1 DDR1 DDR1/2 DDR1/2 DDR2 /3 DDR2 /3 Constant Features · I/D cache memory: 32 , Hardware PCIe 2 2 2 2 2 2 2 2 2 2 3 3 3 3 3 3 3 3 4 3 3 4 4 USB sRIO GPIO DDR2 /3 Memory 1 1 2 2 2 2 1 1 1 1


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PDF MPC870 MPC875 MPC880 MPC885 256-pin 357-pin MPC85x MPC86x, mpc8314 PSC9131RDB T4240 BSC9130 JESD-207 P3041ds P1022DS PPCEVAL-CDS-8548 P2020AMC-SA MPC8572DS
2007 - block diagram of wifi enabled robo

Abstract: ADSL2 DSLAM chipset powerline ethernet adapter schematic diagram VSC7385 GL850A EEMB ADSL2 Modem circuit diagram mpc dhrystone GL850 MPC8313E-rdb
Text: connectivity to · Dual integrated DDR2 /DDR3 Based on Freescale's 90 nm silicon-on-insulator network , increase and represent the next double data rate ( DDR2 /DDR3) memory step in continuous innovation , full ECC support, supporting: 333 MHz clock rate (667 MHz data rate), 64-bit, 1.8V SSTL, DDR2 , Acceleration Coherency Module 64-bit DDR/ DDR2 SDRAM Controller Perf Mon DUART 2 x I2C Timers , High internal processing bandwidth The MPC8568E family consists of the · Integrated DDR/ DDR2


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PDF MPC8572E MPC8568E MPC8560E MPC8555E MPC8548E MPC8541E MPC8540 MPC8360E MPC8349E MPC8323E block diagram of wifi enabled robo ADSL2 DSLAM chipset powerline ethernet adapter schematic diagram VSC7385 GL850A EEMB ADSL2 Modem circuit diagram mpc dhrystone GL850 MPC8313E-rdb
2009 - Not Available

Abstract: No abstract text available
Text: SDRAM with 128-MB Address Space ­ DDR2 /Mobile DDR Memory Controller with one of the following: · 16-Bit DDR2 SDRAM with 256-MB Address Space · 16-Bit mDDR SDRAM with 256-MB Address Space One Configurable , " 16-Bit DDR2 SDRAM With 512 MB Address Space" bullet to " 16-Bit DDR2 SDRAM With 256 MB Address Space , C6742 DDR2 , 16-bit bus width, up to 156 MHz Mobile DDR, 16-bit bus width, up to 150 MHz Asynchronous (8 , Clocks · Fixed-Point Multiply Supports Two 32 x 32-Bit Multiplies, Four 16 x 16-Bit Multiplies, or Eight


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PDF TMS320C6742 SPRS587D TMS320C6742TM TMS320C6742 32-Bit 16-Bit
2009 - Not Available

Abstract: No abstract text available
Text: €¢ NAND (8- or 16-Bit-Wide Data) • 16-Bit SDRAM with 128-MB Address Space – DDR2 /Mobile DDR Memory Controller with one of the following: • 16-Bit DDR2 SDRAM with 256-MB Address Space • 16-Bit mDDR , header title from Timing Requirement tables. Section 1.1 Features Updated/Changed the " 16-Bit DDR2 SDRAM With 512 MB Address Space" bullet to " 16-Bit DDR2 SDRAM With 256 MB Address Space" Deleted , FEATURES DDR2 /mDDR Memory Controller C6742 DDR2 , 16-bit bus width, up to 156 MHz Mobile DDR, 16-bit


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PDF TMS320C6742 SPRS587D TMS320C6742â TMS320C6742 200-MHz C674xâ C674x 64-Bit 16-Bit
2009 - 40E-4

Abstract: No abstract text available
Text: Library 1.8V or 3.3V LVCMOS IOs (except DDR2 interfaces) Two External Memory Interfaces: ­ EMIFA · NOR (8-/16-Bit-Wide Data) · NAND (8-/16-Bit-Wide Data) · 16-Bit SDRAM With 128 MB Address Space ­ DDR2 /Mobile DDR Memory Controller · 16-Bit DDR2 SDRAM With 512 MB Address Space or · 16-Bit mDDR SDRAM With 256 MB , UHPI General-Purpose Input/Output Port C6742 DDR2 , 16-bit bus width, up to 156 MHz Mobile DDR, 16-bit , Point Multiply Supports Two 32 x 32-Bit Multiplies, Four 16 x 16-Bit Multiplies, or Eight 8 x 8


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PDF TMS320C6742 SPRS587C TMS320C6742 32-Bit 16-Bit 40E-4
2009 - 0X0075

Abstract: ic 7804
Text: Library 1.8V or 3.3V LVCMOS IOs (except DDR2 interfaces) Two External Memory Interfaces: ­ EMIFA · NOR (8-/16-Bit-Wide Data) · NAND (8-/16-Bit-Wide Data) · 16-Bit SDRAM With 128 MB Address Space ­ DDR2 /Mobile DDR Memory Controller · 16-Bit DDR2 SDRAM With 512 MB Address Space or · 16-Bit mDDR SDRAM With 256 MB , Port [McBSP] eHRPWM eCAP UHPI General-Purpose Input/Output Port 2 C6742 DDR2 , 16-bit bus width, up , Point Multiply Supports Two 32 x 32-Bit Multiplies, Four 16 x 16-Bit Multiplies, or Eight 8 x 8


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PDF TMS320C6742 SPRS587C TMS320C6742 32-Bit 16-Bit 0X0075 ic 7804
2009 - Not Available

Abstract: No abstract text available
Text: Library 1.8V or 3.3V LVCMOS IOs (except DDR2 interfaces) Two External Memory Interfaces: ­ EMIFA · NOR (8-/16-Bit-Wide Data) · NAND (8-/16-Bit-Wide Data) · 16-Bit SDRAM With 128 MB Address Space ­ DDR2 /Mobile DDR Memory Controller · 16-Bit DDR2 SDRAM With 512 MB Address Space or · 16-Bit mDDR SDRAM With 256 MB , Port [McBSP] eHRPWM eCAP UHPI General-Purpose Input/Output Port 2 C6742 DDR2 , 16-bit bus width, up , Point Multiply Supports Two 32 x 32-Bit Multiplies, Four 16 x 16-Bit Multiplies, or Eight 8 x 8


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PDF TMS320C6742 SPRS587C TMS320C6742 32-Bit 16-Bit
2009 - SRAM 10ns

Abstract: 0x6400
Text: Library 1.8V or 3.3V LVCMOS IOs (except DDR2 interfaces) Two External Memory Interfaces: ­ EMIFA · NOR (8-/16-Bit-Wide Data) · NAND (8-/16-Bit-Wide Data) · 16-Bit SDRAM With 128 MB Address Space ­ DDR2 /Mobile DDR Memory Controller · 16-Bit DDR2 SDRAM With 512 MB Address Space or · 16-Bit mDDR SDRAM With 256 MB , Port [McBSP] eHRPWM eCAP UHPI General-Purpose Input/Output Port Size (Bytes) 2 C6742 DDR2 , 16-bit , Point Multiply Supports Two 32 x 32-Bit Multiplies, Four 16 x 16-Bit Multiplies, or Eight 8 x 8


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PDF TMS320C6742 SPRS587B TMS320C6742 32-Bit 16-Bit SRAM 10ns 0x6400
2009 - spi bios programmer top 838c

Abstract: CP/2014
Text: -MB Address Space – DDR2 /Mobile DDR Memory Controller with one of the following: • 16-Bit DDR2 SDRAM , DDR2 /mDDR Memory Controller C6742 DDR2 , 16-bit bus width, up to 156 MHz Mobile DDR, 16-bit bus , €“ Compact 16-Bit Instructions • C674x Two-Level Cache Memory Architecture – 32KB of L1P Program RAM , Multiplies, Four 16 x 16-Bit Multiplies, or Eight 8 x 8-Bit Multiplies per Clock Cycle, and Complex , Library 1.8-V or 3.3-V LVCMOS I/Os (Except for DDR2 Interfaces) Two External Memory Interfaces: â


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PDF TMS320C6742 SPRS587E TMS320C6742â TMS320C6742 200-MHz C674x 64-Bit 16-Bit spi bios programmer top 838c CP/2014
2009 - Not Available

Abstract: No abstract text available
Text: – DDR2 /Mobile DDR Memory Controller • 16-Bit DDR2 SDRAM With 512 MB Address Space or • 16-Bit , C6742 DDR2 , 16-bit bus width, up to 156 MHz Mobile DDR, 16-bit bus width, up to 150 MHz DDR2 /mDDR , Direct-Memory-Access Controller (EDMA3) – DDR2 /Mobile DDR Memory Controller – One Configurable UART Modules â , , Bit-Counting – Compact 16-Bit Instructions • C674x Two Level Cache Memory Architecture – 32K-Byte L1P , -Bit Multiplies, Four 16 x 16-Bit Multiplies, or Eight 8 x 8-Bit Multiplies per Clock Cycle, and Complex


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PDF TMS320C6742 SPRS587C TMS320C6742 200-MHz C674x C674xâ
2009 - Not Available

Abstract: No abstract text available
Text: Library 1.8V or 3.3V LVCMOS IOs (except DDR2 interfaces) Two External Memory Interfaces: ­ EMIFA · NOR (8-/16-Bit-Wide Data) · NAND (8-/16-Bit-Wide Data) · 16-Bit SDRAM With 128 MB Address Space ­ DDR2 /Mobile DDR Memory Controller · 16-Bit DDR2 SDRAM With 512 MB Address Space or · 16-Bit mDDR SDRAM With 256 MB , UHPI General-Purpose Input/Output Port Size (Bytes) 2 C6742 DDR2 , 16-bit bus width, up to 156 MHz , Point Multiply Supports Two 32 x 32-Bit Multiplies, Four 16 x 16-Bit Multiplies, or Eight 8 x 8


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PDF TMS320C6742 SPRS587B TMS320C6742 32-Bit 16-Bit
2009 - LD E 5027

Abstract: soc 1600
Text: Library 1.8V or 3.3V LVCMOS IOs (except DDR2 interfaces) Two External Memory Interfaces: ­ EMIFA · NOR (8-/16-Bit-Wide Data) · NAND (8-/16-Bit-Wide Data) · 16-Bit SDRAM With 128 MB Address Space ­ DDR2 /Mobile DDR Memory Controller · 16-Bit DDR2 SDRAM With 512 MB Address Space or · 16-Bit mDDR SDRAM With 256 MB , Port [McBSP] eHRPWM eCAP UHPI General-Purpose Input/Output Port 2 C6742 DDR2 , 16-bit bus width, up , Point Multiply Supports Two 32 x 32-Bit Multiplies, Four 16 x 16-Bit Multiplies, or Eight 8 x 8


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PDF TMS320C6742 SPRS587C TMS320C6742 32-Bit 16-Bit LD E 5027 soc 1600
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