The recommended power-up sequence is to apply VCC first, followed by AVCC, and then DVCC. This ensures that the internal voltage regulators are powered up correctly.
To configure the PCM4202DBR for master clock mode, set the MCLK pin to the desired clock frequency, and set the M/S pin to logic high. This will enable the internal clock generator and allow the PCM4202DBR to generate the master clock signal.
The maximum input signal level for the ADCs is 2.5 Vrms. Exceeding this level may result in signal clipping and distortion.
To optimize the performance of the PCM4202DBR in noisy environments, use a low-pass filter on the analog input signals, and ensure that the power supply lines are well-decoupled and filtered. Additionally, consider using a shielded enclosure and keeping the analog and digital circuits separate.
The latency of the PCM4202DBR's ADCs is approximately 1.5 clock cycles. This means that there is a delay of 1.5 clock cycles between the input signal and the corresponding digital output.
PCM4202DBR datasheet
by Texas Instruments
