The recommended power-up sequence is to power up the analog supply (VCCA) first, followed by the digital supply (VCCD), and then the clock signal. This ensures proper initialization of the device.
To minimize noise and jitter, it is recommended to keep the analog and digital signal traces separate, use a solid ground plane, and place the device close to the analog power supply. Additionally, use a low-jitter clock source and ensure that the clock signal is properly terminated.
The maximum allowed clock jitter for the PCM1792ADBG4 is 100 ps RMS. Exceeding this limit can result in decreased performance and increased distortion.
To configure the PCM1792ADBG4 for master clock mode, set the MCLK pin to the desired clock frequency, and set the BCK pin to the desired bit clock frequency. The device will then generate the LRCK signal internally.
The recommended termination for the digital output pins of the PCM1792ADBG4 is a 50-ohm resistor to ground, to ensure proper signal integrity and minimize reflections.
PCM1792ADBG4 datasheet
by Texas Instruments
