The recommended power-up sequence is to apply VCC first, followed by VDD, and then the analog power supplies (VAA and VDA). This ensures that the internal voltage regulators are powered up correctly.
To optimize the analog filter performance, ensure that the analog power supplies (VAA and VDA) are well-filtered and decoupled, and that the analog input signals are properly terminated and filtered to prevent aliasing.
The maximum clock frequency supported by the PCM1781DBQR is 256 fs (where fs is the sampling frequency). For example, at a sampling frequency of 48 kHz, the maximum clock frequency is 12.288 MHz.
To configure the PCM1781DBQR for master clock mode, set the MCLK pin as an output by setting the MCLKOE bit in the Control Register. Then, set the desired clock frequency using the MCLKDIV bits in the Control Register.
To minimize noise and ensure optimal performance, keep the analog and digital signal traces separate, use a solid ground plane, and place decoupling capacitors close to the power pins. Also, avoid running digital signal traces near the analog input pins.
PCM1781DBQR datasheet
by Texas Instruments
