The recommended power-up sequence is to apply VCC first, followed by AVCC, and then DVCC. This ensures that the internal voltage regulators are powered up correctly.
To minimize noise and ensure optimal performance, it is recommended to keep the analog and digital grounds separate, use a solid ground plane, and keep the analog and digital signal traces separate and away from each other.
The PCM1744U supports clock frequencies up to 256 fs (12.288 MHz) for 24-bit audio data.
To configure the PCM1744U for Master Clock mode, set the MCLK pin to the desired clock frequency, and set the BCK pin to the desired bit clock frequency. The LRCK pin should be set to the desired word clock frequency.
A decoupling capacitor value of 0.1 μF to 1 μF is recommended for the VCC, AVCC, and DVCC pins to filter out noise and ensure stable operation.
PCM1744U datasheet
by Texas Instruments
