The recommended power-up sequence is to apply VCC first, followed by VDD, and then the digital inputs. This ensures that the internal voltage regulators are powered up correctly and prevents any potential latch-up conditions.
To optimize the performance of the PCM1737E/2K, ensure that the analog power supply (VCC) is well-regulated and decoupled, and that the digital power supply (VDD) is also well-regulated and decoupled. Additionally, use a low-jitter clock source and ensure that the analog and digital grounds are separated and connected to a single point.
The maximum clock frequency that can be used with the PCM1737E/2K is 256 fs (fs = 44.1 kHz, 48 kHz, 88.2 kHz, 96 kHz, 176.4 kHz, or 192 kHz). However, the actual clock frequency used may be limited by the specific application and the quality of the clock source.
To configure the PCM1737E/2K for master clock mode, connect the MCLK pin to a clock source and set the BCK pin to the desired clock frequency. To configure the PCM1737E/2K for slave clock mode, connect the BCK pin to a clock source and set the MCLK pin to the desired clock frequency.
The recommended layout and routing for the PCM1737E/2K involves separating the analog and digital signals, using a star-ground configuration, and minimizing the length of the clock and data lines. Additionally, use a multi-layer PCB with a solid ground plane to reduce noise and EMI.
PCM1737E/2K datasheet
by Texas Instruments
