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LTC3455EUF-1#TRPBF Linear Technology LTC3455/LTC3455-1 - Dual DC/DC Converter with USB Power Manager and Li-Ion Battery Charger; Package: QFN; Pins: 24; Temperature Range: -40°C to 85°C
LTC3455EUF-1#PBF Linear Technology LTC3455/LTC3455-1 - Dual DC/DC Converter with USB Power Manager and Li-Ion Battery Charger; Package: QFN; Pins: 24; Temperature Range: -40°C to 85°C
LTC3455EUF Linear Technology LTC3455/LTC3455-1 - Dual DC/DC Converter with USB Power Manager and Li-Ion Battery Charger; Package: QFN; Pins: 24; Temperature Range: -40°C to 85°C
LTC3455EUF#PBF Linear Technology LTC3455/LTC3455-1 - Dual DC/DC Converter with USB Power Manager and Li-Ion Battery Charger; Package: QFN; Pins: 24; Temperature Range: -40°C to 85°C
LTC3455EUF#TRPBF Linear Technology LTC3455/LTC3455-1 - Dual DC/DC Converter with USB Power Manager and Li-Ion Battery Charger; Package: QFN; Pins: 24; Temperature Range: -40°C to 85°C
LTC3455EUF#TR Linear Technology LTC3455/LTC3455-1 - Dual DC/DC Converter with USB Power Manager and Li-Ion Battery Charger; Package: QFN; Pins: 24; Temperature Range: -40°C to 85°C
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CSB455E Murata Manufacturing Co Ltd Bristol Electronics 1,000 $0.75 $0.15
CSB455E-LF Chip One Exchange 335 - -

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csb 455e datasheet (2)

Part Manufacturer Description Type PDF
CSB455E muRata CERAMIC RESONATOR / CERALOCK Original PDF
CSB455E35 Hynix Semiconductor 2-4V, 455KHz, 4-bit single chip microcomputer Original PDF

csb 455e Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
csb 455e

Abstract: KF2 V6 455e M1094 squarewave generator optron M1094B1 ku band signal generator LC RESONATOR 455kHz csb 455e resonator
Text: resonator connected to pins 2 and 3, for example the 455KHz type Murata CSB 455E . The frequency of this


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PDF M1094 M1094 DIP-14 M1094B1 50-22yjF S-907S S-3076 csb 455e KF2 V6 455e squarewave generator optron M1094B1 ku band signal generator LC RESONATOR 455kHz csb 455e resonator
1998 - LA7687

Abstract: csb 400p transistor SMD t05 CSA4.00MG CSAC 2.00 MGC SMD W05 77 transistor SMD t04 CST4.00MGW csa 8.00mt U455
Text: 9.3 C* Dimensions (in mm) 3.5 9.0 7.0 CSB 455E 1.8 Standard Products 3.6 , 2.0T0.5 C 1.0max. CSB 455J 1.0T0.5 Dimensions 5.0T0.3 3.3T0.3 8.5T0.3 2.0T0.5 , This is the PDF file of catalog No.P27E-10. CERAMIC RESONATOR Ceramic Resonator CSA/ CSB Series CERALOCK® with two leaded terminals. The CSA and CSB series ceramic resonator owe their development to , consistent high quality, both the CSA and CSB series are ideally suited to microprocessor and remote control


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PDF P27E-10. P27E10 P16E-10 49MHz 50MY10 00MHz 01MY60MHz 00MY60MHz LA7687 csb 400p transistor SMD t05 CSA4.00MG CSAC 2.00 MGC SMD W05 77 transistor SMD t04 CST4.00MGW csa 8.00mt U455
1997 - csb 400p

Abstract: CSB455E csb 300d csa 8.00mt CSB murata series resonator 455e LA7687 CSA4.00MG CSTCS16 CSTCS MURATA
Text: 1.75 Dimensions (in mm) C 3.5 CSB 600P 0.3 M 7.0 3.5 CSB 455E 9.3 , 430e519kHz CSBFMJ V 2.0 M 2.3 1000J 8.5 C 5.0 3.3 CSB 455J 2 1 C M , CSA/ CSB Series (CERALOCK®) CERALOCK with two leaded terminals. R The CSA and CSB series ceramic , their high mechnical Q and consistent high quality, both the CSA and CSB series are ideally suited to , technology and the other for LS-TTL technology. The CSB series includes the thin and compact J type which is


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PDF P16E-9. P16E9 51Mb8 0Mb60MHz 01Mb60MHz 190kb1250kHz 26Mb60MHz 450kb500kHz csb 400p CSB455E csb 300d csa 8.00mt CSB murata series resonator 455e LA7687 CSA4.00MG CSTCS16 CSTCS MURATA
2000 - MC68H705

Abstract: LA7687 transistor SMD t05 transistor SMD t04 series resonator 455e TC4069UBE csb 455e csa 8.00mt CST 8.00 MTW CSTCC4.00MG
Text: 9.0 7.0 CSB 455E 1.8 Standard Products 3.6 9.0 7.9 CSB 400P 0.25 Not , Dimensions CSB 455J C 5.0T0.3 3.3T0.3 8.5T0.3 2.0T0.5 1.0 max. 7.5T0.3 1.5 1.0 , No.P16E-11. CERAMIC RESONATOR Ceramic Resonator CSA/ CSB Series CERALOCK® with two leaded terminals. The CSA and CSB series ceramic resonator owe their development to MURATA's innovative expert , and CSB series are ideally suited to microprocessor and remote control unit applications. The CSB


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PDF P16E-11. P16E11 P16E-11 00MY10 00MHz 01MY70 MC68H705 LA7687 transistor SMD t05 transistor SMD t04 series resonator 455e TC4069UBE csb 455e csa 8.00mt CST 8.00 MTW CSTCC4.00MG
LA7687

Abstract: series resonator 455e CSB murata CSTCS MURATA 8085 traffic light control CSTCS um93403 csb 400p CSB455E CSTCS16
Text: 1.75 Dimensions (in mm) C 3.5 CSB 600P 0.3 M 7.0 3.5 CSB 455E 9.3 , 430e519kHz CSBFMJ V 2.0 M 2.3 1000J 8.5 C 5.0 3.3 CSB 455J 2 1 C M , CSA/ CSB Series (CERALOCK®) CERALOCK with two leaded terminals. R The CSA and CSB series ceramic , their high mechnical Q and consistent high quality, both the CSA and CSB series are ideally suited to , technology and the other for LS-TTL technology. The CSB series includes the thin and compact J type which is


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PDF P16E-9. P16E9 51Mb8 0Mb60MHz 01Mb60MHz 190kb1250kHz 26Mb60MHz 450kb500kHz LA7687 series resonator 455e CSB murata CSTCS MURATA 8085 traffic light control CSTCS um93403 csb 400p CSB455E CSTCS16
str f 6467

Abstract: SC 455E IR3r LJ sharp EL display
Text: floating capacitance caused by wiring. · Ceramic oscillator (OSC) : CSB 455E (MURATA Mfg. Co., Ltd.) or


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PDF LR3718X 455kHz 30-pin 28-pin 24-pin 36-pin str f 6467 SC 455E IR3r LJ sharp EL display
2010 - ZTA 4.0 MG

Abstract: No abstract text available
Text: ~ 1250 KHz KHz Ceramic Resonators (ZTB) are Murata CSB Compatible Preview The ZTB series ceramic , Frequency Range (kHz) 190~249 250~374 375~429 430~699 700~1250 T ZTB H 455E L W


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PDF PC1401C LA7620 TA7777P LDA3586N LA7650 TA8654AN AN5302 ZTB912F ZTB912F101 ZTB912F104 ZTA 4.0 MG
2009 - Not Available

Abstract: No abstract text available
Text: read action Standby current ●Block diagram CSB VOLTAGE INSTRUCTION DECODE DETECTION , ●Pin assignment and description Vcc HOLDB SCK Terminal name Vcc GND CSB SCK SI SO HOLDB BR25H010-WC BR25H020-WC BR25H040-WC BR25H080-WC BR25H160-WC BR25H320-WC CSB SO WPB Input , high time 85 – – ns tSCKWH SCK low time 85 – – ns tSCKWL CSB high time tCS 85 – – ns CSB setup time tCSS 90 – – ns CSB hold time tCSH 85 – – ns SCK setup


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PDF BR25H010-WC, BR25H020-WC, BR25H040-WC, BR25H080-WC, BR25H160-WC, BR25H320-WC BR25Hâ
2007 - sck-15

Abstract: BR25H010-W BR25H020-W BR25H040-W BR25H080 BR25H080-W BR25H160-W 28TI
Text: CSB VOLTAGE INSTRUCTION DECODE DETECTION CONTROL CLOCK SCK GENERATION WRITE SI , description Vcc HOLDB SCK Terminal name Vcc GND CSB SCK SI SO CSB SO WPB GND Input , time 85 ­ ­ ns tSCKWL CSB high time tCS 85 ­ ­ ns CSB setup time tCSS 90 ­ ­ ns CSB , delay time1 tCSS tCS CSB tSCKS tPD2 ­ ­ 55 ns tOH tOZ 0 ­ ­ ­ ­ , CSB SCK tPD ns ns tHFS tSCKWL SCK SI Data output delay time2 (CL2


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PDF BR25H010-W, BR25H020-W, BR25H040-W, BR25H080-W, BR25H160-W, BR25H320-W BR25H-W sck-15 BR25H010-W BR25H020-W BR25H040-W BR25H080 BR25H080-W BR25H160-W 28TI
2002 - Not Available

Abstract: No abstract text available
Text: = 24 IOL SPI Interface Output Latch CSB 10 SCLK 3 Shift Register Q0 Q1 Q2 Q3 , essential that the SCLK pin be in a logic low state whenever chip select bar pin ( CSB ) makes any transition , state as long as the device is not accessed ( CSB in logic high state). When CSB is in a logic high state , in turn, turns OFF the specific output on the rising edge of the CSB signal. Conversely, a logic low , rising edge of the CSB signal. To program the eight outputs of the L9823 ON or OFF,an eight bit serial


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PDF L9823
2000 - Not Available

Abstract: No abstract text available
Text: by asserting CSB low. Data at the SI lead is transferred on the rising edge of SCLK. The MSB is transferred first. The outputs become active at the rising edge of CSB . Diagnostic status bits are transferred out the SO lead at the falling edge of SCLK. The SO lead is high impedance while CSB is high. An open , . The fault data is latched when CSB is asserted low. If an overcurrent condition or short circuit to , OUT2 SO SCLK QPOD VPWR 2 OUT0 3 CSB SI MicroController with Bus SCLK SO CMOS


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PDF CS1112 MS-013 CS1112YDWF24 CS1112YDWFR24
2005 - 12F629

Abstract: 12F629 adc AN-877 ANALOG DEVICES 12F629 ic 12F629 program 0X01B 0x01C 0X00E stream register AN-812
Text: : 781.461.3113 www.analog.com SPI SPI SPI / (SCLK) ( CSB ) (SDIO) (SDO) SPI CSB 0 CSB SCLK SDIO CONVERTER INTERFACE 05739-001 SPI SCLK CONTROLLER SDIO 1. CSB 0 CSB 1 SPI CONTROLLER SCLK CSB SCLK CONVERTER INTERFACE DEVICE 1 SDIO SDIO CSB SCLK CONVERTER , . 10 ( CSB ) . 3 , . 12 12/05- Revision 0: Initial Version Rev. A | Page 2 of 20 AN-877 SPI SPI ( CSB


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PDF AN-877 AN05739-0-4/07 12F629 12F629 adc AN-877 ANALOG DEVICES 12F629 ic 12F629 program 0X01B 0x01C 0X00E stream register AN-812
2007 - BR25H160-W

Abstract: BR25H040 BR25H010-W BR25H020-W BR25H040-W BR25H080 BR25H080-W
Text: read action Standby current Radiation resistance design is not made Block diagram CSB , description Vcc HOLDB SCK Terminal name Vcc GND CSB SCK SI SO CSB SO WPB GND Input , time 85 ­ ­ ns tSCKWL CSB high time tCS 85 ­ ­ ns CSB setup time tCSS 90 ­ ­ ns CSB , time OUTPUT fall time Write time timing tCSS tCS CSB tSCKS High-Z SO Fig , from the most significant bit MSB. tCS tCSH tSCKH CSB tPD2 ­ ­ 55 ns SCK 0 ­


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PDF BR25H010-W, BR25H020-W, BR25H040-W, BR25H080-W, BR25H160-W, BR25H320-W BR25H-W BR25H160-W BR25H040 BR25H010-W BR25H020-W BR25H040-W BR25H080 BR25H080-W
2010 - Not Available

Abstract: No abstract text available
Text: *Radiation resistance design is not made Block diagram CSB VOLTAGE INSTRUCTION DECODE DETECTION , Function - Power source to be connected - All input / output reference voltage, 0V CSB , , and serial data input SO Output HOLDB CSB SCK Input WPB Input GND Fig , SCK low time tSCKWL 85 - - ns CSB high time tCS 85 - - ns CSB setup time tCSS 90 - - ns CSB hold time tCSH 85 - - ns SCK setup


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PDF BR25Family BR25H-WC 10001EDT01 R1010A
2011 - BR35H-WC

Abstract: si1210
Text: Diagram CSB SCK VOLTAGE INSTRUCTION DECODE CONTROL CLOCK GENERATION WRITE INHIBITION HIGH VOLTAGE , CSB SO NC GND Fig.2 Pin Assignment Diagram Operating Timing Characteristics Terminal Name Vcc GND CSB SCK SI SO NC Input/Output ­ ­ Input Input Input Output ­ Function Power Supply , SCK frequency SCK high time SCK low time CSB high time CSB setup time CSB hold time SCK setup time SCK , ns ns ns ns ns ns ns ns ns ns ns ns s s ns ns ms CSB tSCKS tSCKWL tSCKWH tRC tFC SCK tDIS


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PDF BR35H-WC R1120A si1210
2000 - si 4422

Abstract: 751E CS1112 CS1112YDWF24 CS1112YDWFR24
Text: CONNECTIONS AND MARKING DIAGRAM VDD VPWR OUT0 IN0 GND GND GND GND IN1 OUT1 SI CSB 24 1 A , port, and at the STATUS lead. I/O Control SPI communication is initiated by asserting CSB low. Data , become active at the rising edge of CSB . Diagnostic status bits are transferred out the SO lead at the falling edge of SCLK. The SO lead is high impedance while CSB is high. An open drain output, (STATUS , latched when CSB is asserted low. If an overcurrent condition or short circuit to VBATT occurs, the


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PDF CS1112 CS1112 r14525 CS1112/D si 4422 751E CS1112YDWF24 CS1112YDWFR24
2000 - Not Available

Abstract: No abstract text available
Text: port, and at the STATUS lead. I/O Control SPI communication is initiated by asserting CSB low. Data at , become active at the rising edge of CSB . Diagnostic status bits are transferred out the SO lead at the falling edge of SCLK. The SO lead is high impedance while CSB is high. An open drain output, (STATUS , CSB is asserted low. If an overcurrent condition or short circuit to VBATT occurs, the output goes , DIAGRAM VDD VPWR OUT0 IN0 GND GND GND GND IN1 OUT1 SI CSB 1 24 ROSC STATUS OUT3 IN3 GND GND GND GND IN2


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PDF CS1112 r14525 CS1112/D
2012 - automotive eeprom

Abstract: SOPJ8 equivalent SOP-J8
Text: . Max. SCK frequency fSCK 5 MHz SCK high time 85 ns tSCKWH SCK low time 85 ns tSCKWL CSB high time tCS 85 ns CSB setup time tCSS 90 ns CSB hold time tCSH 85 ns SCK setup time 90 ns tSCKS SCK hold time 90 , 0.3Vcc / 0.7Vcc Unit pF pF ns ns V V CSB tSCKS tSCKWL tSCKWH tRC tFC CSB SCK SI tPD tCSH , After CSB starts to rise, the time needed for SO to change to High-Z is defined with 10% changing point from SO=High or SO=Low. 0.8Vcc Signal Input CSB SO Vcc NC 0.7Vcc CSB 0.2Vcc IL


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PDF BR35Hxxx-WC BR35Hxxx-WC automotive eeprom SOPJ8 equivalent SOP-J8
2012 - csb 400 P

Abstract: NCV7708
Text: CSB SI SCLK GND GND OUT1 OUT2 VCC EN SO GND ORDERING INFORMATION Device VS VS , Undervoltage Lockout VS Overvoltage Lockout OUT2 VS DRIVE 3 clk Channel Enable Fault CSB , 4 CSB 5 SI Serial Input 6 SCLK Serial Clock 7 GND* Ground. Connect all , 120k 22 mF GND VCC 10 mF VS OUT1 EN microprocessor M OUT2 CSB SI , (Logic Input pins, SI, SCLK, CSB , SO, EN, VCC) Output Current (OUTx) (DC) (AC) (50 ms pulse, 1 s


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PDF NCV7703B NCV7703B NCV7708 NCV7703B/D csb 400 P
2013 - Not Available

Abstract: No abstract text available
Text: - - ns SCK Low Time tSCKWL 85 - - 40 - - ns CSB High Time tCS 85 - - 40 - - ns CSB Setup Time tCSS 90 - - 30 - - ns CSB Hold Time tCSH 85 - - 30 - - ns SCK , .001 Datasheet BR25H040-2C ●Serial Input / Output Timing tCSS tCS CSB tSCKS tSCKWL tRC , tCSH tSCKH CSB SCK SI tPD tRO,tFO tOH tOZ High-Z SO Figure 3. Input / Output


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PDF BR25H040-2C BR25H040-2C 10MHz
2000 - Not Available

Abstract: No abstract text available
Text: asserting CSB low. Data at the SI lead is transferred on the rising edge of SCLK. The MSB is transferred first. The outputs become active at the rising edge of CSB . Diagnostic status bits are transferred out the SO lead at the falling edge of SCLK. The SO lead is high impedance while CSB is high. An open , . The fault data is latched when CSB is asserted low. If an overcurrent condition or short circuit to , OUT2 SO SCLK QPOD VPWR 2 OUT0 3 CSB SI MicroController with Bus SCLK SO CMOS


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PDF CS1112 CS1112 MS-013 CS1112YDWF24 CS1112YDWFR24
2013 - Not Available

Abstract: No abstract text available
Text: - - ns SCK Low Time tSCKWL 85 - - 40 - - ns CSB High Time tCS 85 - - 40 - - ns CSB Setup Time tCSS 90 - - 30 - - ns CSB Hold Time tCSH 85 - - 30 - - ns SCK , .002 Datasheet BR25H160F-2LB Serial Input / output Timing tCSS tCS CSB tSCKS tSCKWL tRC , tCSH tSCKH CSB SCK SI tPD tRO,tFO tOH tOZ High-Z SO Figure 3. Input / Output


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PDF BR25H160F-2LB BR25H160F-2LB 10MHz
2010 - BR25S320

Abstract: br25s640 BR25S320-W VSON008 BR25S640-W VSON008X2030 mark e2
Text: reserved. 2/18 2010.02 - Rev.A Technical Note BR25S320/640/128/256-W Block diagram CSB , 20 ns SCK low time tCS 250 90 40 20 ns CSB high time tCSS 100 60 30 15 ns CSB setup time 100 60 30 15 ns tCSH CSB hold time tSCKS 100 50 20 15 ns SCK setup time tSCKH 100 , reference voltage, 0V CSB Input Chip select input SCK Input Serial clock input SI , Input BR25S320-W BR25S640-W BR25S128-W BR25S256-W CSB SO WPB GND Fig.2 Pin


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PDF BR25family BR25S320-W BR25S640-W BR25S128-W BR25S256-W 10001EAT08 BR25S-W 20MHz R1010A BR25S320 br25s640 VSON008 VSON008X2030 mark e2
2012 - Not Available

Abstract: No abstract text available
Text: , load capacity CL1=100pF) Parameter SCK frequency SCK high time SCK low time CSB high time CSB setup time CSB hold time SCK setup time SCK hold time SI setup time SI hold time Data output delay time1 Data , .Apr.2012 Rev.001 BR25H320-2C Sync data input / output timing tCS tCSS Datasheet CSB tSCKS tSCKWL , sync with data rise edge of SCK. Input address and data from the most significant bit MSB. tCS CSB , output in sync with data fall edge of SCK. Data is output from the most significant bit MSB. "H" CSB


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PDF BR25xxxxFamily BR25H320-2C BR25H320-2C 10MHz
2013 - Not Available

Abstract: No abstract text available
Text: - - ns SCK Low Time tSCKWL 85 - - 40 - - ns CSB High Time tCS 85 - - 40 - - ns CSB Setup Time tCSS 90 - - 30 - - ns CSB Hold Time tCSH 85 - - 30 - - ns SCK , .002 Datasheet BR25H010F-2LB Serial Input / Output Timing tCSS tCS CSB tSCKS tSCKWL tRC , tCSH tSCKH CSB SCK SI tPD tRO,tFO tOH tOZ High-Z SO Figure 3. Input / Output


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PDF BR25H010F-2LB BR25H010F-2LB 10MHz
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