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2008 - PLX PCI9030 bridge

Abstract: pci target plx 9030 PCI9030 cpldbased 64-BIT SOUND CARD Altera N ROHS EPM2210 EPM1270 MAX PLUS II Programmable Logic Development System & Software
Text: block diagram of Altera's MAX II CPLD-based PCI target interface solution. WP-AAB090305-1.3 March , Corporation Figure 2. Altera's MAX II CPLD-Based PCI Target Interface Solution Block Diagram 32-bit PCI I , interrupts Endian byte swapping Local address remap Altera's MAX II CPLD-based PCI target interface , and MAX II CPLD-Based PCI Target Interface Solution Supplier MAX II Device PCI Target , of the MAX II CPLD-Based PCI Target Interface Implementing a PCI target interface does not require


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1997 - XC9536-PC44

Abstract: xc9536pc44 UV-eprom programmer schematic XC7336 27 eprom programmer schematic ADR12 XC9536pc xilinx xc9536 Schematic HW-130 ADR11
Text: ® XAPP079 March, 1997 (Version 1.0) CPLD-Based 1Mbit Virtual SPROM Downloader for , of a very low cost, CPLD-based virtual SPROM downloader for programming the Xilinx high density , CPLD-Based 1Mbit Virtual SPROM Downloader for XC4000-Series FPGAs design can easily be expanded to 4 Mbits , U2 CPLD-Based 1Mbit Virtual SPROM Downloader for XC4000-Series FPGAs MODULE VSPROM TITLE ` , March, 1997 (Version 1.0) 5 CPLD-Based 1Mbit Virtual SPROM Downloader for XC4000-Series FPGAs


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PDF XAPP079 XC4000-Series XC4000-Series XC7300, XC9500 XC9536-PC44 xc9536pc44 UV-eprom programmer schematic XC7336 27 eprom programmer schematic ADR12 XC9536pc xilinx xc9536 Schematic HW-130 ADR11
2008 - Stepper Motor Circuit for Analog speedometer

Abstract: cluster speedometer stepper motor Stepper Motor for speedometer vid29 speedometer digital car dashboard cluster stepper motor VID-29 555 circuit stepper motor sensor input speedoMETER
Text: vehicles owing to the unfavorable price/performance ratio. CPLD-Based Dashboard Cluster Controller The , Altera Corporation Altera has developed this CPLD-based ADS, enabling product developers and , . CPLD-Based ADS Block Diagram To further describe the elements of the CPLD-based ADS architecture, it will , overall performance of the system. The CPLD-based ADS can be scaled up easily for even more accuracy and


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1999 - XC9500XV

Abstract: XCV1000 XC95288XV XC95 XC9572XV XC9536XV XC95144XV XC9500XL TQ100 PC44
Text: CPLD-based electronic products can be easily streamlined through the use of ISP and the Java API for


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PDF XC9500XV XC9500XV 54-input 36-macrocell XC9536XV XCV1000 XC9536XV XC95288XV XC95 XC9572XV XC95144XV XC9500XL TQ100 PC44
xcf128x

Abstract: XC6VLX75T XC6VLX130T XC6VLX240T XC6VSX315T XCF32P XC6VLX760 HW-USB-II-G xc6vlx195t XC6slx45
Text: Flash PROMs and Spartan-3E FPGAs - XAPP483 A CPLD-Based Configuration and Revision Manager for Xilinx


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PDF XCF01S XCF02S XCF04S XCF08P XCF16P XCF32P XCF128X 128Mb XC6VLX75T xcf128x XC6VLX75T XC6VLX130T XC6VLX240T XC6VSX315T XCF32P XC6VLX760 HW-USB-II-G xc6vlx195t XC6slx45
Not Available

Abstract: No abstract text available
Text: C-Mod boards, which measure just 0.7” by 2.16”, allow designers to experiment with CPLD-based


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PDF 600-mil, 40-pin
1998 - VHDL CODE FOR HDLC controller

Abstract: Multi-Channel hdlc Controller vhdl code for pcm bit stream generator VHDL CODE FOR HDLC interrupt controller in vhdl code hdlc C1000 cpldbased slot machine block diagram vhdl
Text: and high performance. This article describes a CPLD-based (Complex Programmable Logic Device , PCI "Master" Interface. VHDL code is available for use as a template to implement the CPLD-based


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2000 - VHDL CODE FOR HDLC controller

Abstract: VHDL CODE FOR HDLC vhdl code for pcm bit stream generator slot machine block diagram vhdl
Text: performance. This article describes a CPLD-based (Complex Programmable Logic Device) approach that fulfills , to implement the CPLD-based approach to the controller. Source code files can be obtained from your


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PDF 16-bit 1-800-LATTICE VHDL CODE FOR HDLC controller VHDL CODE FOR HDLC vhdl code for pcm bit stream generator slot machine block diagram vhdl
1998 - VHDL CODE FOR HDLC controller

Abstract: VHDL CODE FOR HDLC vhdl code CRC 32 vhdl code for pcm bit stream generator vhdl code for sdram controller slot machine block diagram vhdl motorola C1000 Multi-Channel hdlc Controller C1000 PCMT
Text: and high performance. This article describes a CPLD-based (Complex Programmable Logic Device , as a template to implement the CPLD-based approach to the controller. For this given implementation


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IPTV STB

Abstract: AN8080 4000ZE TN1187
Text: smart switch CPLD during an automated factory programming step. Figure 1 - IP-TV STB with CPLD-based


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PDF mach4000zepicodevkit 4000ZE TN1187 com/documents/tn1187 textbase/nppdf/free/2000/blipinthenight01 AN8080 com/documents/an8080 IPTV STB AN8080 TN1187
1997 - UV-eprom programmer schematic

Abstract: 27 eprom programmer schematic EPROM 30 pin programmer schematic xilinx xc9536 Schematic xc9536 cpld XAPP079 XC4013EX HW-130 XC9536 ADR14
Text: ® XAPP079 September, 1997 (Version 1.2) 4Mbit Virtual SPROM Application Note Summary This application note describes the design of a very low cost, CPLD-based virtual SPROM for downloading programming information to the Xilinx high density XC4000-Series FPGAs. Xilinx Family XC9500 Introduction Typically, designers of embedded applications use serial PROMs (SPROMs) to store and download the configuration data for XC4000-Series FPGAs. SPROMs yield faster configuration rates and reduce


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PDF XAPP079 XC4000-Series XC9500 UV-eprom programmer schematic 27 eprom programmer schematic EPROM 30 pin programmer schematic xilinx xc9536 Schematic xc9536 cpld XC4013EX HW-130 XC9536 ADR14
2009 - COOLRUNNER-II examples

Abstract: 245RL CPLD XC2C64 from Xilinx CoolRunner-II family CP132 equivalent 8x8 keyboard and microcontroller interfacing altera board M100 XC2C128 XC2C64 keypad 8x8
Text: obsolescence. Table 3. Comparison of Altera MAX II CPLD-Based and Discrete-Based Functions in Portable Systems


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4000ZE

Abstract: No abstract text available
Text: drawn. Use slow slew rate I/Os when possible. Conclusion Most CPLD-based designs include at least a


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2007 - 8 way dip switch

Abstract: an484_design_example.zip AN3315 AN3230 EPM240 EPM240G 6-pin JTAG header altera max "1 wire slave interface" verilog
Text: CPLDBased SMBus to GPIO Pin Expander Altera Corporation AN-484-1.0 The MAX II CPLD acts as a slave


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1999 - XC9536vq44

Abstract: XC9536-VQ44 XCV300BG432 XAPP178 XAPP098 XC9536VQ44-10
Text: Application Note: Spartan-II Family R XAPP178 (v0.9) December 3, 1999 Configuring Spartan-II FPGAs from Parallel EPROMs Advance Application Note Summary This application note describes a simple CPLD-based interface design to configure a SpartanTM-II device from a parallel EPROM using the Slave Parallel configuration mode. Introduction Many FPGA users prefer to store configuration data on parallel PROMs because they are available in greater storage capacities than serial PROMs. A


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PDF XAPP178 XAPP098 35760h. XC9536vq44 XC9536-VQ44 XCV300BG432 XAPP178 XAPP098 XC9536VQ44-10
2004 - XCF00

Abstract: XAPP693 verilog code for implementation of prom DS123 verilog code for parallel flash memory FPGA Virtex 6 pin configuration verilog code for frame synchronization watchdog vhdl
Text: Application Note: Coolrunner-II CPLD and Spartan/Virtex FPGA Families R XAPP693 (v1.1) January 19, 2005 A CPLD-Based Configuration and Revision Manager for Xilinx Platform Flash PROMs and FPGAs Author: Don St. Pierre Summary This application note illustrates the use of a Xilinx CoolRunnerTM-II CPLD to monitor configuration data between a Xilinx Platform Flash Configuration PROM and a Xilinx SpartanTM or VirtexTM family FPGA. The intent is to ensure reliable configuration of the FPGA


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PDF XAPP693 com/bvdocs/appnotes/xapp693 XCF00 XCF00 XAPP693 verilog code for implementation of prom DS123 verilog code for parallel flash memory FPGA Virtex 6 pin configuration verilog code for frame synchronization watchdog vhdl
2007 - XAPP424

Abstract: XAPP412 XAPP502 SSYA002C X424 XAPP058 XAPP500 XAPP503 XAPP693
Text: CPLD-Based Configuration and Revision Manager for Xilinx Platform Flash PROMs and FPGAs 4. XAPP502, Using a


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PDF XAPP424 XAPP424 XAPP412 XAPP502 SSYA002C X424 XAPP058 XAPP500 XAPP503 XAPP693
distance vector routing

Abstract: SRL16 128X1
Text: offers superior scalability at higher densities. Unlike CPLD-based fixed-length routing FPGA


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1995 - associated with each design are the assignment and configuration files

Abstract: No abstract text available
Text: , and also covers important design considerations in developing a CPLD-based PCI application. These


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PDF 7000E associated with each design are the assignment and configuration files
2009 - C2226

Abstract: R4042
Text: maximum PCI frequency that the CPLD-based arbiter can support is 33MHz 9due to a CPLD limitation. The


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PDF Tsi352 80D6000 74LVC1G14 XCR3064XL-6VQ44C SN74CB3T3257 Tsi352 32BIT, 66MHZ CY2305 C2226 R4042
2007 - ACE FLASH

Abstract: XAPP502 XAPP500 XAPP503 XAPP693 X424 XAPP058 XAPP412 XAPP424
Text: . XAPP503, SVF and XSVF File Formats for Xilinx Devices 3. XAPP693, A CPLD-Based Configuration and Revision


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PDF XAPP424 ACE FLASH XAPP502 XAPP500 XAPP503 XAPP693 X424 XAPP058 XAPP412 XAPP424
2001 - bluetooth transmitter receiver

Abstract: bluetooth transmitter receiver parallel chip bluetooth controller usb PCI32 PCI64
Text: flexibility and reprogrammability FPGA- and CPLD-based systems are best for handling the inevitable unknowns


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PDF WP142 com/xapp/xapp223 bluetooth transmitter receiver bluetooth transmitter receiver parallel chip bluetooth controller usb PCI32 PCI64
2006 - XAPP483

Abstract: spartan MultiBoot trigger DS123 XAPP693 XCF16P XCF32P xilinx spartan-3E FPGA Image Load
Text: implement a truly fail-safe solution. Refer to XAPP693, A CPLD-Based Configuration and Revision Manager for


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PDF XAPP483 XAPP483 spartan MultiBoot trigger DS123 XAPP693 XCF16P XCF32P xilinx spartan-3E FPGA Image Load
2001 - CY7C0430BV

Abstract: CY7C04312BV CY7C04314BV
Text: the logic of a CPLD-based switch fabric. The switch fabric could be designed with parallel interfaces


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2002 - XAPP382

Abstract: JESD 85 LVCMOS25-Low-Voltage COOLRUNNER-II examples COOLRUNNER-II test circuit LVCMOS25 LVCMOS33 LVCMOS33-Low
Text: of CoolRunner-II CPLD-based designs. XAPP382 (v1.0) November 11, 2002 www.xilinx.com


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PDF XAPP382 XAPP382 JESD 85 LVCMOS25-Low-Voltage COOLRUNNER-II examples COOLRUNNER-II test circuit LVCMOS25 LVCMOS33 LVCMOS33-Low
Supplyframe Tracking Pixel