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Part Manufacturer Description Datasheet Download Buy Part
LT1508CSW20 Linear Technology IC POWER FACTOR CONTROLLER WITH POST REGULATOR, PDSO20, 0.300 INCH, PLASTIC, SO-20, Switching Regulator or Controller
LT1509CSW20 Linear Technology IC POWER FACTOR CONTROLLER WITH POST REGULATOR, PDSO20, 0.300 INCH, PLASTIC, SO-20, Switching Regulator or Controller
LT4256-3CGN Linear Technology LT4256-3 - Positive High Voltage Hot Swap Controller with Open-Circuit Detect; Package: SSOP; Pins: 16; Temperature Range: 0°C to 70°C
LT4254CGN#TRPBF Linear Technology LT4254 - Positive High Voltage Hot Swap Controller with Open-Circuit Detect; Package: SSOP; Pins: 16; Temperature Range: 0°C to 70°C
LT4254IGN#PBF Linear Technology LT4254 - Positive High Voltage Hot Swap Controller with Open-Circuit Detect; Package: SSOP; Pins: 16; Temperature Range: -40°C to 85°C
LT4256-3CGN#PBF Linear Technology LT4256-3 - Positive High Voltage Hot Swap Controller with Open-Circuit Detect; Package: SSOP; Pins: 16; Temperature Range: 0°C to 70°C

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IC 7476

Abstract: 7476 truth table circuit diagram with IC 7476 7476 IC J-K Flip-Flop 7476 7476 logic diagram 7476 Connection diagram 7476 ttl 7476 J-K Flip-Flop logic ic 7476
Text: FAIRCHILD TTL/SSI . 9N76/5476, 7476 DUAL JK MASTER/SLAVE FLIP-FLOP WITH SEPARATE PRESETS, CLEARS AND CLOCKS DESCRIPTION - The TTL/SSI 9N76/5476, 7476 is a Dual JK Master/Slave flip-flop with separate , slave. LOGIC AND CONNECTION DIAGRAM DIP (TOP VIEW) K, Q, 0, GND l<2 Q2 Q2 h FLATPAK (TOP VIEW) K, Q, Q , NOTES: tn = Bit time before clock pulse. tn+-j = Bit time after clock pulse. SCHEMATIC DIAGRAM (EACH FLIP-FLOP) Component values shown are typical. CLOCK WAVEFORM LOGIC DIAGRAM (EACH FLIP-FLOP) CLOCK O 5-118


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PDF 9N76/5476, 11N76/7476 400ft IC 7476 7476 truth table circuit diagram with IC 7476 7476 IC J-K Flip-Flop 7476 7476 logic diagram 7476 Connection diagram 7476 ttl 7476 J-K Flip-Flop logic ic 7476
2007 - IC 7476

Abstract: INTERNAL DIAGRAM OF IC 7476 IC 7476 function applications IC 7476 circuit diagram with IC 7476 assignment on bluetooth 7476 IC 7476 Connection diagram PVH071902 of IC 7476 in file
Text: /5/EU. This device contains: FCC ID: PVH071902 IC : 5325A-0719X This device complies with Part , OUT Short circuit or overload at one of the outputs IN FS 7476 _en_02 Failsafe, analog and , 13 ILB BT ADIO 2/2/16/16 Internal Basic Circuit Diagram UL FS ID plus Antenna ID , with electrical isolation Optocoupler Input filter Output driver 7476 _en_02 PHOENIX CONTACT , ILB BT ADIO 2/2/16/16 Bluetooth I/O Module With 16 Digital Inputs and 16 Digital Outputs and 2


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PDF Bm/39 IC 7476 INTERNAL DIAGRAM OF IC 7476 IC 7476 function applications IC 7476 circuit diagram with IC 7476 assignment on bluetooth 7476 IC 7476 Connection diagram PVH071902 of IC 7476 in file
pin diagram of 7476

Abstract: 7476 J-K Flip-Flop PIN CONFIGURATION 7476 7476 FUNCTION TABLE 7476 7476 PIN DIAGRAM Jk 74ls76 pin out 74LS76 flip-flop 74ls76 7476 PIN DIAGRAM input and output
Text: Signetics 7476 , LS76 Flip-Flops Dual J-K Flip-Flop Product Specification Logic Products DESCRIPTION The '76 is a dual J-K flip-flop with Individual J, K, Clock, Set and Reset inputs. The 7476 is , Flip-Flops 7476 , LS76 LOGIC DIAGRAM FUNCTION TABLE INPUTS OPERATING MODE SD Asynchronous set , the outputs to the steady state levels as shown in the Function Table. TYPE 7476 74LS76 TYPICAL f HAX , Clock for predictable operation. 3. The J and K inputs of the 7476 must be stable while the Clock is HIG


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PDF 74LS76 1N916, 1N3064, 500ns 500ns pin diagram of 7476 7476 J-K Flip-Flop PIN CONFIGURATION 7476 7476 FUNCTION TABLE 7476 7476 PIN DIAGRAM Jk 74ls76 pin out flip-flop 74ls76 7476 PIN DIAGRAM input and output
ci 7476

Abstract: 7476 PIN DIAGRAM pin diagram of 7476 jk flip flop 7476 pin diagram of ttl 7476 7476 7476 PIN DIAGRAM input and output 7476 ttl 7476 J-K Flip-Flop LS 7476
Text: circuit should not exceed one second. _ 4. With the Clock Input grounded and all outputs open. Ice is , Signetics Logic Products DESCRIPTION The '76 is a dual J-K flip-flop with individual J, K, Clock, Set and Reset inputs. The 7476 is positive pulse-triggered. JK information is loaded into the , Table. 7476 , LS76 Flip-Flops Dual J-K Flip-Flop Product Specification TYPE TYPICAL fMAX TYPICAL SUPPLY CURRENT (TOTAL) 7476 20MHz 10mA 74LS76 45MHz 4mA ORDERING CODE PACKAGES COMMERCIAL RANGE VCC =


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PDF 74LS76 1N916, 1N3064, 500ris 500ns ci 7476 7476 PIN DIAGRAM pin diagram of 7476 jk flip flop 7476 pin diagram of ttl 7476 7476 7476 PIN DIAGRAM input and output 7476 ttl 7476 J-K Flip-Flop LS 7476
PIN CONFIGURATION 7476

Abstract: pin diagram of 7476 7476 PIN DIAGRAM 7476 FUNCTION TABLE pin diagram of ttl 7476 7476 pin configuration LS 7476 7476 PIN DIAGRAM input and output 74LS76 J-K Flip-Flop 7476
Text: Sjgnetics 7476 , LS76 Flip-Flops Dual J-K Flip-Flop Product Specification Logic Products DESCRIPTION The '76 is a dual J-K flip-flop with individual J, K, Clock, Set and Reset inputs. The 7476 is , duration of the short circuit should not exceed one second. 4. With the Clock input grounded and all , , forcing the outputs to the steady state levels as shown in the Function Table. TYPE 7476 74LS76 TYPICAL f , 5-114 853-0566 81501 Signetics Logic Products Product S pecification Flip-Flops 7476


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PDF 74LS76 1N916, 1N3064, 500ns 500ns PIN CONFIGURATION 7476 pin diagram of 7476 7476 PIN DIAGRAM 7476 FUNCTION TABLE pin diagram of ttl 7476 7476 pin configuration LS 7476 7476 PIN DIAGRAM input and output J-K Flip-Flop 7476
pin diagram of 7476

Abstract: PIN CONFIGURATION 7476 74LS76 7476 PIN DIAGRAM input and output 7476 FUNCTION TABLE Jk 74ls76 pin out 7476 J-K Flip-Flop 7476 pin configuration TTL 7476 7476 logic diagram
Text: Signetics 7476 , LS76 Flip-Flops Dual J-K Flip-Flop Product Specification Logic Products DESCRIPTION The '76 is a dual J-K flip-flop with individual J, K, Clock, Set and Reset inputs. The 7476 is , 81501 Signetics Logic Products Product Specification Flip-Flops 7476 , LS76 LOGIC DIAGRAM , the outputs to the steady state levels as shown in the Function Table. TYPE 7476 74LS76 TYPICAL f MAx , inputs of the 7476 must be stable while the Clock is HIGH for conventional operation. December 4, 1965


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PDF 74LS76 1N916, 1N3064, 500ns 500ns pin diagram of 7476 PIN CONFIGURATION 7476 7476 PIN DIAGRAM input and output 7476 FUNCTION TABLE Jk 74ls76 pin out 7476 J-K Flip-Flop 7476 pin configuration TTL 7476 7476 logic diagram
jk flip flop 7476

Abstract: 7476 PIN DIAGRAM 7476 7476 ttl TTL 74ls76 7476 PIN DIAGRAM input and output pin diagram of 7476 PIN CONFIGURATION 7476 pin diagram of ttl 7476 7476 J-K Flip-Flop
Text: Flip-Flops 7476 , LS76 LOGIC DIAGRAM ld02900s FUNCTION TABLE OPERATING MODE INPUTS OUTPUTS SD Rd , should be shorted at a time and duration of the short circuit should not exceed one second. 4. With the , Signetics Logic Products DESCRIPTION The '76 is a dual J-K flip-flop with individual J, K, Clock, Set and Reset inputs. The 7476 is positive pulse-triggered. JK information is loaded into the , understood to be 40>iA l,H and -1.6mA l,L. and a 74LS unit load (LSul) is 20juA l)H and -0.4mA l|L. 7476


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PDF 74LS76 1N916, 1N3064, 500ns jk flip flop 7476 7476 PIN DIAGRAM 7476 7476 ttl TTL 74ls76 7476 PIN DIAGRAM input and output pin diagram of 7476 PIN CONFIGURATION 7476 pin diagram of ttl 7476 7476 J-K Flip-Flop
2011 - TS820600T

Abstract: TYN608RG TS820-600B TS8206 TS820-600BTR TS820-600T TS820-600 TYN608 scr TYN608 ts820600b
Text: Doc ID 7476 Rev 7 1/13 www.st.com 13 Characteristics TN805, TN815, TS820, TYN608 1 , 200 0.8 0.1 8 5 6 5 1.6 0.85 46 5 Unit µA V V V mA mA V/µs V V m µA 2/13 Doc ID 7476 Rev 7 , 6 IT(AV)(A) 1 0 0 25 Tcase(°C) 50 75 100 125 Doc ID 7476 Rev 7 3/13 , IT(AV)(A) 2,5 D.C. = 180° K=[Zth(j-c)/Rth(j-c)] Recommended pad layout, FR4 printed circuit , IGT,IH,IL[Tj] / IGT,IH,IL[Tj=25°C] 1.8 IGT Recommended pad layout, FR4 printed circuit board


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PDF TN805, TN815 TS820, TYN608 TS820-6d TS820600T TYN608RG TS820-600B TS8206 TS820-600BTR TS820-600T TS820-600 TYN608 scr TYN608 ts820600b
IC 7476 function

Abstract: 41814 T1052
Text: , RGK 2 10 n IL forward off-state and reverse Currents gate controlled delay time circuit , °C Mechanical properties Si-pellet with pressure contact Clamping force weight Creepage distance humidity , /Delivery for larger quantities on request 1) Werte nach DIN IEC 747-6 (ohne vorausgehende Kommutierung)/Values to DIN IEC 747-6 (without prior commutation) 2) Unmittelbar nach der Freiwerdezeit, vgl. Meßbedingungen für t,/lmmediately after circuit commutated turn-off time, see Parameters t, 3) nur in Verbindung


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PDF T1052 IC 7476 function 41814
2011 - TS820 600T

Abstract: No abstract text available
Text: -220AB October 2011 X Doc ID 7476 Rev 7 1/13 www.st.com 13 Characteristics TN805, TN815, TS820 , 220 Ω Tj = 25 °C Tj = 125 °C Doc ID 7476 Rev 7 MAX. TN805, TN815, TS820, TYN608 , ) 0 0 0 1 2 3 4 5 6 0 Doc ID 7476 Rev 7 25 50 75 100 125 , , FR4 printed circuit board D.C. α = 180° 2,0 0.5 TO-220AB TO-220FPAB 1,5 1,0 0.2 , 2.0 Recommended pad layout, FR4 printed circuit board 1.8 IGT 1.6 1.4 DPAK 1.2


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PDF TN805, TN815 TS820, TYN608 TS820-600H TN805-600B TN815-x00B TS820-600B TS820 600T
2010 - TYN608

Abstract: TYN808 SCR 600V, 8A, 15mA Igt 7476 TN805 TN815 TS820 TYN08 TYN1008
Text: ID 7476 Rev 6 X 1/12 www.st.com 12 Characteristics TN805, TN815, TS820, TYN608 , VRRM, RGK = 220 Tj = 25 °C Tj = 125 °C Doc ID 7476 Rev 6 MAX. TN805, TN815, TS820 , ID 7476 Rev 6 25 50 75 100 125 3/12 Characteristics Figure 3. TN805 , pulse duration K=[Zth(j-c)/Rth(j-c)] 2.0 1.0 Recommended pad layout, FR4 printed circuit , layout, FR4 printed circuit board 1.8 IGT 1.6 1.4 DPAK 1.2 0.10 IH & IL RGK = 1k


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PDF TN805, TN815, TS820 TYN608, TYN808, TYN1008 TN805-xxxB TN815-xxxB TS820-xxxB TN805-xxxH TYN608 TYN808 SCR 600V, 8A, 15mA Igt 7476 TN805 TN815 TS820 TYN08 TYN1008
1998 - din 41814

Abstract: 41814 T1052
Text: , RGK 2 10 n IL forward off-state and reverse Currents gate controlled delay time circuit , °C Mechanical properties Si-pellet with pressure contact Clamping force weight Creepage distance humidity , /Delivery for larger quantities on request 1) Werte nach DIN IEC 747-6 (ohne vorausgehende Kommutierung)/Values to DIN IEC 747-6 (without prior commutation) 2) Unmittelbar nach der Freiwerdezeit, vgl. Meßbedingungen für t,/lmmediately after circuit commutated turn-off time, see Parameters t, 3) nur in Verbindung


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PDF T1052 din 41814 41814
W1A 73

Abstract: Diode LT 410 ic tms 1000 81 210 W 20 w1A 49 W1A 95 dt61n dt250n
Text: Thyristor-Dioden-Module fur l-Umrichter Thyristor-diode-modules for current source inverters Modules thyristor-diode pour convertisseurs à circuit intermédiaire à courant continu Typ Type Basisplatte/Baseplate/Face basale = 20 mm TD 61 N 14/20 1400 2000 120 1,4 9,8 76/68 0,8 3,4 1 Vdrm Vrrm Itrmsm Itsm /i2dt Itavm/ IC V(TO) l"T (di/dt)cr tq (dv/dt)or RthJC RthCK ^vj max Vrrm (Thyr , max I EC 747-6 I EC 747-6 sin V V A kA kA2s A/°C V m£i A/|j.s (J.S V/fiS °c/w °c/w °c


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PDF asi/73 W1A 73 Diode LT 410 ic tms 1000 81 210 W 20 w1A 49 W1A 95 dt61n dt250n
2000 - m1g4

Abstract: No abstract text available
Text: °C, iGM = 0,6A, diG/dt = 0,6A/µs Tvj = Tvj max DIN IEC 747-6 Freiwerdezeit circuit commutated , with Chopper-IGBT TD B6HK 104 N 16 RR N B6 Elektrische Eigenschaften / Electrical , DIN IEC 747-6 Kritische Spannungssteilheit critical rate of rise of off-state voltage Tvj = Tvj , °C IC Periodischer Kollektor-Spitzenstrom repetitive peak collektor current t p = 1ms ICRM , Thyristor-Modul mit Chopper-IGBT Thyristor Module with Chopper-IGBT TD B6HK 104 N 16 RR N B6


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1999 - TT46N

Abstract: No abstract text available
Text: circuit commutated turn-off time Isolations-Prüfspannung insulation test voltage Thermische , /dt = 0,75 A/µs, tg = 20 tvj = tvj max vD = VDRM , vR = VRRM DIN IEC 747-6 , tvj = 25°C iGM = 0,75 , , tp = 10 ms tvj = 25°C, tp = 10 ms tvj = tvj max , tp = 10 ms DIN IEC 747-6 , f = 50 Hz, vL = 10 V , / 1300V on demand Werte nach DIN IEC 747-6 (ohne vorrausgehende Kommutierung). / Values to DIN IEC 747-6 , . / Immediatly after circuit commutated turn-off time, see parameters t q. 2) AlN 4 Nm 4 Nm typ. 180 g


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2000 - Not Available

Abstract: No abstract text available
Text: with Chopper-IGBT TD B6HK 74 N 16 RR N B6 Elektrische Eigenschaften / Electrical properties , °C, tp = 10ms Kritische Stromsteilheit critical rate of rise of on-state current DIN IEC 747-6 , collector-emitter voltage V CES Kollektor-Dauergleichstrom DC-collector current TC = 80°C IC , Thyristor Module with Chopper-IGBT TD B6HK 74 N 16 RR N B6 Elektrische Eigenschaften , VDRM, vR = VRRM Zündverzug gate controlled delay time DIN IEC 747-6 Tvj = 25°C, iGM = 0,6A


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2000 - B6HK

Abstract: thyristor TD 45 N 1200
Text: with Chopper-IGBT TD B6HK 74 N 16 RR N B6 Elektrische Eigenschaften / Electrical properties , = 10ms Kritische Stromsteilheit critical rate of rise of on-state current DIN IEC 747-6 , voltage V CES Kollektor-Dauergleichstrom DC-collector current TC = 80°C IC Periodischer , / Technical Information Thyristor-Modul mit Chopper-IGBT Thyristor Module with Chopper-IGBT TD B6HK 74 N , vD = VDRM, vR = VRRM Zündverzug gate controlled delay time DIN IEC 747-6 Tvj = 25°C, iGM = 0


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1998 - Not Available

Abstract: No abstract text available
Text: Currents gate controlled delay time circuit commutated turn-off time t, = t, max, iT = 4000 A t, = t, max , storage temperature Mechanical properties Si-pellet with pressure contact Clamping force weight Creepage , request 1) Werte nach DIN IEC 747-6 (ohne vorausgehende Kommutierung)/Values to DIN IEC 747-6 (without , circuit commutated turn-off time, see Parameters t, 3) nur in Verbindung mit (dv/dt), = B oder L/only in connection with (dv/dt), = B or L 125 T 1052 S BildlFig. 16 Rückstromspitze IRM = f(-dildt), ts


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PDF T1052
2000 - Not Available

Abstract: No abstract text available
Text: max, tp = 10ms DIN IEC 747-6 f=50 Hz, iGM = 1 A diG/dt = 1 A/µs Kritische Spannungssteilheit , currents T vj = Tvj max Zündverzug gate controlled delay time DIN IEC 747-6 vD = VDRM, vR = VRRM T vj = 25°C iGM = 1 A, diG/dt = 1 A/µs 1) Werte nach DIN IEC 747-6 (ohne vorausgehende Kommutierung). / Values to DIN IEC 747-6 (without prior commutation). 2) Unmittelbar nach der Freiwerdezeit, vgl. Meßbedingungen für tq ./ Immediately after circuit commutated turn-off-time, see parameters tq


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Not Available

Abstract: No abstract text available
Text: circuit commutated turn-off time vRM = 100V, VDM = 0,67 VDRM Tvj = Tvj max DIN IEC 747-6 Tvj = , with Chopper-IGBT N TD B6HK 124 N 16 RR B6 Elektrische Eigenschaften / Electrical , DIN IEC 747-6 Kritische Spannungssteilheit critical rate of rise of off-state voltage Tvj = Tvj , 80°C IC Periodischer Kollektor-Spitzenstrom repetitive peak collektor current t p = 1ms , Thyristor-Modul mit Chopper-IGBT Thyristor Module with Chopper-IGBT N TD B6HK 124 N 16 RR B6


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2000 - 7476 IC data

Abstract: 1200V 100 A THYRISTOR CHopper DC
Text: °C, iGM = 0,6A, diG/dt = 0,6A/µs Tvj = Tvj max DIN IEC 747-6 Freiwerdezeit circuit commutated , with Chopper-IGBT TD B6HK 124 N 16 RR N B6 Elektrische Eigenschaften / Electrical , DIN IEC 747-6 Kritische Spannungssteilheit critical rate of rise of off-state voltage Tvj = Tvj , °C IC Periodischer Kollektor-Spitzenstrom repetitive peak collektor current t p = 1ms ICRM , Thyristor-Modul mit Chopper-IGBT Thyristor Module with Chopper-IGBT TD B6HK 124 N 16 RR N B6


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1999 - tt46n

Abstract: No abstract text available
Text: tvj = 25°C, tp = 10 ms tvj = tvj max , tp = 10 ms DIN IEC 747-6 , f = 50 Hz, vL = 10 V IGM = 0,75 A , IEC 747-6 , tvj = 25°C iGM = 0,75 A, diG/dt = 0,75 A/µs tvj = tvj max , iTM = ITAVM vRM = 100 V, vDM = , Zündverzug gate controlled delay time Freiwerdezeit circuit commutated turn-off time , demand Werte nach DIN IEC 747-6 (ohne vorrausgehende Kommutierung). / Values to DIN IEC 747-6 (without , after circuit commutated turn-off time, see parameters t q. 320 280 Qr 240 [µAs] 200 160 120 80 40 0


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2000 - thyristor fast

Abstract: No abstract text available
Text: (diT/dt)cr 200 A/µs T vj = Tvj max, tp = 10ms DIN IEC 747-6 f=50 Hz, iGM = 1 A diG/dt = 1 A , gate controlled delay time DIN IEC 747-6 vD = VDRM, vR = VRRM T vj = 25°C iGM = 1 A, diG/dt = 1 A/µs 1) Werte nach DIN IEC 747-6 (ohne vorausgehende Kommutierung). / Values to DIN IEC 747-6 , / Immediately after circuit commutated turn-off-time, see parameters tq. SZ-M / 12.10.98 , K.-A. Rüther A , Werte / Characteristic values Freiwerdezeit circuit commutatet turn-off time T vj = Tvj max


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2000 - Not Available

Abstract: No abstract text available
Text: (diT/dt)cr 200 A/µs T vj = Tvj max, tp = 10ms DIN IEC 747-6 f=50 Hz, iGM = 1 A diG/dt = 1 A , gate controlled delay time DIN IEC 747-6 vD = VDRM, vR = VRRM T vj = 25°C iGM = 1 A, diG/dt = 1 A/µs 1) Werte nach DIN IEC 747-6 (ohne vorausgehende Kommutierung). / Values to DIN IEC 747-6 , / Immediately after circuit commutated turn-off-time, see parameters tq. SZ-M / 12.10.98 , K.-A. Rüther A , Werte / Characteristic values Freiwerdezeit circuit commutatet turn-off time T vj = Tvj max


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2000 - Not Available

Abstract: No abstract text available
Text: with Chopper-IGBT TD B6HK 124 N 16 RR N B6 Elektrische Eigenschaften / Electrical , DIN IEC 747-6 Kritische Spannungssteilheit critical rate of rise of off-state voltage Tvj = Tvj , 80°C IC Periodischer Kollektor-Spitzenstrom repetitive peak collektor current t p = 1ms , Thyristor-Modul mit Chopper-IGBT Thyristor Module with Chopper-IGBT TD B6HK 124 N 16 RR N B6 , delay time Tvj = 25°C, iGM = 0,6A, diG/dt = 0,6A/µs Tvj = Tvj max DIN IEC 747-6


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