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BD7682FJ-LB BD7682FJ-LB ECAD Model ROHM Semiconductor Quasi-resonant type (low EMI) Control DC/DC converter IC for AC/DC Converter
BM2P139TF BM2P139TF ECAD Model ROHM Semiconductor 100kHz PWM DC/DC Converter IC with Built-in 650V MOSFET, Feedback Voltage=13V ,Package=SOP8
BM2P209TF BM2P209TF ECAD Model ROHM Semiconductor 100kHz PWM DC/DC Converter IC with Built-in 650V MOSFET, Feedback Voltage=20V ,Package=SOP8
BM2P189TF BM2P189TF ECAD Model ROHM Semiconductor 100kHz PWM DC/DC Converter IC with Built-in 650V MOSFET, Feedback Voltage=18V ,Package=SOP8
BM2P129TF BM2P129TF ECAD Model ROHM Semiconductor 100kHz PWM DC/DC Converter IC with Built-in 650V MOSFET, Feedback Voltage=12V ,Package=SOP8
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circuit diagram of MOD 64 counter Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
PMB2312

Abstract: circuit diagram of MOD 100 counter circuit diagram of MOD 64 counter smd 2312 siemens 2312 PMB 2312 smd code marking 3t1 IC KA 2312 marking 3t1 Wiring Diagram siemens
Text: /CMOS compatible MOD input • Standby Mode • Switchable divider ratios 64 /65 or 128/129 , the external network configuration, dividing ratios of 64 /65 or 128/129 can be selected. Type , Circuit Description The symmetrical differential inputs of the IC may be connected asymmetrically. In , : 64 /65 or 1 : 128/129. The MOD input determines whether modulus 1 : n or 1 : n + 1 (n = 64 or 128 , Function SW high = 3.0 to Vs 1 : 64 /65 low = GND to 0.8 V or open 1 : 128/129 MOD high = 2.0 V to Fs or


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PDF PMB2312 Q67000-A6039 23SLDS a23Sb05 35x45' fl235L PMB2312 circuit diagram of MOD 100 counter circuit diagram of MOD 64 counter smd 2312 siemens 2312 PMB 2312 smd code marking 3t1 IC KA 2312 marking 3t1 Wiring Diagram siemens
1999 - circuit diagram of MOD 64 counter

Abstract: STB 6-pin
Text: divide ratio of the ECL-stages is fixed to 1: 64 /65 or 1:128/129. The MOD input determines whether , ; exceeding only one of these values may cause irreversible damage to the integrated circuit . &KDUDFWHULVWLFV The listed characteristics are ensured over the operating range of the integrated circuit , ratio is 1: 64 /65 or 1:128/129 depending on the external circuit configuration. Semiconductor Group , GND modulus 1:n/n+1 (n= 64 or 128) control input ( MOD ) standby mode control input (STB) RF-input I2


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PDF 2314T circuit diagram of MOD 64 counter STB 6-pin
2011 - pulse doppler radar

Abstract: 06333 4 bit mod 16 d flip-flop VCO190-1843T d0945 circuit diagram of MOD 64 counter
Text: with the 64 identical 100 A charge pump cells active (for a total of 6.4 mA). When the ICP counter , the full truth table; see Figure 27 for a block diagram of the MUXOUT circuit . Rev. A | Page 13 of , ) (CONTROL BIT C1) t7 LE t1 LE t6 09450-002 Figure 2. Timing Diagram Rev. A | Page 4 of 28 , RF integrated circuit with an ESD rating of <2 kV, and it is ESD sensitive. Take proper precautions , MULTIPLE OF MOD REFERENCE CYCLES (5µs) FOR COHERENT PHASE MEASUREMENTS Figure 17. On Resistance of the


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PDF ADF4196 ADF4196 32-Lead GSM1800) CP-32-2 CP-32-2 EVAL-ADF4193EBZ1 pulse doppler radar 06333 4 bit mod 16 d flip-flop VCO190-1843T d0945 circuit diagram of MOD 64 counter
2011 - Not Available

Abstract: No abstract text available
Text: table; see Figure 27 for a block diagram of the MUXOUT circuit . Rev. C | Page 13 of 28 09450-021 , ) (CONTROL BIT C1) t7 LE t1 LE t6 09450-002 Figure 2. Timing Diagram Rev. C | Page 4 of 28 , RF integrated circuit with an ESD rating of <2 kV, and it is ESD sensitive. Take proper precautions , 09450-045 INTERVAL BETWEEN R0 WRITES SHOULD BE A MULTIPLE OF MOD REFERENCE CYCLES (5µs) FOR COHERENT , between the integer steps. RF N DIVIDER N = INT + FRAC/ MOD TO PFD N COUNTER FROM RF INPUT STAGE NC


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PDF ADF4196 ADF4196 MO-220-VHHD-2 32-Lead CP-32-2) ADF4196BCPZ ADF4196BCPZ-RL7 EV-ADF4196SD1Z
2005 - TDS714L

Abstract: 06333 how to test 7815
Text: Diagram Rev. A | Page 4 of 28 ADF4193 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted , . This device is a high performance RF integrated circuit with an ESD rating of <2 kV, and it is ESD , OSCILLOSCOPE 1880MHz R&S SMT03 SIG. GEN. INTERVAL BETWEEN R0 WRITES SHOULD BE A MULTIPLE OF MOD REFERENCE , N = INT + FRAC/ MOD TO PFD 100k TO R COUNTER Figure 20. Reference Input Stage R Counter and , the R counter to give a further divide-by-2. Using this option has the additional advantage of


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PDF ADF4193 ADF4193 lo32-Lead CP-32-3) ADF4193BCPZ1 ADF4193BCPZ-RL1 ADF4193BCPZ-RL71 EVAL-ADF4193EB1 EVAL-ADF4193EB2 32-Lead TDS714L 06333 how to test 7815
1998 - circuit diagram of MOD 64 counter

Abstract: B54102 smd 2312 pmb 400 - s UA 796 b631 transistor BFT92 pmb 400 s A1221 k5101
Text: ensured over the operating range of the integrated circuit . Typical characteristics specify mean values , applications. The divide ratio is 1: 64 /65 or 1:128/129 depending on the external circuit configuration. The , fixed to 1: 64 /65 or 1:128/129. The MOD input determines whether modulus 1:n or 1:n+1 (n= 64 or 128 , STB = GND µA 400 'HOD\ WLPHV MOD setup time Wset ( diagram 1) 29 ns AC /DC , see following diagram Due to the internal output current source of the PMB 2313, an external load


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PDF 2313T circuit diagram of MOD 64 counter B54102 smd 2312 pmb 400 - s UA 796 b631 transistor BFT92 pmb 400 s A1221 k5101
2003 - circuit diagram of MOD 64 counter

Abstract: PMB2314T VCO 2307 2314T
Text: the health of the user or other persons may be endangered. Prescaler Circuit 2.1 GHz Revision , 1: 64 /65 or 1:128/129 depending on the external circuit configuration. 1.2 Circuit Description , . Depending on the logic level at SW input the basic divide ratio of the ECL-stages is fixed to 1: 64 /65 or 1:128/129. The MOD input determines whether modulus 1:n or 1:n+1 (n= 64 or 128 according to SW-level) is , Prescaler function SW HIGH = US-0.1 V to US LOW = GND to 0.8 V or open 1: 64 /65 1:128/129 MOD


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PDF 2314T circuit diagram of MOD 64 counter PMB2314T VCO 2307 2314T
2011 - circuit diagram of MOD 64 counter

Abstract: a6069
Text: charge pump cells active (for a total of 6.4 mA). When the ICP counter times out, the charge pump , diagram of the MUXOUT circuit . The ADF4196 serial interface includes a 24-bit input shift register , Diagram Rev. B | Page 4 of 28 Data Sheet ADF4196 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless , performance RF integrated circuit with an ESD rating of <2 kV, and it is ESD sensitive. Take proper , 4 5 INTERVAL BETWEEN R0 WRITES SHOULD BE A MULTIPLE OF MOD REFERENCE CYCLES (5µs) FOR


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PDF ADF4196 ADF4196 CP-32-2) ADF4196BCPZ ADF4196BCPZ-RL7 EVAL-ADF4193EBZ1 EVAL-ADF4193EBZ2 32-Lead GSM1800) circuit diagram of MOD 64 counter a6069
2011 - Not Available

Abstract: No abstract text available
Text: charge pump cells active (for a total of 6.4 mA). When the ICP counter times out, the charge pump , diagram of the MUXOUT circuit . The ADF4196 serial interface includes a 24-bit input shift register , INTERVAL BETWEEN R0 WRITES SHOULD BE A MULTIPLE OF MOD REFERENCE CYCLES (5µs) FOR COHERENT PHASE , after the R counter to provide an additional divide-by-2. Using this option has the added advantage of , VCO frequency (RFOUT), is composed of an integer part (INT) and a fractional part (FRAC/ MOD ). RFOUT


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PDF ADF4196 ADF4196 CP-32-2) ADF4196BCPZ ADF4196BCPZ-RL7 EVAL-ADF4193EBZ1 EVAL-ADF4193EBZ2 32-Lead GSM1800)
2005 - "FRACTIONAL INTERPOLATOR"

Abstract: APPLICATIONS OF mod 8 COUNTER bjt differential amplifier application circuits circuit diagram of MOD 64 counter Transistor based fm modulator ct icp multiplexer 24 pin modulator 26MHz VCO190-1843T ADF4193 DCS1800
Text: ) (CONTROL BIT C1) t7 LE t1 t6 05238-002 LE Figure 2. Timing Diagram Rev. 0 | Page 5 of , 5 INTERVAL BETWEEN R0 WRITES SHOULD BE A MULTIPLE OF MOD REFERENCE CYCLES (5µs) FOR COHERENT , to generate the CML clock levels needed MOD REG FRAC VALUE 05328-018 R Counter and , charge pump cells active ( 6.4 mA total). When the ICP counter times out, the charge pump current is , is the job of the SW1, SW2, and SW3 switches. The application circuit shown in Figure 36 shows how


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PDF ADF4193 ADF4193 ADF4193BCPZ1 ADF4193BCPZ-RL1 ADF4193BCPZ-RL71 EVAL-ADF4193EB1 EVAL-ADF4193EB2 32-Lead "FRACTIONAL INTERPOLATOR" APPLICATIONS OF mod 8 COUNTER bjt differential amplifier application circuits circuit diagram of MOD 64 counter Transistor based fm modulator ct icp multiplexer 24 pin modulator 26MHz VCO190-1843T DCS1800
CXA1541M

Abstract: QFP Package 128 lead .5mm QFP 128 lead .5mm 100MIL circuit diagram of MOD 64 counter
Text: ÔHS - 278 SONY CXA1S41M Description of Operation SW MOD Divider H H 64 L 65 L H 128 L 129 , operating frequency provided at 1.1 GHz • Selection of 64 /65 and 128/129 frequency dividers Applications , MOD (Open "L") 7 I NC Switchover for the divider value (Refer to the Description of Operation) No , divider values-between 64 and 65 or between 128 and 129. This MOD pin should be connected to the modulus , by one at the "High" to "Low" falling edge of the 1 st period. SONY CXA1541M Application Circuit


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PDF CXA1541M CXA1541M 50MIL) 127mm QFP Package 128 lead .5mm QFP 128 lead .5mm 100MIL circuit diagram of MOD 64 counter
2005 - TDS714L

Abstract: ADF4193 DCS1800 GSM900 FRACTIONAL INTERPOLATOR Transistor based fm modulator ct C 1859
Text: device is a high performance RF integrated circuit with an ESD rating of <2 kV, and it is ESD sensitive , MOD 100 90 39 5 INTERVAL BETWEEN R0 WRITES SHOULD BE A MULTIPLE OF MOD REFERENCE CYCLES , COUNTER THIRD-ORDER FRACTIONAL INTERPOLATOR INT REG MOD REG FRAC VALUE 05328-018 R Counter and Doubler N = INT + FRAC/ MOD Figure 22. Fractional-N Divider INT, FRAC, and MOD , of an integer part (INT) and a fractional part (FRAC/ MOD ): RFOUT = FPFD × [INT + (FRAC/ MOD )] where


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PDF ADF4193 ADF4193 D05328-0-1/11 TDS714L DCS1800 GSM900 FRACTIONAL INTERPOLATOR Transistor based fm modulator ct C 1859
2006 - TDS714L

Abstract: modulator 26MHz AD8302 spur spur free fractional PLL pong VCO190-1843T ADF4193 DCS1800 GSM900 TRANSISTOR SDM M6
Text: value of MOD . Setting this bit to 1 inserts a divide-by-2, toggle flip-flop between the R counter , min Figure 2. Timing Diagram Rev. B | Page 4 of 28 ADF4193 ABSOLUTE MAXIMUM RATINGS TA = , performance RF integrated circuit with an ESD rating of <2 kV, and it is ESD sensitive. Proper precautions , MULTIPLE OF MOD REFERENCE CYCLES (5µs) FOR COHERENT PHASE MEASUREMENTS DRAIN VOLTAGE (V) Figure 19 , REG MOD REG FRAC VALUE 05328-018 R Counter and Doubler N = INT + FRAC/ MOD Figure 22


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PDF ADF4193 ADF4193 CP-32-3) ADF4193BCPZ ADF4193BCPZ-RL1 ADF4193BCPZ-RL71 EVAL-ADF4193EB1 EVAL-ADF4193EB2 32-Lead TDS714L modulator 26MHz AD8302 spur spur free fractional PLL pong VCO190-1843T DCS1800 GSM900 TRANSISTOR SDM M6
2005 - Not Available

Abstract: No abstract text available
Text: 05238-002 Figure 2. Timing Diagram Rev. E | Page 4 of 28 Data Sheet ABSOLUTE MAXIMUM RATINGS TA = , MULTIPLE OF MOD REFERENCE CYCLES (5µs) FOR COHERENT PHASE MEASUREMENTS Figure 17. On Resistance of Loop , INPUT STAGE N COUNTER THIRD-ORDER FRACTIONAL INTERPOLATOR N = INT + FRAC/ MOD TO PFD NC S2 REFIN NC , ADF4193 The value of MOD is chosen to give the desired channel step with the available reference , pump is made up of an array of 64 identical cells, each of which is fully differential. All 64 cells


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PDF ADF4193 ADF4193 D05328-0-2/13
2005 - phase detector AD8302

Abstract: No abstract text available
Text: 05238-002 Figure 2. Timing Diagram Rev. F | Page 4 of 32 Data Sheet ABSOLUTE MAXIMUM RATINGS TA = , MULTIPLE OF MOD REFERENCE CYCLES (5µs) FOR COHERENT PHASE MEASUREMENTS Figure 17. On Resistance of Loop , INPUT STAGE N COUNTER THIRD-ORDER FRACTIONAL INTERPOLATOR N = INT + FRAC/ MOD TO PFD NC S2 REFIN NC , ADF4193 The value of MOD is chosen to give the desired channel step with the available reference , pump is made up of an array of 64 identical cells, each of which is fully differential. All 64 cells


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PDF ADF4193 ADF4193 D05328-0-3/13 phase detector AD8302
2005 - 4 bit mod 16 d flip-flop

Abstract: Transistor based fm modulator ct adsp 21xx processor
Text: 05238-002 Figure 2. Timing Diagram Rev. D | Page 4 of 28 Data Sheet ABSOLUTE MAXIMUM RATINGS TA = , MULTIPLE OF MOD REFERENCE CYCLES (5µs) FOR COHERENT PHASE MEASUREMENTS Figure 17. On Resistance of Loop , INPUT STAGE N COUNTER THIRD-ORDER FRACTIONAL INTERPOLATOR N = INT + FRAC/ MOD TO PFD NC S2 REFIN NC , ADF4193 The value of MOD is chosen to give the desired channel step with the available reference , charge pump is made up of an array of 64 identical cells, each of which is fully differential. All 64


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PDF ADF4193 ADF4193 D05328-0-3/12 4 bit mod 16 d flip-flop Transistor based fm modulator ct adsp 21xx processor
2005 - Not Available

Abstract: No abstract text available
Text: device reliability. This device is a high performance RF integrated circuit with an ESD rating of <2 kV , ) INTERVAL BETWEEN R0 WRITES SHOULD BE A MULTIPLE OF MOD REFERENCE CYCLES (5µs) FOR COHERENT PHASE , Input Stage RF N DIVIDER N = INT + FRAC/ MOD FROM RF INPUT STAGE R Counter and Doubler TO , of an integer part (INT) and a fractional part (FRAC/ MOD ): RFOUT = FPFD × [INT + (FRAC/ MOD , pump is made up of an array of 64 identical cells, each of which is fully differential. All 64 cells


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PDF ADF4193 ADF4193 D05328-0-3/12
2012 - ADF4351

Abstract: ADuC70xx
Text: N COUNTER MULTIPLEXER CE AGND OUTPUT STAGE ÷1/2/4/8/16/ 32/ 64 DGND CPGND , t1 09800-002 t6 LE Figure 2. Timing Diagram Rev. 0 | Page 5 of 28 ADF4351 Data , , EVM = 0.61% Rev. 0 | Page 10 of 28 Data Sheet ADF4351 CIRCUIT DESCRIPTION REFERENCE INPUT , is a simplified schematic of the phase frequency detector. TO PFD N COUNTER THIRD-ORDER , )] DELAY Figure 17. RF N Divider U3 CHARGE PUMP CPOUT INT, FRAC, MOD , and R Counter


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PDF ADF4351 divide-by-1/-2/-4/-8/-16/-32/-64 ADF4351 externa20-VHHD-2 3-28-2012-A 32-Lead CP-32-2) ADF4351BCPZ ADF4351BCPZ-RL7 EVAL-ADF4351EB1Z ADuC70xx
1994 - Not Available

Abstract: No abstract text available
Text: dual modulus operation. In dual modulus mode, MOD remains low during operation of the A counter until , MOD output, which is used to select the division ratio of the prescaler. When the A counter is non-zero, the MOD output is low and goes high when the A counter has counted down to zero. MOD remains , ) Fig.2 Simplified block diagram of NJ88C33 NJ88C33 PIN DESIGNATIONS Pin No. Pin Name 1 , microprocessor, the proximity of the synthesiser loop to lock can be evaluated. The A counter is not used in


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PDF DS2429 NJ88C33 NJ88C33 16-bit 12-bit
2003 - B54102

Abstract: B37940-K5330-J62 B37950-K5104-K62 PMB 2304T circuit diagram of MOD 64 counter 2313T 2306T b631 transistor pmb 400 s BFT92
Text: Modulus Set-Up Time Diagram 1 I MOD tset Q Changes of the mod-level made up to , the health of the user or other persons may be endangered. Prescaler Circuit 1.1 GHz Draft Copy , : 64 /65 or 1:128/129. The MOD input determines whether modulus 1:n or 1:n+1 (n= 64 or 128 according to , /129 MOD HIGH = 2.0 V to US or open LOW = GND to 0.8 V 1: 64 /1:128 1:65/1:129 STB HIGH , :128/129 control input (SW) output Q GND modulus 1:n/n+1 (n= 64 or 128) control input ( MOD ) standby


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PDF charts-J60 B54102-A1332-J60 B54102-A1472-J60 B54102-A1682-J60 B54102-A1822-J60 B54102-A1183-J60 B54102-A1223-J60 B54102-A1393-J60 B82412-A3220-M B37940-K5220-J62 B54102 B37940-K5330-J62 B37950-K5104-K62 PMB 2304T circuit diagram of MOD 64 counter 2313T 2306T b631 transistor pmb 400 s BFT92
2012 - F6C30

Abstract: adf4351 4093 oscillator ADF4351BCPZ ADuC70xx frequency synthesizer for LTE Applications EVAL-ADF4351EB1Z DECT base station schematic CATV Wideband Transformer Splitter ep core _type transformer
Text: VALUE THIRD-ORDER FRACTIONAL INTERPOLATOR ÷1/2/4/8/16/ 32/ 64 OUTPUT STAGE N COUNTER , ) (CONTROL BIT C1) t7 LE t1 LE t6 09800-002 Figure 2. Timing Diagram Rev. 0 | Page 5 of 28 , integrated circuit with an ESD rating of <1.5 kV and is ESD sensitive. Proper precautions should be taken for , 0.35°, RMS Jitter = 0.36 ps, EVM = 0.61% Rev. 0 | Page 10 of 28 Data Sheet CIRCUIT DESCRIPTION , (0 or 1). R is the preset divide ratio of the binary 10-bit programmable reference counter (1 to 1023


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PDF divide-by-1/-2/-4/-8/-16/-32/-64 ADF4351 ADF4351 MO-220-VHHD-2 32-Lead CP-32-2) ADF4351BCPZ ADF4351BCPZ-RL7 EVAL-ADF4351EB1Z F6C30 4093 oscillator ADuC70xx frequency synthesizer for LTE Applications EVAL-ADF4351EB1Z DECT base station schematic CATV Wideband Transformer Splitter ep core _type transformer
KS57C5016

Abstract: P30C NTE100
Text: variety of applications, especially in the field of telecommunications. Up to 55 pins of the 64 -pin SDIP , Subsystem clock frequency: 32.768 kHz (typical) CPU clock divider circuit (by 4, 8, or 64 ) 55 I/O Pins , . Figure 16. Interrupt Control Circuit Diagram Septem ber 1996 11-14 ELECTRONICS PRODUCT , sampling clock rate of fxx/ 64 is used for INTO, an interrupt request flag must be cleared before 16 machine , .1 IMODO.O Effect of IMODO Settings Select CPU clock for sampling Select fx/ 64 sampling clock Rising edge


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PDF KS57C5016 64-pin DG3b203 64-QFP-1420B 64-QFP-1420F 003b27fl P30C NTE100
2012 - ADF4351

Abstract: LTE filter band 13 BS4 DECT
Text: Figure 2. Timing Diagram Rev. Pr D | Page 5 of 28 ADF4351 ABSOLUTE MAXIMUM RATINGS TA = 25 , ps, EVM = 0.86%. Rev. Pr D | Page 10 of 28 Preliminary Technical Data CIRCUIT DESCRIPTION , DIVIDERS N = INT + FRAC/ MOD TO PFD N COUNTER THIRD-ORDER FRACTIONAL INTERPOLATOR INT REG MOD , is determined by INT, FRAC and MOD values, which build up this divider. R COUNTER The 10­bit R , the PFD. Division ratios from 1 to 1023 are allowed. INT, FRAC, MOD , AND R COUNTER RELATIONSHIP


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PDF ADF4351 divide-by-1/-2/-4/-8/-16/-32/-64 ADF4351 ADF4351BCPZ1 ADF4351BCPZ-RL71 EVAL-ADF4351EB1Z1 32-Lead 11708-A CP-32-2 LTE filter band 13 BS4 DECT
1995 - transistor A1011

Abstract: a1273 transistor scheme A1266 a1273 a1273 transistor DATA a1273 transistor a1232 transistor a1266 A1306 TRANSISTOR transistor A1267
Text: Simplified Functional Block Diagram of the 80C186 Family CPU .2-2 Physical , 's Manual 1995 Information in this document is provided solely to enable use of Intel products. Intel assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of Intel products except as provided in Intel's Terms and Conditions of Sale for such products. Intel Corporation makes no warranty for the use of its products and assumes no responsibility for any errors which


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PDF 80C186EC/80C188EC 82C59A Index-10 transistor A1011 a1273 transistor scheme A1266 a1273 a1273 transistor DATA a1273 transistor a1232 transistor a1266 A1306 TRANSISTOR transistor A1267
1995 - A1306 TRANSISTOR

Abstract: A1273 A1266 transistor a1266 a1273 transistor a1232 transistor A1267 transistor a1276 a1273 transistor scheme a1273 y transistor
Text: Simplified Functional Block Diagram of the 80C186 Family CPU .2-2 Physical , use of Intel products. Intel assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of Intel products except as provided in Intel's Terms and Conditions of Sale for such products. Intel Corporation makes no warranty for the use of its products and assumes no , or trademark of Intel Corporation. Intel Corporation and Intel's FASTPATH are not affiliated with


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PDF 80C186EC/80C188EC 82C59A Index-10 A1306 TRANSISTOR A1273 A1266 transistor a1266 a1273 transistor a1232 transistor A1267 transistor a1276 a1273 transistor scheme a1273 y transistor
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