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Top Results (6)

Part Manufacturer Description Datasheet Download Buy Part
LTC1393CGN#TR Linear Technology IC MULTIPLEXER DUAL 4X1 16SSOP
LTC1393CGN Linear Technology IC 4-CHANNEL, DIFFERENTIAL MULTIPLEXER, PDSO16, 0.150 INCH, PLASTIC, SSOP-16, Multiplexer or Switch
LTC1391IN Linear Technology IC 8-CHANNEL, SGL ENDED MULTIPLEXER, PDIP16, 0.300 INCH, PLASTIC, DIP-16, Multiplexer or Switch
LTC1391 Linear Technology IC 8-CHANNEL, SGL POLE SGL THROW SWITCH, Multiplexer or Switch
LTC222 Linear Technology IC 4-CHANNEL, SGL POLE SGL THROW SWITCH, Multiplexer or Switch
LTC1390 Linear Technology IC 8-CHANNEL, SGL POLE SGL THROW SWITCH, Multiplexer or Switch

circuit diagram of 16 multiplexer Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
2006 - Not Available

Abstract: No abstract text available
Text: Clock Multiplexer IDTTM / ICSTM 1 Revision 080305 ICS580-01 Integrated Circuit Systems, Inc , Multiplexer Device Operation The ICS580-01 consists of a glitch free mux between INA and INB controlled by , circuit diagram in Figure 3 shows a typical connection for this example. Note that CLK2 and NO_INB are , °C/W °C/W Thermal Resistance Junction to Case Marking Diagram (ICS580M-01) 16 9 Marking Diagram (ICS580M-01LF) 16 9 ICS580M-01 ###### YYWW 1 8 1 580M01LF ###### YYWW 8 Marking


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PDF ICS580-01 ICS580-01 16-pin 199707558G
2006 - ICS557G08

Abstract: ICS557G-08LF ICS55708
Text: PCI-EXPRESS Description The ICS557-08 is a 2:1 multiplexer chip that allows the user to select one of the , · · · Packaged in 16 -pin TSSOP Available in Pb (lead) free package Operating voltage of 3.3 V Low , Junction to Case Marking Diagram (ICS557G-08) 16 9 Marking Diagram (ICS557GI-08) 16 9 557G-08 ###### YYWW$$ 1 8 557GI-08 ###### YYWW$$ 1 8 Marking Diagram (ICS557G-08LF) 16 9 Marking Diagram (ICS557GI-08LF) 16 9 557G08LF ###### YYWW 1 8 1 557GI08L ###### YYWW 8 Notes: 1


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PDF ICS557-08 16-pin 199707558G ICS557G08 ICS557G-08LF ICS55708
2003 - 20-PIN

Abstract: ICS85357-11 ICS85357AG-11 ICS85357AG-11T
Text: Oscillator-to-3.3V LVPECL / ECL Multiplexer and HiPerClockSTM is a member of the HiPerClockSTM family of High , range of 10MHz to 25MHz. The oscillator circuit is optimized for parallel resonant mode, and will , /products/hiperclocks.html 1 REV. B JANUARY 16 , 2003 ICS85357-11 Integrated Circuit Systems , /products/hiperclocks.html 2 REV. B JANUARY 16 , 2003 ICS85357-11 Integrated Circuit Systems , /hiperclocks.html 3 REV. B JANUARY 16 , 2003 ICS85357-11 Integrated Circuit Systems, Inc. 4:1 OR 2:1


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PDF ICS85357-11 ICS85357-11 10MHz 25MHz signifiS85357-11 85357AG-11 20-PIN ICS85357AG-11 ICS85357AG-11T
1999 - Not Available

Abstract: No abstract text available
Text: ICS580-01 Glitch-Free Clock Multiplexer Device Operation The ICS580-01 consists of a glitch free mux , switches in the manner described in the first example. The circuit diagram in Figure 3 shows a typical , θJC Marking Diagram (ICS580M-01) 16 Marking Diagram (ICS580M-01LF) 16 9 580M01LF ###### YYWW ICS580M-01 ###### YYWW 1 1 8 Marking Diagram (ICS580M-01I) 16 8 Marking Diagram (ICS580M-01ILF) 16 9 9 580M01ILF ###### YYWW ICS580M-01I ###### YYWW 1 9 1


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PDF ICS580-01 ICS580-01 ICS581-01 ICS581-02. 16-pin
1999 - AIR FLOW DETECTOR CIRCUIT DIAGRAM

Abstract: ICS580M-01ILF ICS580-01 ICS580M-01 ICS580M-01I ICS580M-01T ICS581-01 ICS581-02
Text: INA. The output then switches in the manner described in the first example. The circuit diagram in , Ambient 3 m/s air flow 105 °C/W 58 °C/W JC Marking Diagram (ICS580M-01) 16 Marking Diagram (ICS580M-01LF) 16 9 580M01LF ###### YYWW ICS580M-01 ###### YYWW 1 1 8 Marking Diagram (ICS580M-01I) 16 8 Marking Diagram (ICS580M-01ILF) 16 9 9 580M01ILF , Multiplexer Package Outline and Package Dimensions ( 16 pin SOIC, 150 Mil. Narrow Body) Package dimensions


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PDF ICS580-01 ICS580-01 ICS581-01 ICS581-02. 16-pin AIR FLOW DETECTOR CIRCUIT DIAGRAM ICS580M-01ILF ICS580M-01 ICS580M-01I ICS580M-01T ICS581-02
2013 - Not Available

Abstract: No abstract text available
Text: circuit shown in Figure 1, the ADC and multiplexer are both triggered by the rising edge of CNV signal , multiplexer in the on state as a simple RC circuit with time constant of RON × CD. The time for switch to , Pre-Filter, Multiplexer , and AD8065 Input For the purposes of calculating settling time, the circuit can , all input channels provides 16 -bit performance. Circuit Evaluation Boards CN-0269 Circuit , Files Schematics, Layout Files, Bill of Materials The signal processing circuit combined with a


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PDF CN-0269 AD7984 18-Bit, AD8475 AD8065 ADG5208 com/CN0269. ADG5236 ADR444
2006 - wiring diagram for dual float switch level control

Abstract: a01L ICS85454-01 ICS85454AK-01 ICS85454AK-01LF ICS85454AK-01T MO-220
Text: ICS85454-01 Integrated Circuit Systems, Inc. DUAL 2:1/1:2 DIFFERENTIAL-TO-LVDS MULTIPLEXER GENERAL DESCRIPTION FEATURES The ICS85454-01 is a 2:1/1:2 Multiplexer and a member of the HiPerClockSTM family of high HiPerClockSTM performance clock solutions from ICS. The 2:1 Multiplexer allows , REV. B JUNE 16 , 2006 ICS85454-01 Integrated Circuit Systems, Inc. DUAL 2:1/1:2 , /products/hiperclocks.html 2 REV. B JUNE 16 , 2006 ICS85454-01 Integrated Circuit Systems, Inc


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PDF ICS85454-01 ICS85454-01 100Mbit 1000Mbit 85454AK-01 25min/1 25max. wiring diagram for dual float switch level control a01L ICS85454AK-01 ICS85454AK-01LF ICS85454AK-01T MO-220
2006 - wiring diagram for dual float switch level control

Abstract: a01L serdes Buffer 5A01 ICS85454-01 MO-220
Text: ICS85454-01 Integrated Circuit Systems, Inc. DUAL 2:1/1:2 DIFFERENTIAL-TO-LVDS MULTIPLEXER GENERAL DESCRIPTION FEATURES The ICS85454-01 is a 2:1/1:2 Multiplexer and a member of the HiPerClockSTM family of high HiPerClockSTM performance clock solutions from ICS. The 2:1 Multiplexer allows , ICS85454-01 Integrated Circuit Systems, Inc. DUAL 2:1/1:2 DIFFERENTIAL-TO-LVDS MULTIPLEXER , Measurement Information, "2.5V Output Load Test Circuit " diagram . TABLE 5. AC CHARACTERISTICS, VDD = 2.375V


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PDF ICS85454-01 ICS85454-01 100Mbit 1000Mbit 85454AK-01 25min/1 25max. wiring diagram for dual float switch level control a01L serdes Buffer 5A01 MO-220
2000 - F-153

Abstract: 74F153 MS-001 M16D M16A F153 74F153SJ 74F153SC 74F153PC N16E
Text: (non-inverted) form. In addition to multiplexer operation, the F153 can generate any two functions of three , 16 -Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow 74F153SJ M16D 16 , Inputs Inputs (a or b) The F153 is a dual 4-input multiplexer . It can select two bits of data from , (millimeters) unless otherwise noted 16 -Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 , for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the


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PDF 74F153 74F153SC 16-Lead MS-012, 74F153SJ 74F153PC F-153 74F153 MS-001 M16D M16A F153 74F153SJ 74F153SC 74F153PC N16E
1988 - 74ACT158

Abstract: 74ACT158MTC 74ACT158SC 74ACT158SJ M16A M16D MTC16
Text: % The ACT158 is a high-speed quad 2-input multiplexer . It selects four bits of data from two sources , 74ACT158SC M16A 16 -Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow , -Input Multiplexer April 2007 Truth Table The ACT158 quad 2-input multiplexer selects four bits of data , Logic Diagram Please note that this diagram is provided only for the understanding of logic , THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE


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PDF 74ACT158 ACT158 74ACT158SC 16-Lead MS-012, 74ACT158SJ 74ACT158MTC MTC16 74ACT158 74ACT158MTC 74ACT158SC 74ACT158SJ M16A M16D MTC16
2006 - 580M01LF

Abstract: 580M-01
Text: . The circuit diagram in Figure 3 shows a typical connection for this example. Note that CLK2 and NO_INB , -01 GLITCH-FREE CLOCK MULITPLEXER CLOCK MULTIPLEXER Thermal Characteristics ( 16 -pin SOIC) Parameter , Marking Diagram (ICS580M-01) 16 9 Marking Diagram (ICS580M-01LF) 16 9 ICS580M-01 ###### YYWW 1 8 580M01LF ###### YYWW 1 8 Marking Diagram (ICS580M-01I) 16 9 Marking Diagram (ICS580M-01ILF) 16 9 , Marking Diagram (ICS580G-01LF) 16 9 Marking Diagram (ICS580G-01ILF) 16 9 580G01LF ###### YYWW 1


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PDF ICS580-01 ICS581-01 ICS581-02. 16-pin 580M01LF 580M-01
1988 - 74AC253

Abstract: 74AC253PC 74AC253SC 74AC253SJ 74ACT253 74ACT253MTC 74ACT253SC 74ACT253SJ
Text: -input multiplexer with 3-STATE outputs. It can select two bits of data from four sources using common select , -Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 74AC253SJ M16D 16 , Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 74ACT253SJ M16D 16 -Lead Small Outline Package , , 74ACT253 Dual 4-Input Multiplexer with 3-STATE Outputs Logic Diagram Symbol VCC IIK Parameter , Dimensions are in millimeters unless otherwise noted. Figure 2. 16 -Lead Small Outline Integrated Circuit


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PDF 74AC253, 74ACT253 AC/ACT253 ACT253 74AC253SC 16-Lead 74ACT253 74AC253 74AC253PC 74AC253SC 74AC253SJ 74ACT253MTC 74ACT253SC 74ACT253SJ
2006 - Not Available

Abstract: No abstract text available
Text: . The circuit diagram in Figure 3 shows a typical connection for this example. Note that CLK2 and NO_INB , CLOCK MULITPLEXER CLOCK MULTIPLEXER Thermal Characteristics ( 16 -pin SOIC) Parameter Thermal , -01) 16 9 Marking Diagram (ICS580M-01LF) 16 9 ICS580M-01 ###### YYWW 1 8 580M01LF ###### YYWW 1 8 Marking Diagram (ICS580M-01I) 16 9 Marking Diagram (ICS580M-01ILF) 16 9 ICS580M , Diagram (ICS580G-01LF) 16 9 Marking Diagram (ICS580G-01ILF) 16 9 580G01LF ###### YYWW 1 Notes: 1


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PDF ICS580-01 ICS581-01 ICS581-02. 16-pin
2011 - china lcd tv schematic diagram

Abstract: diode marking NZ AZ4052M-G1 2 pins diode marking NZ AZ4052 ic 4040 21 inch Lcd tv circuit schematic diagram
Text: (Typically Ground). The AZ4052 is available in standard packages of SOIC- 16 and DIP- 16 . _ _ _ _ , Preliminary Datasheet Dual 4-channel Analog Multiplexer /Demultiplexer Pin Configuration M Package (SOIC- 16 , Functional Block Diagram AZ4052 Figure 3. Functional Block Diagram of AZ4052 Schematic Diagram (One Switch) Figure 4. Schematic Diagram of AZ4052 Oct. 2011 Rev. 1. 1 3 BCD Semiconductor Manufacturing , AZ4052 - AZ4052 Circuit Type Package M: SOIC- 16 P: DIP- 16 G1: Green TR: Tape & Reel Blank


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PDF AZ4052 china lcd tv schematic diagram diode marking NZ AZ4052M-G1 2 pins diode marking NZ ic 4040 21 inch Lcd tv circuit schematic diagram
2006 - ICS581-01

Abstract: ICS580-01 ICS580M-01 ICS580M-01I ICS580M-01ILF ICS581-02 580M-01
Text: CLOCK MULTIPLEXER Pin Assignment Timeout Selection SELB 1 16 DIV 2 15 3 14 , described in the first example. The circuit diagram in Figure 3 shows a typical connection for this example , MULTIPLEXER Thermal Characteristics ( 16 -pin SOIC) Parameter Symbol Conditions Min. Typ. Max , ° C/W 37 ° C/W JC Marking Diagram (ICS580M-01) 16 Marking Diagram (ICS580M-01LF) 16 , -01 REV K 092509 ICS580-01 GLITCH-FREE CLOCK MULITPLEXER CLOCK MULTIPLEXER Marking Diagram


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PDF ICS580-01 ICS580-01 ICS581-01 ICS581-02. 16-pin ICS580M-01 ICS580M-01I ICS580M-01ILF ICS581-02 580M-01
1989 - MC14042

Abstract: 538 NPN transistor 16X1 74HC1398 14514b video multiplexer circuit diagram TRANSISTOR 536 multiplexer 16x1 4 input video multiplexer DG540
Text: GND GX414 VIDEO OUT OUT X16 -VEE X4 Fig. 1 Circuit Diagram of the 16x1 Multiplexer , Fig. 3 Circuit Diagram of a DG-538 16x1 Multiplexer Fig. 2 Circuit Diagram of the DG-536 16x1 Multiplexer The MOS bilateral channels require buffering at their inputs in order to prevent the flow of , (5" by 4") Total parts count = 102 Fig. 4 Circuit Diagram of a DG-540 16x1 Multiplexer , needed with this circuit . The features of the Gennum solution are; No direct cost comparison has been


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PDF GX414 GX414 DG536 DG538 DG540 MC14042 538 NPN transistor 16X1 74HC1398 14514b video multiplexer circuit diagram TRANSISTOR 536 multiplexer 16x1 4 input video multiplexer DG540
2004 - Not Available

Abstract: No abstract text available
Text: /W °C/W Thermal Resistance Junction to Case Marking Diagram 16 9 Marking Diagram (Pb free , , Integrated Circuit Systems (ICS) assumes no responsibility for either its use or for the infringement of any , ICS557-08 2:1 MULTIPLEXER CHIP FOR PCI-EXPRESS Description The ICS557-08 is a 2:1 multiplexer chip that allows the user to select one of the two HCSL (Host Clock Signal Level) or LVDS input pairs and fan out to one pair of differential HCSL or LVDS outputs. This chip is suited especially for


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PDF ICS557-08 ICS557-08 16-pin
2014 - Not Available

Abstract: No abstract text available
Text: 16 -channel analog multiplexer /demultiplexer Fig 3. Logic diagram HEF4067B_Q100 Product , reserved. 8 of 17 HEF4067B-Q100 NXP Semiconductors 16 -channel analog multiplexer /demultiplexer , rights reserved. 13 of 17 HEF4067B-Q100 NXP Semiconductors 16 -channel analog multiplexer , HEF4067B-Q100 16 -channel analog multiplexer /demultiplexer Rev. 2 — 11 September 2014 Product data sheet 1. General description The HEF4067B-Q100 is a 16 -channel analog multiplexer


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PDF HEF4067B-Q100 16-channel HEF4067B-Q100
2006 - a01L

Abstract: wiring diagram for dual float switch level control
Text: Integrated Circuit Systems, Inc. ICS85454-01 DUAL 2:1/1:2 DIFFERENTIAL-TO-LVDS MULTIPLEXER , ICS85454-01 is a 2:1/1:2 Multiplexer and a member of the HiPerClockSTM family of high HiPerClockSTM performance clock solutions from ICS. The 2:1 Multiplexer allows one of 2 inputs to be selected onto one , DIAGRAM SELB PIN ASSIGNMENT SELA nQB VDD QB INA0 nINA0 QA0 1 nQA0 2 INB nINB 16 15 14 13 12 11 , Information, "2.5V Output Load Test Circuit " diagram . TABLE 5. AC CHARACTERISTICS, VDD = 2.375V TO 2.625V


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PDF ICS85454-01 250ps 550ps ICS85454-01 85454AK-01 a01L wiring diagram for dual float switch level control
1999 - F153

Abstract: 74F153 N16E MS-001 M16D M16A 74F153SJ 74F153SC 74F153PC two 81 multiplexer
Text: (noninverted) form. In addition to multiplexer operation, the F153 can generate any two functions of three , 16 -Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow 74F153SJ M16D 16 , Inputs (a or b) The F153 is a dual 4-input multiplexer . It can select two bits of data from up to four sources under the control of the common Select inputs (S0, S1). The two 4-input multiplexer , otherwise noted 16 -Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow Package


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PDF 74F153 74F153SC 16-Lead MS-012, 74F153SJ 74F153PC F153 74F153 N16E MS-001 M16D M16A 74F153SJ 74F153SC 74F153PC two 81 multiplexer
2004 - Not Available

Abstract: No abstract text available
Text: multiplexer chip that allows the user to select one of the two HCSL (Host Clock Signal Level) or LVDS input , ICS557-08 2:1 Multiplexer Chip for PCI-Express Pin Assignment Select Table VDD 1 16 , output clock . 15 CLK Output 16 SEL Input 2 MDS 557-08 B In te grated Circuit , Resistance Junction to Case θJC 20 °C/W Marking Diagram Marking Diagram (Pb free) 16 9 , :1 Multiplexer Chip for PCI-Express Package Outline and Package Dimensions ( 16 -pin TSSOP, 173 Mil


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PDF ICS557-08 ICS557-08 16-pin
2000 - 74F257A

Abstract: 74F257APC 74F257ASC 74F257ASJ M16A M16D MS-001 N16E
Text: Description Features The 74F257A is a quad 2-input multiplexer with 3-STATE outputs. Four bits of data , Number Package Description 74F257ASC M16A 16 -Lead Small Outline Integrated Circuit (SOIC , Select The 74F257A is a quad 2-input multiplexer with 3-STATE outputs. It selects four bits of data , diagram is provided only for the understanding of logic operations and should not be used to estimate , (millimeters) unless otherwise noted 16 -Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150


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PDF 74F257A 74F257A 74F257ASCTHOUT 74F257APC 74F257ASC 74F257ASJ M16A M16D MS-001 N16E
1999 - 74F257A

Abstract: 74F257APC 74F257ASC 74F257ASJ M16A M16D MS-001 N16E
Text: Features The 74F257A is a quad 2-input multiplexer with 3-STATE outputs. Four bits of data from two , Description 74F257ASC M16A 16 -Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 , 74F257A is a quad 2-input multiplexer with 3-STATE outputs. It selects four bits of data from two sources , Physical Dimensions inches (millimeters) unless otherwise noted 16 -Lead Small Outline Integrated Circuit , Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses


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PDF 74F257A 74F257A 74F257ASC 74F257APC 74F257ASC 74F257ASJ M16A M16D MS-001 N16E
2013 - Not Available

Abstract: No abstract text available
Text: of ports that support universal port multiplexer (UPMUX) Timers Watchdog timer (WDT) Real-time , /rest) Tempo: 16 tempos (30 to 480) Tie may be specified. IR remote controller (REMC) Number of , port 16 -bit PWM timer Ch.1 event counter input 0 User-selected I/O (universal port multiplexer ) LCD , /O (universal port multiplexer ) LCD segment output LCD COMMON OUTPUT I/O port 16 -bit PWM timer Ch , circuit input I/O port 16 -bit PWM timer Ch.0 event counter input 1 OSC3 oscillator circuit output LCD


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PDF S1C17W22/23 16-bit S1C17W22/W23
2013 - Not Available

Abstract: No abstract text available
Text: of ports that support universal port multiplexer (UPMUX) Timers Watchdog timer (WDT) Real-time , : 16 tempos (30 to 480) Tie may be specified. IR remote controller (REMC) Number of transmitter â , (universal port multiplexer ) LCD segment output LCD COMMON OUTPUT I/O port 16 -bit PWM timer Ch.1 event , .0 event counter input 0 OSC3 oscillator circuit input I/O port 16 -bit PWM timer Ch.0 event counter , circuit Synchronous serial interface (SPIA) I2C (I2C) UART (UART) 16 -bit PWM timer (T16B


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PDF S1C17W22/23 16-bit S1C17W22/W23
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