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Top Results (6)

Part Manufacturer Description Datasheet Download Buy Part
LTC3730CG Linear Technology LTC3730 - 3-Phase, 5-Bit Intel Mobile VID, 600kHz, Synchronous Buck Controller; Package: SSOP; Pins: 24; Temperature Range: 0°C to 70°C
LTC3738CUHF Linear Technology LTC3738 - 3-Phase Buck Controller for Intel VRM9/VRM10 with Active Voltage Positioning; Package: QFN; Pins: 38; Temperature Range: 0°C to 70°C
LTC3730CG#TR Linear Technology LTC3730 - 3-Phase, 5-Bit Intel Mobile VID, 600kHz, Synchronous Buck Controller; Package: SSOP; Pins: 24; Temperature Range: 0°C to 70°C
LTC3738CUHF#TR Linear Technology LTC3738 - 3-Phase Buck Controller for Intel VRM9/VRM10 with Active Voltage Positioning; Package: QFN; Pins: 38; Temperature Range: 0°C to 70°C
LTC3730CG#PBF Linear Technology LTC3730 - 3-Phase, 5-Bit Intel Mobile VID, 600kHz, Synchronous Buck Controller; Package: SSOP; Pins: 24; Temperature Range: 0°C to 70°C
LTC3738CUHF#PBF Linear Technology LTC3738 - 3-Phase Buck Controller for Intel VRM9/VRM10 with Active Voltage Positioning; Package: QFN; Pins: 38; Temperature Range: 0°C to 70°C

cache controller intel 82496 Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
ma6351

Abstract: LE-24T ZO 607MA EM 5135 diode A82496 290446 ZD6A RapidCAD 522110 jp 241429
Text: : 82496 Cache Controller and 82491 Cache SRAM Data Book PentiumTM Processor User's Manual NOTE: The , 241428; the 82496 Cache Controller and 82491 Cache SRAM Data Book, Order Number 241429; and the , 8K Data Caches - See PentiumTM Processor Data Book for more information The 82496 Cache Controller , critical applications. The 82496 cache controller implements the MESI write-back protocol for full , .1-1 . 1-1 1.1.1. PentiumTM Processor Pinouts 1.1.2. 82496 Cache Controller Pinouts


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PDF 4fl2bl75 ma6351 LE-24T ZO 607MA EM 5135 diode A82496 290446 ZD6A RapidCAD 522110 jp 241429
1996 - t187

Abstract: BGT Q 900 A18 OE T10 cache controller intel 82496 82497 intel 82496 apic s09 82489dx 290446 82496 CDB22
Text: 1-800-879-4683 COPYRIGHT © INTEL CORPORATION 1996 E 82496 CACHE CONTROLLER AND 82491 CACHE SRAM FOR USE , D Pentium® Processor Family Developer's Manual Volume 2: 82496 /82497/82498 Cache Controller , of three books: Pentium® Processor Order Number 241428; the 82496 /82497/82498 Cache Controller and , , Write-Allocation and Cache-toCache Transfers - The 82496 Cache Controller and multiple 82491 Cache SRAMs , . The 82496 cache controller implements the MESI write-back protocol for full multiprocessing support


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PDF Intel486TM 1-55512-237-X 1-55512-240-X t187 BGT Q 900 A18 OE T10 cache controller intel 82496 82497 intel 82496 apic s09 82489dx 290446 82496 CDB22
1996 - NEC 2532

Abstract: cache controller intel 82496 Voltage Doubler with 555 circuit ICS2686 AP-453 intel 82496 82491 TTL 7400 national semiconductor 241563 IC 7418
Text: processor with 256K second-level cache subsystem using the 82496 Cache Controller and the 82491 Cache SRAMs are provided The Pentium processor 82496 Cache Controller and 82491 Cache SRAM form a CPU-Cache core , 82496 Cache Controller and 82491 Cache SRAM the CPUCache chip set must be synchronized with minimal , 256K 82496 82491 SECOND LEVEL CACHE CLOCK DISTRIBUTION DESIGN EXAMPLES 5 1 Clock Routing for the , 82496 82491 SECOND LEVEL CACHE CLOCK DISTRIBUTION ISSUES 11 12 12 16 16 16 22 32 7 0


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PDF AP-479 NEC 2532 cache controller intel 82496 Voltage Doubler with 555 circuit ICS2686 AP-453 intel 82496 82491 TTL 7400 national semiconductor 241563 IC 7418
Intel Pentium 66MHz 1993

Abstract: No abstract text available
Text: will be a fully synchronous 66-MHz system with a 256k second-level cache . It will use the Intel 82496 Cache Controller and 82491 Cache SRAMs. This configuration em bodies many of the most challenging , Data Book, 1993. 7. Intel Corporation, Pentium Processor User's Manual - Volume 2: 82496 Cache Controller and 82491 Cache SRAM Data Book, 1993. 8. Lin, Derrick, and Jim Reilly, Pentium Proces sor Clock , jitter between the clock signals driv ing the cache controller and the Pentium must be less than 200 psec


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PDF SC3508 66-MHz 64-bit AP-479, 50-MHz Intel486 AP-453, CA92121 Intel Pentium 66MHz 1993
0249t

Abstract: Intel Pentium 66MHz 1993
Text: second-level cache . It will use the Intel 82496 Cache Controller and 82491 Cache SRAMs. This configuration em , Processor Data Book, 1993. 7. Intel Corporation, Pentium Processor User's Manual - Volume 2: 82496 Cache Controller and 82491 Cache SRAM Data Book, 1993. 8. Lin, Derrick, and Jim Reilly, Pentium Proces sor Clock , jitter between the clock signals driv ing the cache controller and the Pentium must be less than 200 psec , jO C lock D esign in Intel Pentium TM P rocessor System s using the SC3508 M.K. Williams Owner


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PDF SC3508 SC3508. 0249t Intel Pentium 66MHz 1993
apic s09

Abstract: LR1 D09 intel 82496 82496 D4321
Text: PINOUTS 1-2 I intei 1.1.2. U PINOUTS 82496 Cache Controller Pinouts T V» S APERRI R Q p , 1-3. 82496 Cache Controller Pinout (Top View) 1-3 PINOUTS intei A B c D E F G H J K L M N P , S01 T01 U01 W06 W07 1-8 PINOUTS 1.2.2. 82496 Cache Controller Table 1-2. 82496 Cache , Q03 T02 C18 M16 L15 N15 P16 N16 M15 1-9 PINOUTS Table 1-2. 82496 Cache Controller Pin Cross , I PINOUTS Table 1-2. 82496 Cache Controller Pin Cross Reference by Pin Name (Contd.) w


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PDF D82496 apic s09 LR1 D09 intel 82496 82496 D4321
SC35D

Abstract: No abstract text available
Text: will use the Intel 82496 Cache Controller and 82491 Cache SRAMs. This configuration em bodies many of , Corporation, Pentium Processor User's Manual - Volume 2: 82496 Cache Controller and 82491 Cache SRAM Data Book , and the jitter between the clock signals driv ing the cache controller and the Pentium must be less , >4M C C Clock Design In Intel PentiumTM Processor Systems using the SC3508 M.K. Williams Owner , , high-perfor mance entry In the X86 microprocessor family from Intel . There are 60- and 66-MHz versions. It


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PDF SC3508 66-MHz 64-bit SC35D
ZD6A

Abstract: t177 ZR7a cache controller intel 82496
Text: distribution, the Pentium processor has 50 Vc c (power) and 49 Vss (ground) inputs. The 82496 Cache Controller , the Pentium processor, 82496 Cache Controller , and 82491 Cache SRAM. On the circuit board, all V cc , 82496 Cache Controller /82491 Cache SRAM second level cache . The CPU Cache Chip Set driving its large , , CC= 82496 Cache Controller , CS=82491 Cache SRAM Vcc = See Notes 16,17, T case - See Notes 18,19 Symbol , clocks only require approximately 75 mA) (4) Typical 82496 Cache Controller Supply current is 800 mA at


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PDF Controller/82491 ZD6A t177 ZR7a cache controller intel 82496
241814

Abstract: pentium 1993 PentiumTM multiprocessing
Text: intei 82496 CACHE CONTROLLER AND 82491 CACHE SRAM FOR USE WITH THE PentiumTM PROCESSOR High Performance Second Level Cache - Zero Wait States at 66 MHz - Two-way Set Associative - Write-Back with , , and Cache-to-Cache Transfers The 82496 Cache Controller and multiple 82491 Cache SRAMs combine with , , and has new data integrity features for mission critical applications. The 82496 cache controller , allow the 82496 to concurrently handle CPU bus, memory bus, and internal cache operation for maximum


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PDF 128-Bit 241814 pentium 1993 PentiumTM multiprocessing
pentium ii overdrive

Abstract: intel fan pinout processor pentium 2 cache controller intel 82496
Text: 82496 Cache Controller and 82491 Cache SRAM chip set. 1.2 Intel Verification Program The Intel , familiar to the millions of end users and dealers who have purchased Intel Math Coprocessor upgrades to , purchased Intel math coprocessor upgrades to boost system floating point performance. The majority of , from Intel 's Math Coprocessor upgrade customers highlights three main character istics of end user easy , of insertion force The Future Pentium OverDrive processor will support the Intel 82430 PCIset. Unlike


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PDF 510X60, 567X66) pentium ii overdrive intel fan pinout processor pentium 2 cache controller intel 82496
ZD6A

Abstract: TAG03 82497 3 PP 03 L 04 14-3-221 cfa24 cache controller intel 82496 zd-5a
Text: V (3) (4) NOTES: 1. 2. 3. 4. Applies to 82497 Cache Controller and 82492 Cache SRAM inputs , (all 82497 Cache Controller and 82492 Cache SRAM signals), 5VT buffers (Pentium processor (735\90, 815 , , 815U 00, 1000U 20, 1 110U 33) signals). Both the 82497 Cache Controller and 82492 Cache SRAM require a 3.3V and 5V supply. The 82497 Cache Controller and 82492 Cache SRAM are 5V com ponents and require 3.3V , , 1110U 33). The 82497 Cache Controller and 82492 Cache SRAM are 5V parts internally, with som e 3.3V I/O


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PDF
1996 - pentium processor block diagram

Abstract: 241430 4558n BT 815 transistor 241429 82430fx pentium system software writers manual 2202m 82430F Pentium A80501-60
Text: 241428; the 82496 /82497/82498 Cache Controller and 82491/82492/82493 Cache SRAM, Order Number 241429 , with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel 's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to


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PDF lia31-0 Intel486TM 1-55512-237-X 1-55512-240-X pentium processor block diagram 241430 4558n BT 815 transistor 241429 82430fx pentium system software writers manual 2202m 82430F Pentium A80501-60
OPTi chipset 486

Abstract: 82C496 opti 82c496 82C497 opti 486 chipset opti 82c206 block interleave 82497 opti isa vl 82C206
Text: Back cache controller with one level write buffer that is an optional part of the DXBB ( Building Block , adaptor. For cache based systems the 82C497 (the cache controller ) sits between the CPU and the 82C496 and , line size. The cache controller can support cache sizes from 32K to 512K with a cacheable address range , accessed cache line is specified as a dirty line. 3. Cache read miss (not dirty) The cache controller does , ) while the local bus cache line fill is going on. 4. Cache read miss (dirty) The cache controller updates


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PDF 82C497 82C497) QFPl60-P-2828 160-Pin OPTi chipset 486 82C496 opti 82c496 opti 486 chipset opti 82c206 block interleave 82497 opti isa vl 82C206
1996 - wt 633-12

Abstract: PC motherboard intel i7 schematic diagram 2013 intel pentium 80501 host pc recover target dead motherboard bios 20-pin debug header A20-A3 5081M 2032M ATIC 112 pentium processor block diagram T42A
Text: 241428; the 82496 /82497/82498 Cache Controller and 82491/82492/82493 Cache SRAM, Order Number 241429 , with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel 's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to


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PDF lia31-0 Intel486TM 1-55512-237-X 1-55512-240-X wt 633-12 PC motherboard intel i7 schematic diagram 2013 intel pentium 80501 host pc recover target dead motherboard bios 20-pin debug header A20-A3 5081M 2032M ATIC 112 pentium processor block diagram T42A
241595

Abstract: ds2 lio board Intel486TM PROCESSOR FAMILY BT320
Text: buffers of the processor for use with the 82496 Cache Controller /82491 Cache SRAM sec ondary cache as a chip set (refer to the 82496 Cache C ontroller/82491 Cache SRAM Data Book fo r Use with the Pentium tm , , 8K Write Back Data - 2-Way 32-Byte Line Size - Software Transparent - MESI Cache Consistency , Support - Multiprocessor Instructions - Support for Second Level Cache Internal Error Detection - , level performance. Sepa rate code and data caches reduce cache conflicts while remaining software


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PDF 510X60 32-Bit 32-Byte 273-Pin 567X66) 241595 ds2 lio board Intel486TM PROCESSOR FAMILY BT320
matrix tv m21 service mode manual

Abstract: cache controller intel 82496 transistors bt a24 82496 hep 230
Text: PENTIUM® PROCESSOR (510\60, 567\66) intel The separate caches are shown, the code cache and data cache , Cache Controller /82491 Cache SRAM secondary cache as a chip set (refer to the Pentium® Processor Family , intel PENTIUM® PROCESSOR (510X60, 567X66) PENTIUM® PROCESSOR AT PENTIUM® PROCESSOR AT Binary , , 8K Write Back Data — 2-Way 32-Byte Line Size — Software Transparent — MESI Cache Consistency , €” Support for Second Level Cache ■Internal Error Detection — Functional Redundancy Checking — Built


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PDF 510X60, 567X66) 32-Bit 64-Bit 32-Byte 567X66 273-Pin matrix tv m21 service mode manual cache controller intel 82496 transistors bt a24 82496 hep 230
82801GB

Abstract: 82801JR 82801IR 82801IB intel G31 intel p43 82801gr p35 chipset Intel G33 express chipset intel g33
Text: Intel ® Pentium® Processor E5800 (2M Cache , 3.20 GHz, 800 MHz FSB) Menu Language: English , Intel ® Pentium® Processor E5800 (2M Cache , 3.20 GHz, 800 MHz FSB) Add to Compare Compare Now (0 , /2011 11:55:11 AM] Intel ® Pentium® Processor E5800 (2M Cache , 3.20 GHz, 800 MHz FSB) Intel , Information Intel ® Pentium® Processor E5800 (2M Cache , 3.20 GHz, 800 MHz FSB) LGA775, Tray Socket LGA775 , VT-x Yes Boxed Intel ® Pentium® Processor E5800 (2M Cache , 3.20 GHz, 800 MHz FSB) LGA775 Socket


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PDF E5800 E5000 ucts/42802/Intel-Pentium-Processor-E5800- 20-GHz-800-MHz-FSB) 82801GB 82801JR 82801IR 82801IB intel G31 intel p43 82801gr p35 chipset Intel G33 express chipset intel g33
Intel 430vX

Abstract: 430VX 82437
Text: PRELIMINARY INTEL 430VX PCISET 82437VX SYSTEM CONTROLLER (TVX) AND 82438VX DATA PATH UNIT (TDX) Supports All 3V Pentium® Processors PCI 2.1 Compliant Integrated DRAM Controller - 64-Bit Path to Memory - , Cache Controller - Direct Mapped Organization - Supports 256-KB and 512-KB Pipelined Burst, DRAM Cache , Controller (TVX), two 100-Pin QFP Data Paths (TDX) a The Intel 430VX PCIset consists of the , (L2) cache controller supports a write-back cache policy for cache sizes of 256 Kbytes and 512 Kbytes


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PDF 430VX 82437VX 82438VX 64-Bit 256-KB 512-KB 62437VX Intel 430vX 82437
Intel H61

Abstract: FCLGA1155 intel p67 intel Q67 BX80623G850 CPUs Processors FC-LGA10 intel q65 Sandy Bridge intel Sandy Bridge
Text: Intel ® Pentium® Processor G850 (3M Cache , 2.90 GHz) Menu Language: English English , Threads Clock Speed Intel ® Smart Cache Bus/Core Ratio DMI Instruction Set Instruction Set Extensions , :// - Cache -2_90-GHz)[8/3/2011 12:06:01 PM] Intel ® Pentium® Processor G850 (3M Cache , 2.90 GHz) Intel ® Wireless Display Intel ® Flexible Display Interface , Intel ® Pentium® Processor G850 (3M Cache , 2.90 GHz) FC-LGA10D, Tray Socket FCLGA1155 Step Step


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PDF ducts/53491/Intel-Pentium-Processor-G850- 90-GHz) Intel H61 FCLGA1155 intel p67 intel Q67 BX80623G850 CPUs Processors FC-LGA10 intel q65 Sandy Bridge intel Sandy Bridge
2012 - PPGA478

Abstract: intel 915PM LE80536GC0332M HPBGA479 RJ80536GC0332M H-PBGA479 ECCN LE80536GC0332M SLJ8Z CCATS RJ80536
Text: Intel ® Pentium® M Processor 745 (2M Cache , 1.80 GHz, 400 MHz FSB) Page 1 of 3 English Home , Intel ® Pentium® M Processor 745 (2M Cache , 1.80 GHz, 400 MHz FSB) SPECIFICATIONS Specifications , \In. 13-Aug-2012 Intel ® Pentium® M Processor 745 (2M Cache , 1.80 GHz, 400 MHz FSB) Page 2 of , (Configurations: 2) Intel ® E7320 Chipset with 6300ESB I/O Controller Hub # of CPUs: 1 Embedded: Yes System Price: N/A System TDP: 34.1W Intel ® E7320 Chipset with 82801ER I/O Controller Hub 5 R (ICH5R) # of CPUs: 1


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PDF 32-bit 76V-1 8473301180-MPU PPGA478 BXM80536GC1800F 3A991 H-PBGA479 H-PBGA479 RJ80536GC0332M PPGA478 intel 915PM LE80536GC0332M HPBGA479 ECCN LE80536GC0332M SLJ8Z CCATS RJ80536
2000 - intel desktop board SERVICE MANUAL

Abstract: 80960JT PC-100 SYM53C1010 SRCU31
Text: Intel ® Server RAID Controller U3-1 (SRCU31) Technical Product Specification Document number , respective owners. ii Revision 1.1 Document number 273351-002 Intel ® Server RAID Controller U3 , . 15 iv Revision 1.1 Document number 273351-002 Intel ® Server RAID Controller U3-1 (SRCU31 , number 273351-002 Intel ® Server RAID Controller U3-1 (SRCU31) TPS 1. Overview Overview The Intel ® Server RAID Controller U3-1 (SRCU31) is a single-channel Ultra 160 SCSI RAID PCI adapter


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PDF SRCU31) 80-pin intel desktop board SERVICE MANUAL 80960JT PC-100 SYM53C1010 SRCU31
2009 - intel date code format

Abstract: LE80536VC001512 sl8a4 ICH4-M LE80536 915PM 6300ESB 910GML RJ80536VC001512 HPBGA479
Text: at 4/16/2009 9:02:44 AM Intel ® Celeron® M Processor ULV 373 (512K Cache , 1.00 GHz, 400 MHz FSB , Halogen Free Intel ® Celeron® M Processor ULV 373 (512K Cache , 1.00 GHz, H-PBGA479 400 MHz FSB) uFCBGA , RJ80536VC001512 06D8 LE80536VC001512 SPEC Code SL8A4 SL89S Intel ® Celeron® M Processor ULV 373 (512K Cache , 1.00 GHz, H-PBGA479 C0 400 MHz FSB) uFCBGA, Tray Intel ® Celeron® M Processor ULV 373 (512K Cache , 1.00 GHz , Embedded Intel ® 852GM Chipset with 6300ESB I/O Controller Hub Embedded Intel ® 852GM Chipset with 82801DB I


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PDF 06D8h rt/processors/mobile/celeron/sb/CS-023760 intel date code format LE80536VC001512 sl8a4 ICH4-M LE80536 915PM 6300ESB 910GML RJ80536VC001512 HPBGA479
2009 - 82801GHM

Abstract: LE80537LF0214M 82801GBM PBGA479 intel CORE 2 duo instruction set 945GMS LE80537LF0214M SL9SM 28026 ICH7M-DH LE80537
Text: , based on Intel ® CoreTM microarchitecture, include two complete execution cores, shared L2 cache , and , Intel ® CoreTM2 Duo Processor L7400 (4M Cache , 1.50 GHz, 667 MHz FSB) with SPEC Code(s) SL9SM, SLGFX , Processor L7400 (4M Cache , 1.50 GHz, 667 MHz FSB) with SPEC Code(s) SL9SM, SLGFX Intel Developer Forum , ] Intel ® CoreTM2 Duo Processor L7400 (4M Cache , 1.50 GHz, 667 MHz FSB) with SPEC Code(s) SL9SM, SLGFX , Processor L7400 (4M Cache , 1.50 GHz, 667 MHz FSB) with SPEC Code(s) SL9SM, SLGFX Intel ® CoreTM2 Duo


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PDF T9400, P8400, SL9400, SL9380, SP9300, SU9300, T7500, T7400, L7500, L7400 82801GHM LE80537LF0214M 82801GBM PBGA479 intel CORE 2 duo instruction set 945GMS LE80537LF0214M SL9SM 28026 ICH7M-DH LE80537
1994 - i960 sb

Abstract: 32-bit microprocessor architecture applications of microprocessor in printer i960 kb i960 microprocessor control unit intel i960 intel i960 series i960CF
Text: INSTRUCTION PREFETCH QUEUE INSTRUCTION CACHE INTERRUPT PORT PROGRAMMABLE INTERRUPT CONTROLLER , performance goal of RISC (Reduced Instruction Set Computing) techniques. Intel also offers the second i960 , cache memory design, the i960 CF processor is capable of double the performance of the i960 CA , . s Superscalar RISC core s 1 Kbyte two-way set associative instruction cache ® (i960 CA processor only) s 4 Kbyte two-way set associative instruction cache (i960 CF processor only) s 1 Kbyte


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PDF CA/i960 32-Bit 32-bit i960-282 0/0194/10K/HP i960 sb 32-bit microprocessor architecture applications of microprocessor in printer i960 kb i960 microprocessor control unit intel i960 intel i960 series i960CF
82424tx

Abstract: 82424ZX 82423 82423ZX S82378 82423TX 82420 intel 290467 82378IB 0/82420 intel
Text: three components: the 82424 Cache DRAM Controller (CDC), the 82423 Data Path Unit (DPU), and the 82378 , -Pin QFP Package P ro d u ct D escrip tion The 82424 Cache DRAM Controller (CDC) is a single-chip bridge , controller , PCI controller , fast 32-bit DMA controller , and standard system I/O functions. 1-204 INTEL , is intended to be used with the 82424 Cache DRAM Controller (CDC). During bus operations between the , te l 82424 CACHE AND DRAM CONTROLLER (CDC) Supports 25/33/527 MHz lntel486TM SX, lntel487TM SX


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PDF 4flEbl75 Intel486 Intel486 8242ASTER* IRQ12/M FERRI/IRQ13 82424tx 82424ZX 82423 82423ZX S82378 82423TX 82420 intel 290467 82378IB 0/82420 intel
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