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Part Manufacturer Description Datasheet Download Buy Part
LTC1840CGN#PBF Linear Technology LTC1840 - Dual Fan Controller with 2-Wire Interface; Package: SSOP; Pins: 16; Temperature Range: 0°C to 70°C
LTC1840CGN#TR Linear Technology LTC1840 - Dual Fan Controller with 2-Wire Interface; Package: SSOP; Pins: 16; Temperature Range: 0°C to 70°C
LTC1840IGN#PBF Linear Technology LTC1840 - Dual Fan Controller with 2-Wire Interface; Package: SSOP; Pins: 16; Temperature Range: -40°C to 85°C
LTC1695CS5#PBF Linear Technology LTC1695 - SMBus/I2C Fan Speed Controller in SOT-23; Package: SOT; Pins: 5; Temperature Range: 0°C to 70°C
LTC1840CGN Linear Technology LTC1840 - Dual Fan Controller with 2-Wire Interface; Package: SSOP; Pins: 16; Temperature Range: 0°C to 70°C
LTC1695CS5 Linear Technology LTC1695 - SMBus/I2C Fan Speed Controller in SOT-23; Package: SOT; Pins: 5; Temperature Range: 0°C to 70°C

c 9050 60001, motor Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
-20/C9045 - 60001

Abstract: C9045+60001 A/C9045 - 60001 C9045+-+60001
Text: THE INFORMATION CONTAINED HEREIN IS CONSIDERED "PROPRIETARY" TO BEL FUSE INC. AND SHALL NOT BE COPIED, REPRODUCED OR DISCLOSED WITHOUT THE WRITTEN APPROVAL OF BEL FUSE INC. ELECTRICAL CHARACTERISTICS @ 25° C .0 TURNS RATIO: 2.0 INDUCTANCE: P6-P5-P4) P3-P2-P1) P6-P5-P4 P3-P2-P1 (J6-J3 (J2-J1 350uH MIN. 350uH MIN. 0.1V, 0.1V, 3.0 LEAKAGE INDUCTANCE: P6-P5-P4 (WITH J6 AND J3 SHORT P3-P2-P1 , compatible -260° c for io seconds ma:. ORIGINATED BY Bain Liu DATE 12-15-08 DRAWN BY LW Yuan


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PDF 350uH 10OKHz, CH0077 -20/C9045 - 60001 C9045+60001 A/C9045 - 60001 C9045+-+60001
A/C9045 - 60001

Abstract: No abstract text available
Text: SPECIFIED TO BE ±.005 [0.13] 5. WAVE SOLDER COMPATIBLE - PREHEAT 125* C /90SECS. THIS DRAWING AND THE


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PDF 350uH 100KHz, A/C9045 - 60001
2013 - Not Available

Abstract: No abstract text available
Text: to -40° C to +85° C Output Enable Standard Tape & Reel Packaging Standard, EIA-418 RoHS/Green , indicates MHz and decimal point. OPERATING TEMPERATURE RANGE C = -20° C to +70° C (standard) I = -40° C to +85° C FREQUENCY STABILITY 6 5 3 2 = = = = ± ± ± ± 2 1 20 ppm 25 ppm 50 ppm [standard] 100 ppm [-40° C to +85° C Only] 1] 6I Stability/Temperature combination is , -020, 260° C maximum. 3. Moisture Sensitivity Level 1 per JEDEC J-STD-020. D.U.T. PIN ASSIGNMENTS PIN


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PDF EIA-418 62M5000] 155M5200] J-STD-020, J-STD-020.
Not Available

Abstract: No abstract text available
Text: Specifications Motor Protection: P-Q Curve In H2O Insulation Resistance: (Pa) Speed Curve 4.0 , 125 9000 0.0 Expected Life 14000 0.5 Ps 15000 747 1.0 -10° C ~ +60° C (Operating) -40° C ~ +60° C (Storage) (non-condensing environment) 872 3.0 Dielectric , Rate: 10% 25° C 100,000 Hours .57 1.13 1.70 2.27 2.83 3.40 3.99 Speed , (At Ta = 25° C , rated voltage + 12VDC and f=66.4 kHz) at Vin=12V, f=66.4kHz, Vst=3.3V, Ta=25˚ C


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PDF 3122FT 3122FT-D4W-B56-
LDT-362

Abstract: No abstract text available
Text: -60005E LDT-60001 " T-4T-07 LASER DIODE IN C . 1300nm EDGE EMITTING LED SERIES FEATURES ►High Peak , • Fotward Voltage • Soldering Time @ 260° C Min. 1270 Typ. 1300 70 0.5 0.5 4.0 4.0 , . FORWARD CURRENT OF THE LDT-60005 CHARACTERISTICS 5 è s E © c ■5 £ OUTPUT POWER AND FORWARD VOLTAGE AS A FUNCTION OF FORWARD CURRENT C ) EMISSION SPECTRA , * Yes Yes Yes Yes No 1 meter Coming 50/125 -45°Cto +85° C -50°Cto +125° C Yes


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PDF 00DDM34 LDT-362, LDT-362E LDT-60005, LDT-60005E LDT-60001 T-4T-07 1300nm LDT-362
Not Available

Abstract: No abstract text available
Text: OTHERWISE SPECIFIED) 7. 0 9. R E V IS IO N S S H C E T I c w w p w r w m m tM v i m w m atcuwMCS , wwritN cowB« of « s nicm ow a. wc_ 2LV.m 2/17/95 2117 /g. 2Ù2J3BL CUSTOMER I I I C BERG T R O N I C S HPC IH V ERT. H O R . ASS Y. «< u i aa lA S f ' * 1^ T 3:1 rom t - y m 60001


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PDF 60001-XX001 0020/O
UNF-2B

Abstract: sensortronics 60050 1256H single LOAD CELL load cell 100kg sensortronics 3000d A/C9045 - 60001
Text: and compression measurements OUTLINE DIMENSIONS in inches [mm] "A" THREAD, 2 PLACES " C " 4 , B C D 25 - 200 1/4-28 UNF-2B 0.65 0.50 2.00 250 - 300 3/8-24 UNF-2B 0.75 0.50 2.00 , mV/V % ±% FSO ±% FSO ±% FSO ±% FSO ±% FSO/°F ±% of load/°F °F (° C ) °F (° C ) °F (° C ) % of


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PDF 5000d, 10000d 3000d 08-Apr-05 UNF-2B sensortronics 60050 1256H single LOAD CELL load cell 100kg sensortronics A/C9045 - 60001
2011 - Not Available

Abstract: No abstract text available
Text: +1.8Vdc, +2.5Vdc, +3.3Vdc or +5.0Vdc Operating Temperature to -40° C to +85° C Output Enable Standard Tape & , FREQUENCY STABILITY 6 5 3 2 = = = = ± ± ± ± 20 ppm 25 ppm 50 ppm [standard] 100 ppm [-40° C to +85° C Only] 1 M FREQUENCY IN MHz M - indicates MHz and decimal point. 2 OPERATING TEMPERATURE RANGE C = -20° C to +70° C (standard) I = -40° C to +85° C 1] 6I Stability/Temperature combination is not available. 2 , 100 25 1 UNIT V ° C MHz ± ppm ± ppm/yr ° C Aging Operating Temperature Commercial Industrial


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PDF 62M5000) 155M5200) J-STD-020, J-STD-020.
RMJ2

Abstract: A/C9045 - 60001
Text: TH E IN FO R M ATIO N C O N TA IN E D H E R E IN IS C O N S ID E R E D "P R O P R IE T A R Y " TO B E L F U S E INC. AN D S H A L L NOT BE C O PIE D , R E P R O D U C E D OR D IS C LO S ED W ITH O U T , @ 25° C PIN S S C H E M ATIC 1.0 2.0 TURNS RATIO: P6-P5-P4 P3-P2-P1 P6-P4 P3-P1 P6-P4 , TC T P 2 TD - P 3 PD + P4 ' TX+ IN D U C T A N C E : I 00KH2 I OOKHi fv rm J2 T X J3 R X + 3.0 4.0 5.0 LE A K A G E IN D U C T A N C E : 0.3uH 0.3uH 30pF 30pF 1.2 MAX. MAX


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PDF 350uH 350uH 00KH2 SI-60001 10/100BT, RMJ2 A/C9045 - 60001
MST100

Abstract: XS125 WM1003N tag 440 40118 hrc fuse 16.5ka XS16 XS125 fuse GE xs35 NS32M40
Text: E G Fixing Centres H OS C Rating 80 - 100M160 58.00 26.40 90.50 , ) up to 440 (kA) 80 Approvals Max Operating Ambient Temperature (° C ) 40 ASTA 20 Certified , . C Discrimination SAFECLIP Fuse Links will discriminate with each other at fault levels up to , 2:1. Motor Starting Ability All SAFECLIP Fuse Links are suitable for the protection of motor circuits and have superior withstand to motor starting surges. Protection against electric shock


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PDF 63M80* 32M40 63M80 100M125 100M160 MST100 XS125 WM1003N tag 440 40118 hrc fuse 16.5ka XS16 XS125 fuse GE xs35 NS32M40
SI-60001-F

Abstract: A/C9045 - 60001
Text: THE INFORMATION CONTAINED HEREIN IS CONSIDERED "PROPRIETARY" TO BEL FUSE INC. AND SHALL NOT BE COPIED, REPRODUCED OR DISCLOSED WITHOUT THE WRITTEN APPROVAL OF BEL FUSE INC. ELECTRICAL CHARACTERISTICS @ 25" C 1.0 TURNS RATIO: 2.0 INDUCTANCE: (P6-P5-P4 (P3-P2-P1 P6-P4 P3-P1 (J6-J3 (J2-J1 350uH , DRAWN BY LW Yuan DATE 12-15- C TITLE MagJack® 10/100BT TAB DOWN, SHIELDED PART NO. / DRAWING NO , [0.13] 5. PEFLOW AND WAVE SOLDER COMPATIBLE -260° C FOR 10 SECONDS MAX. ORIGINATED BY Bain Liu DATE


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PDF 350uH 30MHz 60MHz 80MHz 100KH2 100KH2 10/100BT -60001-F SI-60001-F A/C9045 - 60001
A/C9045 - 60001

Abstract: No abstract text available
Text: to -40° C to +85° C Output Enable Standard Tape & Reel Packaging Standard, EIA-418 RoHS/Green , indicates MHz and decimal point. OPERATING TEMPERATURE RANGE C = -20° C to +70° C [standard] I = -40° C to +85° C FREQUENCY STABILITY 6 5 3 2 = = = = ± ± ± ± 3 1 20 ppm 25 , ] -40° C to +85° C Only. 3] Frequency is recorded with three leading significant digits before the ‘Mâ , ] with gold [Au] flash plate. 2. Reflow conditions per JEDEC J-STD-020, 260° C maximum, 20 seconds. 3


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PDF EIA-418 62M5000] 155M5200] J-STD-020, A/C9045 - 60001
SCO-10

Abstract: SUNNY sunny SCO
Text: SCO-10 Series - Ceramic SMD package - 5.0, 3.3, 2.5, 1,8V supply voltage - HCMOS/TTL output - Tri-state function available - Reflow soldering is possible -Available on tape and reel SCO-10 CERAMIC SMD TYPE ■ELECTRICAL SPECIFICATIONS Frequency Range 1.000 to 106.250MHz(5V), 1.000 to 200MHz(3.3, 2.5, 1.8V) Operating Temperature Range 0 to +70 C or -40 to +85 °C Storage Temperature Range -55 to+125 " C Frequency Tolerance / Stability Inclusive of Operating Temperature ± 100, ±50ppm or


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PDF SCO-10 SCO-10 250MHz 200MHz 50ppm 20ppm 999MHz 000MHz SUNNY sunny SCO
1996 - PCI9050

Abstract: 38e9 c 9050 10B5 93CS56 NM93CS46 PCI-9050-1
Text: PCI 9050 August 31, 1996 PCI Bus Target Interface Chip for VERSION 1.0 Low Cost Adapters , _ The PCI 9050 provides a compact high performance PCI bus target (slave) interface for adapter boards. The PCI 9050 was designed to connect a wide variety of local bus designs to the PCI bus and to allow , The PCI 9050 can be programmed to connect directly to either the multiplexed or non-multiplexed 8, 16, or 32 bit local bus. The 16 bit mode enables easy conversion of ISA designs to PCI. The PCI 9050


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PDF 250ns 500ns 750ns 1000ns 1250ns PCI9050 38e9 c 9050 10B5 93CS56 NM93CS46 PCI-9050-1
1998 - ISA slot

Abstract: plx 9050 c 9050 plx9050 9050
Text: interface with the PCI 9050 for software and hardware purposes T E C H N O L O G Y ® Overview As , powerful PLX 9050 Bus Target Interface Chip s PCI 9050RDK available for both Generic and ISA Bus , painless way to convert their ISA adapters, PLX offers its PCI 9050 RDK. The RDK plays development host to , of the kit is the PCI 9050 Bus Target interface chip! This 160pin chip has a PCI bus on one side and a flexible local bus on the other. It includes a PCI board designed with the PCI 9050 chip, I/O


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PDF 9050RDK 9050RDK Windows95 ISA slot plx 9050 c 9050 plx9050 9050
Not Available

Abstract: No abstract text available
Text: are standard C M O S stages (refer to A D 9050 Output Stage) with isolated supply pins (Pins 2 0 , 22 , A D C , limiting performance. Figure 18. D ifferentially Driven A D 9050 Using Trans­ fo rm er , e A D 9050 is a complete 10-bit monolithic sampling analogto-digital converter (ADC) with an onboard , ™¦3.3V + 0.512V) C A 2.5 V reference is included onboard, or the user can provide an external , pro­ cess, the A D 9050 is packaged in space saving surface mount packages (SO IC , SSO P) and is


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PDF 10-Bit, AD9050 10-bit -J-C20 28-Lead
1998 - AD27

Abstract: AD29 AD30 PCI Backplane Block Diagram
Text: Disappearance of the ISA Bus T E C H N O L O G Y ® CLK RST# INTA# LOCK# PCI 9050 I/O , 85 84 83 82 81 PCI 9050 PIN OUT T E C H N O L O G Y ® PLX Technology, Inc. 390 , PCI 9050 Bus Target Interface Chip Features s PCI Specification 2.1 Compliant Target , provide single-chip PCI interfaces for every market, PLX offers designers its PCI 9050 Bus Target Interface Chip for low cost adapters. The PCI 9050 provides a compact, high performance PCI bus target


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PDF 32-bit LAD10 LAD11 LAD12 LAD13 LAD14 LAD15 LAD16 LAD17 LAD18 AD27 AD29 AD30 PCI Backplane Block Diagram
LDT-362

Abstract: 12AE6
Text: LASER DIODE IN C - LDT-362, LDT-362E LDT-60005, LDT-60005E LDT-60001 1300nm EDGE EMITTING LED , thermistor may be included In the fla ng e p a c k a g e to provide tem per ature stability. All of the p a , below. ELECTRO-OPTICAL CHARACTERISTICS OF THE DIODE (AT 25 ° C ) Parameters Wavelength* Spectral , Current · Forward Voltage · Soldering Time @ 260° C Symbol * AA Min. 1270 Typ. 1300 70 0.5 0.5 4.0 4.0 Max. 1330 90 0.65 Units nm nm nm /° C nm /° C nsec nsec Tr Tf Po 40 80 150 4 8 50 -1.5 +5.0 Imax VF 200


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PDF LDT-362, LDT-362E LDT-60005, LDT-60005E LDT-60001 1300nm LDT-362 12AE6
P-CDL

Abstract: D0014S3 10B5 38E9 93CS56 NM93CS46 PCI9050
Text: PDL^ PCI 9050 T e cTHTSTS-STX August 31, 1996 VERSION 1.0 Featu res_ • PCI Specification , QFP Package PCI Bus Target Interface Chip for Low Cost Adapters General Description_ The PCI 9050 provides a compact high performance PCI bus target (slave) interface for adapter boards. The PCI 9050 was , bus designs to achieve 132 Mbytes/sec burst transfers on the PCI bus. The PCI 9050 can be programmed , bit mode enables easy conversion of ISA designs to PCI. The PCI 9050 contains a bi-directional FIFO


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PDF 160Pin 250ns 500ns 1000ns P-CDL D0014S3 10B5 38E9 93CS56 NM93CS46 PCI9050
2001 - plx 9052

Abstract: A 9050 14 pci 9052 9050-1
Text: . Document PCI 9050 Data Book C . Revision 2.0 Description PCI 9050-1 Data Book Publication , PCI 9050 Errata Rev. 1.3 August 2001 Errata Documentation A. Affected Silicon Revision This document details errata in the following silicon: Product PCI 9050 B. Part Number PCI , # de-assertion during an idle phase Read Ahead Mode (PCI Read No Flush Mode) with Burst Enabled -1- 9050 , register compatible with the PCI 9050 . Impact: In the production phase, for some types of adapters it is


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PDF 160-pin 9050-SIL-ER-P0-1 plx 9052 A 9050 14 pci 9052 9050-1
1997 - Not Available

Abstract: No abstract text available
Text: interface to 3 V logic systems. T he digital outputs are standard C M OS stages (refer to AD 9050 Output , 9050 will supply 3 V output levels. C are should be taken to filter and isolate the output supply of the AD 9050 as noise could be coupled into the AD C , limiting performance. +5V 1kΩ T he , U CT D ES CRIP TION T he AD 9050 is a complete 10-bit monolithic sampling analogto-digital converter (AD C ) with an onboard track-and-hold and reference. T he unit is designed for low cost, high


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PDF 10-Bit, MSPS/60 AD9050 10-bit C2048bâ
1997 - 0x9050 0x10b5

Abstract: PLXMON95 LA2780 8BA22 9050RDK NM93CS46 MACH210 BD28 PLX9050 AN8250
Text: Fax: 1- 408-774-2169 Email: info@plxtech.com Web and FTP Site: //www.plxtech.com T E C H N O L O , . 26 PCI 9050 Target Interface Chip , PCI software to explore and configure the PCI 9050 and piggybacked ISA cards · Troubleshoot , software to learn about the PLX PCI 9050 interface chip, to build PCI-based projects, and test functional , 9050RDK card include the PLX PCI 9050 interface chip and the ISA 8/16 connector. You can plug most ISA


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PDF 9050RDK 9050RDK-M002 0x9050 0x10b5 PLXMON95 LA2780 8BA22 9050RDK NM93CS46 MACH210 BD28 PLX9050 AN8250
Not Available

Abstract: No abstract text available
Text: 10 5 10 BITS A D 9050 (2) 74 A C 5 7 4 9 13 1, 7, 12, 21,23 Figure 1 . Typical , ] GND VD [ * vr e fout |T v r e f in [7 c o m p [T r e f bp U g n d |T A D 9050 i]v D D TOP , 9050 as noise could be coupled into the A D C , limiting perform ance. Figure 17. Single Ended , PRODUCT DESCRIPTION T he A D 9050 is a com plete 10-bit m onolithic sampling analogto-digital converter , 5 V/3 V logic, selected by the user. T he two-step architecture used in the AD 9050 is opti mized to


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PDF 10-Bit, AD9050 10-bit AD9050. AD9050
Not Available

Abstract: No abstract text available
Text: .2 S E C T IO N 1 - P C I 9050 G E N E R A L D E S C R IP T IO N , generate a PCI interrupt from two local bus interrupt inputs. C lock. The PCI 9050 local bus interface , a RETRY to the PCI bus. P C I L O C K m echanism The PCI 9050 supports PCI target LO CK sequences , R e v n in n 1 (I P C I 9050 b flS S m i □□Q14D4 A3? SECTION 3 FUNCTIONAL , PCI 9050 TE August 31, 1996 VERSION 1.0 PCI Bus Target Interface Chip for Low Cost


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PDF
SCO-10

Abstract: Sunny Oscillators
Text: +125° C Inclusive of Operating Temperature Range, Supply Voltage, and Load ±100, ±50ppm or ±25, Â


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PDF SCO-10 20ppm 250MHz 200MHz 768kHz or-40 50ppm 20ppm 999MHz 000MHz Sunny Oscillators
Supplyframe Tracking Pixel