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msd9wb9pt-2

Abstract: MSTAR
Text: , rectangle draw/fill, text draw and trapezoid draw BitBlt , stretch BitBlt , trapezoid BitBlt , mirror BitBlt and rotate BitBlt Raster Operation (ROP) Support Porter-Duff Compliant with NTSC M/N, PAL B, G/H, I


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PDF 16-bit 1066MHz 380-ball msd9wb9pt-2 MSTAR
CL-GD7543

Abstract: g31 crb register116 sra 433 d1
Text: . 280 12.57 GR32: BitBLT Raster Operation (ROP) Register , . . 63 Bit Block Transfer ( BitBLT ) E ngine , . 262 12.41 GR20: BitBLT Width Low Register. 263 12.42 GR21: BitBLT Width High Register. 264 12.43 GR22: BitBLT Height Low Register


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PDF CL-GD7541/GD7543 CL-GD7541/GD7543 32-Bit 486DX 12-Bit CL-GD7543 g31 crb register116 sra 433 d1
vport

Abstract: No abstract text available
Text: .326 GR32: BitBLT Raster Operation (ROP) Function R egister , . 101 3.5.5 Bit Block Transfer ( BitBLT ) Engine , . 256 12.13 SR17: BitBLT Memory Map I/O Address Control R egister , .308 GR20: BitBLT Width Low GR21: BitBLT Width High R egister


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PDF CL-GD7548 CL-GD7548 vport
ST VIPER 27h

Abstract: OPTi 82C264 82C264 6900S 92c168 seven segment ulf ix 2933 MD31 4 stroke engine files bitblt raster
Text: .24 5.4.1 Status/Start 5.4.2 BitBLT Mode 5.4.3 BitBLT Raster Operation Register , is via bits 1 and 0 of the BitBLT mode register. Raster Operations between the source and destination , .16 4.7.1 BitBLT .16 4.7.2 Color Expansion , .1 4.7.8 Raster 4.8 Hardware Cursor


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PDF 82C264 ST VIPER 27h OPTi 82C264 6900S 92c168 seven segment ulf ix 2933 MD31 4 stroke engine files bitblt raster
MD-720-3

Abstract: srf 2417 cl-gd7543 HDE 3515 capacitor lsk 561 VGA 20 PIN LCD MONITOR CABLE CONNECTION DIAGRAM CL-PX4072 MD720-3 LCOS svga PC104 pinout
Text: .326 12.61 GR32: BitBLT Raster Operation (ROP) Function Register , €” BitBLT engine (double-buffering, auto-start, memory-mapped I/O, and transparent BitBLT ) — Color , BitBLT GUI acceleration, continuous upscaling for 1024 x 768 and 800 x 600 LCDs, true-color capability , /SVGA LCD Controller — CIRRUS LOGIC UNIQUE FEATURES High Performance ■BitBLT engine, color expansion, hardware cursor, linear addressing, and 32-bit memory interface ■BitBLT double-buffering


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PDF CL-GD7541/7543 16-bit MD-720-3 srf 2417 cl-gd7543 HDE 3515 capacitor lsk 561 VGA 20 PIN LCD MONITOR CABLE CONNECTION DIAGRAM CL-PX4072 MD720-3 LCOS svga PC104 pinout
MD21-MD20

Abstract: OE23 SC15064 pc motherboard schematics
Text: J b . SIERRA æMICDNDUCTOR ' v FALCON/64 (Integrated 64-Bit GUI Accelerator) SC15064 FEATURES Graphics Acceleration (hardware based) BitBlt Raster operations Line draw Pattern fill Color expansion PRODUCT BRIEF Bus Support · · PCI Local Bus ISA BUS · VESA® VL-BUSTM Software Support · Windows 3.1 · Windows NT · OS/2 2.1 · SCO UNIX · Accelerated CAD drivers · Exter.ced mode support for a variety of DOS applications DRAM Memory Support 1,2, or 4 MBytes display memory Extended Data Out (EDO


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PDF FALCON/64 64-Bit SC15064 640x480 800x600 1024x768, 1024x768 1280x1024, A242010 MD21-MD20 OE23 SC15064 pc motherboard schematics
wd9710

Abstract: MRC D30
Text: .63 BITBLT RASTER OPERATION . 64 , .4 2. 6 2.3.2 Hardware BITBLT , . 61 BITBLT REGISTER MAP , .60 9-1 FIRST BITBLT REGISTER BLOCK (BLOCK 4 ) .61 9-2 SECOND BITBLT REGISTER BLOCK (BLOCK 5


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PDF 64-Bit 79-890018-000-P3 171fl22a WD9710 208-pin 200-PIN wd9710 MRC D30
HDE 3515

Abstract: Cirrus Logic Voyager
Text: . 326 GR32: BitBLT Raster Operation (ROP) Function Register , from Enhanced MVA™ ■GUI acceleration — BitBLT engine (double-buffering, auto-start, memorymapped I/O, and transparent BitBLT ) — Color expansion for 8- or 16-bit pixels — True packed-pixel , High Performance ■BitBLT engine, color expansion, hardware cursor, linear addressing, and 32 , resolution and color-depth capabilities. ■BitBLT double-buffering, auto-start, and m em ory-m apped


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PDF CL-GD7548 CL-GD7541/7543 16-bit HDE 3515 Cirrus Logic Voyager
WD90C31

Abstract: transistor m023 WD90C30 HSYNC, VSYNC input output til 815 display IBM ega registers CRTC overscan Western digital 8514 transistor DA3 309 bitblt raster
Text: Background Colors Map And Plane Mask Raster Operations Patterns 9.7.1 BITBLT Pattern Storage - , Registers Cursor Color Modes BITBLT Registers Raster Operation Code EGA Registers Summary Shadow , General Description 1.2.1 Hardware Cursor 1.2.2 Hardware BITBLT 18-1 18-1 18-2 18-2 18-2 2.0 , Differences Between Hardware And Software Cursor Cursor Plane Protection 8.6.6 HARDWARE BITBLT 9.1 Source And Destination 9.1.1 BITBLT Source Low, Index 2 BITBLT Source High, Index 3 9.1.2 BITBLT


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PDF WD90C31 WD90C31 144-PIN transistor m023 WD90C30 HSYNC, VSYNC input output til 815 display IBM ega registers CRTC overscan Western digital 8514 transistor DA3 309 bitblt raster
Not Available

Abstract: No abstract text available
Text: . 97 BITBLT Truth Table . . . . . 103 Raster Operation Code 103 EGA , BITBLT 2.0 T-52-33-45 Page WD90C31 ARCHITECTURE 1 1 2 2 2 . . 3.0 WD90C31 , . . . 99 9.2.1 BITBLT Source Low, index 2 . . . . . . . . . . 100 9.2.2 BITBLT Source High, Index 3 . . . . . . . . . . . . . . . 100 9.2.3 BITBLT Destination Low, Index 4 . . . . . . . . . . . . . . 100 9.2.4 BITBLT Destination High, Index 5


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PDF WD90C31 1BS56 T-52-33-45 grante20 144-PIN INFORMATION2/7/92
90C31

Abstract: No abstract text available
Text: €¢ Hardware BITBLT . - Raster operations. Special double scanning and underline. - Transparency. - , 1.2.1 Hardware Cursor . 1.2.2 Hardware BITBLT , . 11.2 Source And Destination . 11.2.1 BITBLT Source Low, Index 2 . 11.2.2 BITBLT Source High, Index 3 11.2.3 BITBLT Destination Low, Index 4 11.2.4 BITBLT , . 11.4.1 BITBLT Dimension X, index 6 11.4.2 BITBLT Dimension Y, Index 7 11.4.3 BITBLT Row Pitch


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PDF 7ifi52fl WD90C31A WD90C31A 132-pin T-52-33-45 144-pin 90C31
Not Available

Abstract: No abstract text available
Text: . 144 19.7.1 BITBLT Raster Operation, Index 9 .144 , . 6 2. 14 2 .1 5 2. 16 3.0 HARDWARE BIT BLOCK TRANSFER ( BITBLT , . 127 INDEXED REGISTER ACCESS FOR HARDWARE CURSOR, BITBLT , AND LINE D R AW IN G , .138 19.1.1 BITBLT Control - Part 1, Index 0 . 138 19.1.2 BITBLT Control - Part 2, Index 1 . 139 SOURCE


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PDF l71fl2Zfl WD90C24A/A2 001fl3 208-pin 206-PIN
WD90C24

Abstract: LTM10C015K lcm-5505 LQ10D011 NL6448AC30-03 EG9011D WD90C24A 6845 crt controller crt controller 6845 WD90C24A2
Text: .143 19.7 RASTER OPERATIONS .144 19.7.1 BITBLT Raster Operation , TRANSFER ( BITBLT ) .6 2. 12 HARDWARE LINE DRAWING , HARDWARE CURSOR, BITBLT , AND LINE 17. 1 ACCESSING , .137 19.0 HARDWARE BITBLT .138 19. 1 CONTROL AND STATUS.138 19.1.1 BITBLT Control - Part 1, Index 0.138 19.1.2 BITBLT Control - Part 2, Index


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PDF WD90C24A/A2 P0418 17ia22fl 001fl3 WD90C24A/A2 208-pin WD90C24 LTM10C015K lcm-5505 LQ10D011 NL6448AC30-03 EG9011D WD90C24A 6845 crt controller crt controller 6845 WD90C24A2
STN21

Abstract: gd170
Text: architecture that supports: • Simultaneous display and Bit Block Trans­ fer ( BITBLT ) without changing the , Hardware Window Accelerator ( BITBLT ) Hardware Line Drawing Frame Buffer Controller Each module is , flicker on the panel screen. 2.12 HARDWARE WINDOW ACCELERATOR ( BITBLT ) The WD90C24 was designed , WD90C24 Bit Block Transfer ( BITBLT ) increases speed. With BITBLT , blocks of pixels are transferred , system I/O or memory port For additional BITBLT information refer to Section 19. 2.13 WD90C24


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PDF WD90C24 WD90C24 00171BQ 208-pin STN21 gd170
1997 - crt controller

Abstract: No abstract text available
Text: .12-97 GR32: BitBLT Raster Operation Function Register , €” 64-bit BitBLT acceleration engine — 64-bit display memory interface — 64-bit data paths s GUI acceleration — — — — BitBLT setup register double buffering with autostart Transparent BitBLT (source color key) Memory-mapped I/O True packed-pixel addressing for 8, 16, and 24 bpp , the CL-GD7556 is accomplished with 64-bit architecture (64-bit BitBLT engine, memory interface, and


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PDF CL-GD7556 CL-GD7556 64-bit CL-GD7555, crt controller
gr2c

Abstract: gr26
Text: Pitch Source Pitch Destination Start Source Start BitBLT Mode Start/Status Raster Operation How , destination area, the CL-GD7548 BitBLT engine can use various logical raster operations to com bine the source , -2. Logical Com binations of Bits Using the BitBLT Engine Microsoft® Name / Raster Operation BLACKNESS , CL-GD7548 XGA/SVGA LCD Controller Ì CIRRUS LOGIC Appendix A BitBLT Engine A.1 In tr o d u c tio n BitBLT (bit block transfer) is an operation in which one area (source area) of


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PDF CL-GD7548 CL-GD7548 gr2c gr26
100411B

Abstract: IOR 5B2 3H 92c168 opti 486 chipset
Text: No file text available


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PDF 92C178 92C178, 92C168, 92C178 100411B IOR 5B2 3H 92c168 opti 486 chipset
Not Available

Abstract: No abstract text available
Text: DATA BO O K v1.1 BITBLT ENGINE 411 CL-GD7541/GD7543 W CIRRUS LOGIC A.4 Raster Operations , destination area, the CL-GD7541/GD7543 BitBLT engine can use various logical raster operations to com bine the , A-2. Logical Combinations of Bits Using the BitBLT Engine Microsoft^ Name / Raster Operation , BitBLT mode Start/Status Raster Operation Transparent Color - Low Byte Transparent Color - High Byte , CL-GD7541/GD7543 Super V G A L C D Controller CIRRUS LOGIC Appendix A BitBLT Engine A


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PDF CL-GD7541/GD7543 CL-GD7541/G D7543
bitblt

Abstract: DP8511V DP8500 DP8511 V44A system on a chip graphics DP850
Text: m co a Q National Semiconductor DP8511 BITBLT Processing General Description The DP8511 BITBLT Processing Unit (BPU), a member of National Semiconductor's Advanced Graphics Chip Set (AGCS), is a high performance microCMOS device intended for use in raster graphics applications. Specifically designed to complement the DP8500 Raster Graphics Processor (RGP), the BPU performs data operations that are elementary to BITBLT (BIT boundary Block Transfer) graphics: Shift, mask, and bitwise logical


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PDF DP8511 DP8500 D-7100 728746tfkd bitblt DP8511V V44A system on a chip graphics DP850
bitblt

Abstract: video graphic* controller 16-bit DP8510 block diagram for barrel shifter
Text: National Semiconductor DP8510 BITBLT Processing General Description The DP8510 BITBLT Processing Unit (BPU) is a high-performance microCMOS device designed for use in raster graphics applications. It implements, in high-speed pipelined logic, the data operations which are fundamental to BITBLT , necessary data path operations, easing the implementation of a wide variety of BITBLT systems. A number of , CPU, the BPU and the memory system. The BPU has two modes, BITBLT and line drawing. The mode is set by


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PDF DP8510 32-bit 16-bit 16-word 44-pin DQO-15 bitblt video graphic* controller 16-bit block diagram for barrel shifter
CL-GD7541

Abstract: MD-720-3 graphical lcd 128X64 with touch screen 128X64 graphical LCD screen cl-gd7543 LD3120 APPLE LCD INVERTER SiS chipset 486 CL-GD7542 LCD VGA Controller Preliminary Data Boo mc1377 application note
Text: . 280 12.57 GR32: BitBLT Raster Operation (ROP) Register , acceleration — BitBLT (bit block transfer) engin e — Color expansion for 8- or 16-bit pixel s — True , ordering in display memory with PCI host interface High Performance ■BitBLT engine, color expansion , . 63 3.2.5 Bit Block Transfer ( BitBLT ) Engine , .262 12.41 GR20: BitBLT Width Low Register


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PDF CL-GD7541/GD7543 CL-GD7542 16-bit CL-GD7543 CL-GD7541 MD-720-3 graphical lcd 128X64 with touch screen 128X64 graphical LCD screen LD3120 APPLE LCD INVERTER SiS chipset 486 CL-GD7542 LCD VGA Controller Preliminary Data Boo mc1377 application note
1998 - b69000 chips

Abstract: b69000 B65555 chips m69000 m69000 chips 69000 B65554 69000 agp to video converter bitblt raster
Text: Reduced Motion Artifacts · Crisper Display Graphics Acceleration · 64-bit Single Cycle BitBLT Engine · System/Screen-Screen BitBLTs · Transparent, Source, Destination BitBLT · 256 3-Op Raster Operations · , . These operations include color expansion, system-to-screen BitBLT , screen-to-screen BitBLT , transparent source/destination BitBLT , rectangle fill, and 2563Op raster operations. 2D acceleration is


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PDF 64-BIT 24-bit 24bpp PC97-98 36-bit b69000 chips b69000 B65555 chips m69000 m69000 chips 69000 B65554 69000 agp to video converter bitblt raster
1998 - B69030

Abstract: M69030 69030 chips 69030 Chips and Technologies 69030 MONOCHROME CRT CONTROLLER 1024x600 YUV422-RGB tmed 128x128
Text: Display Graphics Acceleration · 64-bit Single Cycle BitBLT Engine · System/Screen-Screen BitBLTs · Transparent, Source, Destination BitBLT · 256 3-Op Raster Operations · Color Expansion · Instant Full , . These operations include color expansion, system-to-screen BitBLT , screen-to-screen BitBLT , transparent source/destination BitBLT , rectangle fill, and 256 raster operations. 2D acceleration is , -Bit BitBLT Engine Low-Power Consumption Dual Independent Display · Different or same display image on


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PDF 64-Bit 1600x1200 1280x1024 64-bit 1600x1200, 24-bit/color, PC98-99 36-bit B69030 M69030 69030 chips 69030 Chips and Technologies 69030 MONOCHROME CRT CONTROLLER 1024x600 YUV422-RGB tmed 128x128
VL16160

Abstract: VL16160PC VL16160-QC bitblt raster
Text: V L S I Tech n o lo gy , in c . VL16160 RASTER OP ALU FEATURES · Provides hardware assist for , 256 possible raster operations on source, destination, and pattern data · 28- pin package; 5 V supply DESCRIPTION The VL16160 Raster Op ALU (RALU) provides hardware-assisted perform ance enhancements for bit , ( BITBLT ), allow bit mapped images to be combined and manipulated by logical operators. These operators , for masking with multiple mask registers for clipping is included. The BITBLT operation is general


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PDF VL16160 32-bit VL16160 VL16160PC VL16160-QC bitblt raster
GP360

Abstract: RPX 200 GP425 T28b 2d graphics line drawing filling texture mapping CQ T4A X1Y11
Text: control, DM A to print engine, and BitBLT engine. High speed Raster Printer Accelerator for the 15 to 40 , Primitives: · Trapezoid fill for high speed graphics · Line drawing B it BLT Engine: · Three operand BitBLT , Family Raster Printer Accelerator (RPX) FEATURES (cont'd) Print Engine Interface: · Serial data or , CIRRUS LOGIC Raster Printer Accelerator (RPX) family is comprised o f functionally compatible , reducing controller chip count to a minimum. Product s i CL-G P 315: Highly integrated Raster Printer


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Supplyframe Tracking Pixel