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LT1103CY Linear Technology IC SWITCHING CONTROLLER, Switching Regulator or Controller
LT3524S Linear Technology IC SWITCHING CONTROLLER, PDSO, Switching Regulator or Controller
LT1945IMS Linear Technology IC 0.4 A DUAL SWITCHING CONTROLLER, PDSO8, PLASTIC, MSOP-10, Switching Regulator or Controller
LTC3830DWF Linear Technology IC SWITCHING CONTROLLER, 250 kHz SWITCHING FREQ-MAX, UUC, DIE, Switching Regulator or Controller
LT1103IY Linear Technology IC 2 A SWITCHING CONTROLLER, PSFM7, TO-220, 7 PIN, Switching Regulator or Controller
LT3524CN Linear Technology IC SWITCHING CONTROLLER, PDIP, Switching Regulator or Controller

axi compliant ddr3 controller Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
rk3188

Abstract: RK3188-T ARGB888 emmc boot sequence
Text: 10/100MEthernet Controller „ IEEE802.3u compliant Ethernet Media Access Controller (MAC) „ Support , memory interface( DDR3 /LPDDR2/LVDDR3) capable of sustaining demanding memory bandwidths, also provides a , DDR3 -800, LPDDR2-800, LVDDR3-800 z Totally 3-channels SD/MMC interface to support MMC4.41, SD3 , Cache controller + L2 Dataram, and including PD_A9_0, PD_A9_1, PD_A9_2, PD_A9_3, PD_DGB One isolated , memory „ DDR3 -800, 16/32bits data widths, 2 ranks, totally 2GB(max) address space, maximum address


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PDF RK3188Technical RK3188 1080p 60fps, 264/MVC/VP8 30fps, RK3188-T ARGB888 emmc boot sequence
2012 - Not Available

Abstract: No abstract text available
Text: memory controller • Timer and Interrupts • 16-bit or 32-bit interfaces to DDR3 , DDR2, or , and static memory interface modules. The dynamic memory controller supports DDR3 , DDR2, and LPDDR2 , access to a common memory. The DDR controller features four AXI slave ports for this purpose: â , host controller registers and data structures Two full CAN 2.0B compliant CAN bus interface , -bit) serial NOR flash 8-Channel DMA Controller • Memory-to-memory, memory-to-peripheral


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PDF Zynq-7000 DS188 Zynq-7000
2012 - zynq axi ethernet software example

Abstract: AMBA AXI dma controller designer user guide XC7Z020 ZYNQ-7000 axi compliant ddr3 controller Xilinx Z-7020 DDR3L lpddr2 XC7Z100 XC7Z010 CLG400
Text: interface modules. The dynamic memory controller supports DDR3 , DDR3L, DDR2, and LPDDR2 memories. The static , set of dedicated I/Os. Speed of up to 1333 Mb/s for DDR3 is supported. The DDR memory controller is , memory. The DDR controller features four AXI slave ports for this purpose: · · · One 64-bit port is , SGMII interfaces Two USB 2.0 OTG peripherals, each supporting up to 12 Endpoints · USB 2.0 compliant device IP core · Supports on-the-go, high-speed, full-speed, and low-speed modes · Intel EHCI compliant


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PDF Zynq-7000 DS190 ZynqTM-7000 zynq axi ethernet software example AMBA AXI dma controller designer user guide XC7Z020 axi compliant ddr3 controller Xilinx Z-7020 DDR3L lpddr2 XC7Z100 XC7Z010 CLG400
2012 - UG585

Abstract: CLG225 ZYNQ-7000 zynq7000
Text: ) Byte-parity support Multiprotocol dynamic memory controller • 16-bit or 32-bit interfaces to DDR3 , modules. The dynamic memory controller supports DDR3 , DDR3L, DDR2, and LPDDR2 memories. The static memory , own set of dedicated I/Os. Speed of up to 1333 Mb/s for DDR3 is supported. The DDR memory controller , to a common memory. The DDR controller features four AXI slave ports for this purpose: • One 64 , high speed and full speed modes Intel EHCI compliant USB host controller registers and data


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PDF Zynq-7000 DS190 UG585 CLG225 zynq7000
2012 - XA7Z020

Abstract: CLG225 XA7Z020-1CLG484I UG585 HSTL RGMII XA7Z010 Z-7010 ZYNQ-7000 Z-7020 AMBA AXI dma controller designer user guide
Text: controller and static memory interface modules. The dynamic memory controller supports DDR3 , DDR2, and LPDDR2 , set of dedicated I/Os. Speed of up to 1066 Mb/s for DDR3 is supported. The DDR memory controller is , memory. The DDR controller features four AXI slave ports for this purpose: · · · One 64-bit port is , PHY interface Intel EHCI compliant USB host controller registers and data structures CAN 2.0 , External Memory Interfaces · · · · Multiprotocol dynamic memory controller 16-bit or 32-bit interfaces to


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PDF Zynq-7000 DS188 ZynqTM-7000 XA7Z020 CLG225 XA7Z020-1CLG484I UG585 HSTL RGMII XA7Z010 Z-7010 Z-7020 AMBA AXI dma controller designer user guide
2012 - Not Available

Abstract: No abstract text available
Text: €¢ Multiprotocol dynamic memory controller • 16-bit or 32-bit interfaces to DDR3 , DDR3L, DDR2, or LPDDR2 , to have shared access to a common memory. The DDR controller features four AXI slave ports for this , EHCI compliant USB host controller registers and data structures Two full CAN 2.0B compliant CAN bus , controller and the third goes to the dual-ported on-chip memory (OCM). Each high-performance AXI port has , €¢ USB 2.0 compliant device IP core • Supports on-the-go, high-speed, full-speed, and low-speed


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PDF Zynq-7000Q DS196 Zynq-7000Q -7000Q
2012 - ZYNQ-7000

Abstract: xc7z020 zynq axi ethernet software example AMBA AXI dma controller designer user guide ARm cortexA9 GPIO axi interface ddr3 memory controller Z-7045 FFG676 xc7z030 XC7Z010 2clg
Text: dynamic memory controller and static memory interface modules. The dynamic memory controller supports DDR3 , logic to have shared access to a common memory. The DDR controller features four AXI slave ports for , PHY interface Intel EHCI compliant USB host controller registers and data structures CAN 2.0 , SGMII interfaces Two USB 2.0 OTG peripherals, each supporting up to 12 Endpoints · USB 2.0 compliant device IP core · Supports on-the-go, high-speed, full-speed, and low-speed modes · Intel EHCI compliant


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PDF Zynq-7000 DS190 ZynqTM-7000 xc7z020 zynq axi ethernet software example AMBA AXI dma controller designer user guide ARm cortexA9 GPIO axi interface ddr3 memory controller Z-7045 FFG676 xc7z030 XC7Z010 2clg
2012 - Z-7020

Abstract: No abstract text available
Text: ) Byte-parity support Multiprotocol dynamic memory controller • 16-bit or 32-bit interfaces to DDR3 , modules. The dynamic memory controller supports DDR3 , DDR3L, DDR2, and LPDDR2 memories. The static memory , own set of dedicated I/Os. Speed of up to 1333 Mb/s for DDR3 is supported. The DDR memory controller , to a common memory. The DDR controller features four AXI slave ports for this purpose: • One 64 , high speed and full speed modes Intel EHCI compliant USB host controller registers and data


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PDF Zynq-7000 DS190 Z-7020
2012 - Not Available

Abstract: No abstract text available
Text: ) Byte-parity support Multiprotocol dynamic memory controller • 16-bit or 32-bit interfaces to DDR3 , modules. The dynamic memory controller supports DDR3 , DDR3L, DDR2, and LPDDR2 memories. The static memory , own set of dedicated I/Os. Speed of up to 1333 Mb/s for DDR3 is supported. The DDR memory controller , to a common memory. The DDR controller features four AXI slave ports for this purpose: • One 64 , high speed and full speed modes Intel EHCI compliant USB host controller registers and data


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PDF Zynq-7000 DS190
2012 - Not Available

Abstract: No abstract text available
Text: €¢ Multiprotocol dynamic memory controller • 16-bit or 32-bit interfaces to DDR3 , DDR3L, DDR2, or LPDDR2 , to have shared access to a common memory. The DDR controller features four AXI slave ports for this , EHCI compliant USB host controller registers and data structures Two full CAN 2.0B compliant CAN bus , €¢ USB 2.0 compliant device IP core • Supports on-the-go, high-speed, full-speed, and low-speed modes • Intel EHCI compliant USB host • 8-bit ULPI external PHY interface • 32 KB Level


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PDF Zynq-7000Q DS196 Zynq-7000Q -7000Q
2012 - FBG676

Abstract: XC7A200T-2-FBG676
Text: Bring-up: Enables hands-on operation with the base TRD, which features PCIe, DDR3 memory, AXI stream interconnect, and AXI virtual FIFO controller IP cores—all supported through a custom evaluation graphical , Target - Figure 14 64 bits at 800 Mb/s XADC DDR3 IO UCD90120A AXI MIG Power and , controller from NorthWest Logic and DDR3 64-bit SODIMM memory operating at 800 Mb/s. Artix-7 FPGA Base TRD , IP AXI4 Stream Interconnect PG038, LogiCORE IP AXI VFIFO Controller UG952, AC701 Evaluation Board


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PDF AC701 UG967 2002/96/EC FBG676 XC7A200T-2-FBG676
2013 - axi interface ddr3 memory controller

Abstract: M2s010-fgg484 M2S050-1FG484I M2S050-FG484 M2S050T-1FG484I M2S120T-1FC1152I M2S050T-FG896 M2S005-VF400 M2S010T-FGG484 SECDED
Text: controller is compliant with the Motorola SPI, Texas Instruments synchronous serial, and National , . Users would then instantiate a soft AHB or AXI SDRAM memory controller in the FPGA fabric and connect I , ), memory protection unit (MPU), 8 Kbyte instruction cache, and additional peripherals, including controller , )/ DDR3 memory controllers provide high speed memory interfaces. SmartFusion2 Family Reliability · · , in MSS PCI Express (PCIe) Endpoint Controller x1, x2, x4 Lane PCI Express Core Up to 2 Kbytes Maximum


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PDF 51700115PB-5/2 axi interface ddr3 memory controller M2s010-fgg484 M2S050-1FG484I M2S050-FG484 M2S050T-1FG484I M2S120T-1FC1152I M2S050T-FG896 M2S005-VF400 M2S010T-FGG484 SECDED
2013 - Not Available

Abstract: No abstract text available
Text: ) can be obtained by instantiating a soft AHB or AXI SDRAM memory controller in the FPGA fabric and , are initiated though this block. SPI The serial peripheral interface controller is compliant with , /deserialization (SERDES) communication, while double data rate 2 (DDR2)/ DDR3 memory controllers provide high , €“ Supports LPDDR/DDR2/ DDR3 – Maximum 333 MHz Clock Rate – SECDED Enable/Disable Feature â , Fabric or an SGMII Interface to a soft Ethernet MAC – PCI Express (PCIe) Endpoint Controller


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PDF 51700121PB-5/12
2013 - M2GL150T-1FCG1152I

Abstract: No abstract text available
Text: peripheral interface controller is compliant with the Motorola SPI, Texas Instruments synchronous serial , /deserialization (SERDES) communication, while double data rate 2 (DDR2)/ DDR3 memory controllers provide high , ) HPMS DDR (MDDR) and Fabric DDR (FDDR) Controllers – Supports LPDDR/DDR2/ DDR3 Up to 240 , SGMII Interface to the Ethernet MAC in HPMS – PCI Express (PCIe) Endpoint Controller x1, x2 , a Soft SDRAM Memory Controller High Performance Memory Subsystem • 64 KB Embedded SRAM


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PDF 51700121PB-1/6 M2GL150T-1FCG1152I
2009 - Not Available

Abstract: No abstract text available
Text: and 4 Memory Interface controller blocks supporting DDR, DDR2, DDR3 , and LP DDR interfaces â , Interface GbE (SFP) Memory Controller Block DDR3 SODIMM Local Link to AXI4-Stream Interface , Xilinx Connectivity Targeted Design platforms now support the industry standard AXI interface for design , LogiCORE for XAUI AXI MIG Memory Non- Embedded Mixed IP • GTP transceivers running , €¢ Xilinx Virtual-FIFO memory controller design using built-in Memory Interface Controller Block â


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PDF 125Gb/s) power00
2013 - Not Available

Abstract: No abstract text available
Text: internal coefficient memory • Preadder/subtractor for improved efficiency Memory controller DDR3 , support up to two hard memory controllers for DDR3 , DDR2, and LPDDR2 SDRAM devices. Each controller , . For the Cyclone V SoC FPGA devices, an additional hard memory controller in the HPS supports DDR3 , (EMAC), USB 2.0 On-The-GO (OTG) controller , quad serial peripheral interface (QSPI) flash controller , NAND flash controller , Secure Digital/MultiMediaCard (SD/MMC) controller , UART, controller area


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PDF CV-51001
2012 - Not Available

Abstract: No abstract text available
Text: DDR3 • 1.2 V for LPDDR2 • 1.35 V for DDR3L The power consumption for the NVCC_DRAM supply is , €¢ On-die termination (ODT)—Enabled/disabled, termination value, which is used for the DDR controller and , onboard DDR3 memory devices. This board (on which the measurements were taken) includes four DDR3 devices , ) is a feature of the DDR3 /DDR3L SDRAM that allows the DRAM to turn on/off termination resistance for , memory channel by allowing the DRAM controller to independently turn on/off termination resistance for


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PDF AN4576
2013 - Not Available

Abstract: No abstract text available
Text: €¢ 1.5 V for DDR3 i.MX 6Solo Power Consumption Measurement, Rev. 0 4 Freescale Semiconductor , , termination value, which is used for the DDR controller and DDR memories • Board termination for DDR , SD Platform also includes the current of the onboard DDR3 memory devices. This board (on which the measurements were taken) includes four DDR3 devices, having a total capacity of 1 GB. For power-optimized , termination (ODT) settings On-die termination (ODT) is a feature of the DDR3 /DDR3L SDRAM that allows the


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PDF AN4715
2012 - XC7K325TFFG900

Abstract: XC7K325TFFG900-2 kintex7 XC7K325TFFG900 -2
Text: Controller 64-bit @ 800 MHz MicroBlaze Processor Core EDK IP Core Third-Party IP Core Master AXI , through the axi4_0 interconnect where the Kintex-7 FPGA AXI DDRX memory controller and other high-speed , memory controller . The axi _7series_ddrx contains one AXI4 interface slave connection. The slave’s data , limit of the axi _7series_ddrx controller are both set to 32. IIC Controller Configuration The , Flash Memory Controller DDR, DDR2, DDR3 , LPDDR PCIe Crystal Oscillator Flash Memory


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PDF KC705 DS669 KC705 XC7K325TFFG900 XC7K325TFFG900-2 kintex7 XC7K325TFFG900 -2
2012 - XC7K325TFFG900-2

Abstract: XC7K325TFFG900 PC28F00AP30TF XC7K325T-ffg900 pc28f00ap30 adv7511 pcie microblaze RS232-UART pc28f00 DSP48E1s
Text: MicroBlaze Processor Core EDK IP Core Third-Party IP Core DDR Controller 64-bit @ 800 MHz AXI MM , memory controller . The axi _7series_ddrx contains one AXI4 interface slave connection. The slave's data , limit of the axi _7series_ddrx controller are both set to 32. IIC Controller Configuration The , controller is configured to execute multiple memory access cycles to match memory bank x data width to AXI , DDR3 SDRAM 64 KB internal block RAM 128 MB linear (parallel) flash SDHC controller 2 GB SD card 1 KB


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PDF KC705 DS669 XC7K325TFFG900-2 XC7K325TFFG900 PC28F00AP30TF XC7K325T-ffg900 pc28f00ap30 adv7511 pcie microblaze RS232-UART pc28f00 DSP48E1s
2013 - QSFP28 I2C

Abstract: No abstract text available
Text: controller with support for DDR4, DDR3 , DDR2, LPDDR2 • 40-bit (32-bit + 8-bit ECC) with select packages , 10.3125 Gbps transceiver data rate (chip to chip) Memory devices supported 28.05 Gbps DDR3 SDRAM @ 667 MHz/1333 Mbps DDR4 SDRAM @ 1333 MHz/2666 Mbps DDR3 SDRAM @ 1067 MHz/2133 Mbps Hybrid Memory , /2666 Mbps DDR4 external memory interface 1067 MHz/2133 Mbps DDR3 external memory interface 1.2 V to , Gen1/Gen2/Gen3 complete protocol stack, x1/x2/x4/x8 end point and root port • DDR4/ DDR3 /DDR3L/DDR3U


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PDF AIB-01023 20-nm QSFP28 I2C
2013 - MS2025

Abstract: M2S150
Text: ULPI Interface • CAN Controller , 2.0B Compliant , Conforms ISO11898-1, 32 Transmit and 32 , peripheral interface controller is compliant with the Motorola SPI, Texas Instruments synchronous serial , . Users would then instantiate a soft AHB or AXI SDRAM memory controller in the FPGA fabric and connect I , instruction cache, and additional peripherals, including controller area network (CAN), Gigabit Ethernet, and , /deserialization (SERDES) communication, while double data rate 2 (DDR2)/ DDR3 memory controllers provide high


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PDF 51700115PB-12/10 MS2025 M2S150
2010 - axi compliant ddr3 controller

Abstract: M85000 arm cortex a9 comcerto cortex a9 "ARM Cortex A9" CORTEX-A9 mindspeed 484 dyna image DDR31200
Text: >> DDR3 Memory Controller with ECC Single block of low cost memory supports all external memory needs , for FFT, DCT, and filter processing operations. A single DDR3 memory controller , configurable for , supported through 64-bit AXI , 64-bit AHB, and APB buses, with multiple dedicated DMA engines, allowing all , -2, HMAC · Indus trial temp range · M ulti-layer 64bit AR M AXI bus · Two independently c , time slots total - H.100/H.110 compliant F or more produc t information, pleas e vis it www.minds


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PDF M85000 85xxx-BRF-001-B 85000G 85xxx-001 85xxx- axi compliant ddr3 controller M85000 arm cortex a9 comcerto cortex a9 "ARM Cortex A9" CORTEX-A9 mindspeed 484 dyna image DDR31200
2013 - T3150

Abstract: No abstract text available
Text: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91 DDR3 Memory , Transcede 3xxx DDR3 SDRAM Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . , . . . . . . . . . . . .92 DDR3 SDRAM Device Interface Timing . . . . . . . . . . . . . . . . . . , Access Controller (GMAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 8.1 , 20.6.2.1 MAP Master Controller (MC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .


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PDF 843xx-DSH-001-A T3150
2012 - axi interconnect xilinx

Abstract: zynq XC7Z020CLG484
Text: . AXI was added to the Plot Graph descriptions. DDR3 was removed from Figure 2-6 and Figure 2-7. The , Controller OCM Interconnect CoreSight Components DAP SRAM/NOR NAND Quad SPI 32b GP AXI , Controller 12 13 14 15 8 9 10 11 4 5 6 7 0 1 2 3 IRQ High Performance AXI 32b/64b Slave Ports , between AXI masters in the programmable logic and the processing system's DDR3 memory. The main aim of , display controller . M_AXI_GP - This AXI master port interfaces with AXI slave IPs in PL through an AXI


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PDF Zynq-7000 ZC702 UG925 2002/96/EC Zynq-7000 axi interconnect xilinx zynq XC7Z020CLG484
Supplyframe Tracking Pixel