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LT1036CK Linear Technology IC VREG DUAL OUTPUT, FIXED POSITIVE REGULATOR, MBFM4, METAL CAN, TO-3, 3 PIN, Fixed Positive Multiple Output Standard Regulator
LTC4245IG Linear Technology LTC4245 - Multiple Supply Hot Swap Controller with I2C Compatible Monitoring; Package: SSOP; Pins: 36; Temperature Range: -40°C to 85°C
LTC2925CUF#PBF Linear Technology LTC2925 - Multiple Power Supply Tracking Controller with Power Good Timeout; Package: QFN; Pins: 24; Temperature Range: 0°C to 70°C
LTC3444EDD#PBF Linear Technology LTC3444 - Micropower Synchronous Buck-Boost DC/DC Converter for WCDMA Applications; Package: DFN; Pins: 8; Temperature Range: -40°C to 85°C
LTC4245IUHF#TRPBF Linear Technology LTC4245 - Multiple Supply Hot Swap Controller with I2C Compatible Monitoring; Package: QFN; Pins: 38; Temperature Range: -40°C to 85°C
LTC2925IUF#PBF Linear Technology LTC2925 - Multiple Power Supply Tracking Controller with Power Good Timeout; Package: QFN; Pins: 24; Temperature Range: -40°C to 85°C

atm header-error-check multiple bit Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
1994 - 622LY

Abstract: 822LY TNETA1500 19.44MHZ OSCILLATOR
Text: feature is deactivated by setting a bit in control register 1 (see Table 6). The ATM cells with , ATM cells transmitted. When a reset operation occurs, this bit is cleared (set to 0). The normal , When set to a high level, this bit causes the receive section to stop dropping ATM cells that contain , output FIFO. disable the dropping of ATM idle cells from the receive-data stream When this bit is set , bit is set, the receive section does not drop ATM unassigned cells from the receive-data stream. An


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PDF TNETA1500 52-MBIT/S SDNS021D 53-Byte 44-MHz 622LY 822LY TNETA1500 19.44MHZ OSCILLATOR
1994 - 622LY

Abstract: 822LY TNETA1500
Text: feature is deactivated by setting a bit in control register 1 (see Table 6). The ATM cells with , ATM cells transmitted. When a reset operation occurs, this bit is cleared (set to 0). The normal , When set to a high level, this bit causes the receive section to stop dropping ATM cells that contain , output FIFO. disable the dropping of ATM idle cells from the receive-data stream When this bit is set , bit is set, the receive section does not drop ATM unassigned cells from the receive-data stream. An


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PDF TNETA1500 52-MBIT/S SDNS021D 53-Byte 44-MHz 622LY 822LY TNETA1500
1994 - TNETA1500

Abstract: No abstract text available
Text: The ATM cells with multiple-bit header errors are dropped, unless a bit is set in control register 1 , that are detected in the headers of incoming ATM cells. When a reset operation is performed, this bit , disable the dropping of ATM cells with multiple-bit header errors When set to a high level, this bit , reset operation occurs, this bit is cleared. The normal operation of the TNETA1500 drops ATM cells that , of ATM idle cells from the receive-data stream When this bit is set, the receive section does not


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PDF TNETA1500 52-MBIT/S SDNS021C 53-Byte 44-MHz TNETA1500
1994 - Not Available

Abstract: No abstract text available
Text: The ATM cells with multiple-bit header errors are dropped, unless a bit is set in control register 1 , -byte header of ATM cells transmitted. When a reset operation occurs, this bit is cleared (set to 0). The , When set to a high level, this bit causes the receive section to stop dropping ATM cells that contain , output FIFO. disable the dropping of ATM idle cells from the receive-data stream When this bit is set , bit is set, the receive section does not drop ATM unassigned cells from the receive-data stream. An


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PDF TNETA1500 52-MBIT/S SDNS021D 53-Byte 44-MHz
Not Available

Abstract: No abstract text available
Text: RCKI, beginning with the first tw o bytes of the ATM header. W hen EN155 is high (155.52-M bit /s , is low (622.08-M bit /s operation), ATM cells are clocked into the TNETA1600 through T D 0 -T D 1 5 , least-significant bit . TW Ë I Transm it write enable. A low level on TW E enables the writing of ATM cells , eight bytes during 622.08-M bit /s operation) from the ATM -layer device without overflowing the transm , byte (or first two bytes in 622.08-M bit /s operation) of an incoming ATM cell on the transm it-cell


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PDF TNETA1600 08-MBIT/S 52-MBIT/S SDNS036
1996 - transmit g1

Abstract: STM 1 5A2 TD15 TNETA1600 TNETA1610 TNETA1611 TNETA151 ATM 38E
Text: bit . TWE I Transmit write enable. A low level on TWE enables the writing of ATM cells into , (or first two bytes in a 16- bit cell interface) of an ATM cell. Once the input FIFO receives a high , TNETA1600 SONET/SDH ATM RECEIVER/TRANSMITTER FOR 622.08-MBIT/S OR 155.52-MBIT/S OPERATION , Frames Carrying ATM Cells; Including: ­ Frame Scrambling/Descrambling ­ Pointer Processing ­ ATM-Cell , -Byte ATM Headers of Incoming ATM Cells D D D D Separate Serial Receive- and Transmit-Data


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PDF TNETA1600 08-MBIT/S 52-MBIT/S SDNS036 transmit g1 STM 1 5A2 TD15 TNETA1600 TNETA1610 TNETA1611 TNETA151 ATM 38E
1997 - TNETA1500A

Abstract: No abstract text available
Text: -byte ATM header of incoming ATM cells by using the HEC byte. This feature is deactivated by setting a bit , of ATM cells transmitted. When a reset operation occurs, this bit is cleared (set to 0). The normal , When set to a high level, this bit causes the receive section to stop dropping ATM cells that contain , FIFO. disable the dropping of ATM idle cells from the receive-data stream When this bit is set, the , bit is set, the receive section does not drop ATM unassigned cells from the receive-data stream. An


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PDF TNETA1500A 52-MBIT/S SDNS042A 53-Byte 44-MHz TNETA1500A
1997 - TNETA1500A

Abstract: 822LY 622LY
Text: ATM cells by using the HEC byte. This feature is deactivated by setting a bit in control register 1 (see Table 6). The ATM cells with multiple-bit header errors are dropped, unless a bit is set in , disable the dropping of ATM cells with multiple-bit header errors When set to a high level, this bit , reset operation occurs, this bit is cleared. The normal operation of the TNETA1500A drops ATM cells , dropping of ATM idle cells from the receive-data stream When this bit is set, the receive section does


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PDF TNETA1500A 52-MBIT/S SDNS042A 53-Byte 44-MHz TNETA1500A 822LY 622LY
TNETA1500A

Abstract: Alarm Clock by using ttl atm header-error-check multiple bit 622LY-221K ECE-A1AFS471
Text: ATM cells with multiple-bit header errors are dropped, unless a bit is set in control register 1 (see , detected in the headers of incoming ATM cells. When a reset operation is performed, this bit is cleared , device continues to transmit ATM cells that are inserted in an STS-3c/STM-1 frame. Internally, this bit , dropping of ATM cells with multiple-bit header errors When set to a high level, this bit causes the , occurs, this bit is cleared. The normal operation of the TNETA1500A drops ATM cells that contain


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PDF TNETA1500A 52-MBIT/S SDNS042 53-Byte 44-MHz 622LY-221K 822LY-221K) ECE-A1AFS471 ECE-V1AA471 TNETA1500A Alarm Clock by using ttl atm header-error-check multiple bit 622LY-221K ECE-A1AFS471
1999 - 4413

Abstract: IDT77155 IDT77V400 IDT77V500 IDT77V550 IDT79R36100 IDT79RV3041 IDT79RV4640 osam marking code
Text: bit is set in the Status Register. ISAMs are two ATM cells deep, so that the next ATM cell can , 3/1/99 - Section 2, Page 11 Section 2 2.3.2 ATM Cell (53 Byte) DPI Bit Ordering The following figures provide examples of the ATM Cell bit ordering in various DPI configurations. 53 Byte ATM Cell - (8 Bit Utopia) msb#7 3 3 lsb#0 GFC VPI 11 3 7 7 53 Byte ATM Cell - (4 , Byte ATM Cell - (8 Bit DPI) Port#0 msb#3 lsb#0 Port#1 msb#3 lsb#0 msb#7 Byte 0 3


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PDF IDT77V400 IDT77V500 4413 IDT77155 IDT77V550 IDT79R36100 IDT79RV3041 IDT79RV4640 osam marking code
1997 - TNETA1500A

Abstract: tsct 1000 622LY 822LY
Text: ATM cells by using the HEC byte. This feature is deactivated by setting a bit in control register 1 (see Table 6). The ATM cells with multiple-bit header errors are dropped, unless a bit is set in , disable the dropping of ATM cells with multiple-bit header errors When set to a high level, this bit , reset operation occurs, this bit is cleared. The normal operation of the TNETA1500A drops ATM cells , dropping of ATM idle cells from the receive-data stream When this bit is set, the receive section does


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PDF TNETA1500A 52-MBIT/S SDNS042A 53-Byte 44-MHz TNETA1500A tsct 1000 622LY 822LY
TNETA1500A

Abstract: No abstract text available
Text: setting a bit in control register 1 (see Table 6). The ATM cells with multiple-bit header errors are , incoming ATM cells. When a reset operation is performed, this bit is cleared (set to 0). The normal , EC byte in the 5 -byte header of ATM cel Is transmitted. When a reset operation occurs, this bit is , device continues to transmit ATM cells that are inserted in an STS-3c/STM-1 frame. Internally, this bit , extract ATM cells from the incoming STS-3c/STM-1 frame. Internally, this bit is logically ORed with the


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PDF TNETA1500A 52-MBIT/S 53-Byte 44-MHz
1995 - Not Available

Abstract: No abstract text available
Text: TNETA1570 ATM SEGMENTATION AND REASSEMBLY DEVICE WITH INTEGRATED 64- BIT PCI-HOST INTERFACE , PCBE7 PREQ64 PACK64 PAD0 TNETA1570 ATM SEGMENTATION AND REASSEMBLY DEVICE WITH INTEGRATED 64- BIT , , TEXAS 75265 TNETA1570 ATM SEGMENTATION AND REASSEMBLY DEVICE WITH INTEGRATED 64- BIT PCI-HOST , TNETA1570 ATM SEGMENTATION AND REASSEMBLY DEVICE WITH INTEGRATED 64- BIT PCI-HOST INTERFACE SDNS033B ­ JUNE , 655303 · DALLAS, TEXAS 75265 TNETA1570 ATM SEGMENTATION AND REASSEMBLY DEVICE WITH INTEGRATED 64- BIT


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PDF TNETA1570 64-BIT SDNS033B
1995 - TNETA1570

Abstract: No abstract text available
Text: asynchronous transfer mode ( ATM ) segmentation and reassembly (SAR) device with a 64- bit peripheral component , odd-parity bit over SEGDATA7 -SEGDATA0. ATM mode SEGPAR SEGPAR (TXPAR) is the odd-parity bit over , PHY mode RESPAR (TXPAR) is the odd-parity bit over RESDATA7 -RESDATA0. ATM mode RESPAR , 32- bit /64- bit PCI-bus interface. The interface to the ATM layer is the UTOPIA interface , the DMA entry is loaded into the internal transmit FIFO. The EOP bit in the ATM header is set for the


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PDF TNETA1570 64BIT SDNS033B 64-Bit TNETA1570
1995 - TNETA1570

Abstract: be46
Text: TNETA1570 ATM SEGMENTATION AND REASSEMBLY DEVICE WITH INTEGRATED 64- BIT PCI-HOST INTERFACE , ATM SEGMENTATION AND REASSEMBLY DEVICE WITH INTEGRATED 64- BIT PCI-HOST INTERFACE SDNS033B ­ JUNE , , TEXAS 75265 3 TNETA1570 ATM SEGMENTATION AND REASSEMBLY DEVICE WITH INTEGRATED 64- BIT PCI-HOST , · DALLAS, TEXAS 75265 TNETA1570 ATM SEGMENTATION AND REASSEMBLY DEVICE WITH INTEGRATED 64- BIT , SEGDATA7 ­ SEGDATA0. ATM mode SEGPAR (TXPAR) is the odd-parity bit over SEGDATA7 ­ SEGDATA0


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PDF TNETA1570 64-BIT SDNS033B TNETA1570 be46
1995 - PAD31

Abstract: t1624
Text: TNETA1570 ATM SEGMENTATION AND REASSEMBLY DEVICE WITH INTEGRATED 64- BIT PCI-HOST INTERFACE , ATM SEGMENTATION AND REASSEMBLY DEVICE WITH INTEGRATED 64- BIT PCI-HOST INTERFACE SDNS033B ­ JUNE , , TEXAS 75265 3 TNETA1570 ATM SEGMENTATION AND REASSEMBLY DEVICE WITH INTEGRATED 64- BIT PCI-HOST , · DALLAS, TEXAS 75265 TNETA1570 ATM SEGMENTATION AND REASSEMBLY DEVICE WITH INTEGRATED 64- BIT , SEGDATA7 ­ SEGDATA0. ATM mode SEGPAR (TXPAR) is the odd-parity bit over SEGDATA7 ­ SEGDATA0


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PDF TNETA1570 64-BIT SDNS033B PAD31 t1624
1995 - Not Available

Abstract: No abstract text available
Text: TNETA1570 ATM SEGMENTATION AND REASSEMBLY DEVICE WITH INTEGRATED 64Ć BIT PCIĆHOST INTERFACE , asynchronous transfer mode ( ATM ) segmentation and reassembly (SAR) device with a 64- bit peripheral component , €¢ 3 TNETA1570 ATM SEGMENTATION AND REASSEMBLY DEVICE WITH INTEGRATED 64Ć BIT PCIĆHOST INTERFACE , odd-parity bit over SEGDATA7 −SEGDATA0. ATM mode SEGPAR SEGPAR (TXPAR) is the odd-parity bit over , ATM SEGMENTATION AND REASSEMBLY DEVICE WITH INTEGRATED 64Ć BIT PCIĆHOST INTERFACE SDNS033B − JUNE


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PDF TNETA1570 SDNS033B 64-Bit
2005 - DSLAM configuration

Abstract: E300 MPC8360E MPC8548 vdsl2 phy "L2TP"
Text: , VLAN, RTP, PPP, PPPoE/oA, > Multiple QoS levels requiring different hierarchical lP or ATM traffic , , VLAN functionality, 32- bit PCI bridge, four DMA channels, USB Interface, ATM / POS PHY support up , over ATM is supported and allows ATM traffic to be distributed across multiple E1/T1 circuits , developed quickly Either/or 16- bit ATM UTOPIA L2 > Offers flexibility to accommodate new standards , DSLAM Line Card xDSL Subscriber Interfaces ATM /FR Line Card link layer protocols must also


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PDF MPC8360E 16-bit DSLAM configuration E300 MPC8360E MPC8548 vdsl2 phy "L2TP"
2005 - MSC8122

Abstract: E300 MPC8360E MPC8548 "network interface cards" Power consumption SGSN
Text: /or ATM 8/16- bit UTOPIA L2 Serial/Ethernet Console Backplane Key Benefits > The , MSC GMSC MGW MGW PSTN SGSN Multiplexing over ATM (IMA) protocol, which GGSN IP Network lur transports higher bandwidth traffic over multiple Tower lower bandwidth links. Using ATM as the B transport technology, these links will migrate to lub RNC lucs lups higher data rates, such as OC-3/STM-1 (to B aggregate the traffic from multiple Node Bs), Multiple


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PDF MPC8360E MSC8122 E300 MPC8360E MPC8548 "network interface cards" Power consumption SGSN
1994 - atm header error checking

Abstract: ATM circuit diagram atm recommendation availability ATM timing diagram UTOPIA Level 3 atm forum
Text: . There are multiple PHY layers defined for ATM (defined by ANSI, the ITU and the ATM Forum). Each of the , proposal is to leverage ATM development across multiple PHY types. The ATM-PHY interface is not a UNI , more octets for a 16- bit interface. © 1994 The ATM Forum 5 All Rights Reserved UTOPIA , In 16- bit mode, 54-octet cells are transferred between ATM and PHY layers. As for 8- bit mode, a , Data bus extension for 16- bit mode TxPrty[1:0] ATM to PHY O Data bus odd parity TxSOC


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PDF af-phy-0017 16-bit atm header error checking ATM circuit diagram atm recommendation availability ATM timing diagram UTOPIA Level 3 atm forum
2001 - hecs 450

Abstract: hecs 50 DSLAM VHDL key fob siemens
Text: Multiple CPE IMA Over T1/E1 ATM Access Side Figure 6 - IMA within the ATM Edge Switch IMA and CES , are slaved to the ATM device. UTOPIA Level 2 allows the user to connect multiple devices. HEC , ATM service where constant bit rate virtual circuits emulate an end-toend T1 or E1 circuit. CPE - , .5 What is ATM ?.5 Combining Inverse Multiplexing and ATM .5


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PDF MT90220 MT90221 hecs 450 hecs 50 DSLAM VHDL key fob siemens
2001 - 77V400

Abstract: 77V500 IDT77500 IDT77V011 IDT77V012 IDT77V400 IDT77V500 V400 OD031
Text: multiple SwitchStar chipsets to create an ATM core switch. Surrounding the core switch are additional , Output Port from the Cell-Bus to transmit ATM traffic to multiple PHYs. The IDT77V011 accomplishes this , transmitting the same ATM cell to multiple PHYs. If a system needs to support the capability to transmit the , to that Output Port. Multicast can only transmit an individual ATM cell once to multiple Output , follows: CBRCLK3 = ( Bit Rate of CBR VC service * number of Sub-ports) / ( ATM Cell Length in Bytes


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PDF 16x16 IDT77500/IDT77V400s. IDT77V500s IDT77V400s 77V400 77V500 IDT77500 IDT77V011 IDT77V012 IDT77V400 IDT77V500 V400 OD031
DPRAM

Abstract: XCV600E IMA-32 XC4085XLA
Text: with the ATM Forum Inverse Multiplexer for ATM (IMA) specification · Supports the 8/16 bit UTOPIA , converting a single ATM stream into multiple lower speed ATM streams for transmission over independent , master to one or multiple PHY devices. These PHY devices encapsulate the ATM cell data for transmission , receiving ATM cell data over multiple T1/E1 links. The IMA Mux extracts the realigned cell data from the , ATM bus for IMA32. When the signal is high, 16 bit UTOPIA operation is enabled. Set this signal low


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PDF IMA-32 4000XLA 4085XLA09BG352C 4000XLA DPRAM XCV600E XC4085XLA
1999 - XCV600E-6BG432C

Abstract: "Dual-Port RAM" DPRAM XC4085XLA-09BG352C IMA-32 XC4000XLA XC4085XLA XC4085XLA09BG352C XCV600E
Text: Forum Inverse Multiplexer for ATM (IMA) specification Supports the 8/16 bit UTOPIA Level 2 , converting a single ATM stream into multiple lower speed ATM streams for transmission over independent , Utopia Level 2 master to one or multiple PHY devices. These PHY devices encapsulate the ATM cell data , occur when receiving ATM cell data over multiple T1/E1 links. The IMA Mux extracts the realigned cell , Signal which selects the width of the ATM bus for IMA32. When the signal is high, 16 bit UTOPIA


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PDF ima32 IMA-32 XC4000XLA XC4085XLA09BG352C 4000XLA XCV600E-6BG432C "Dual-Port RAM" DPRAM XC4085XLA-09BG352C XC4000XLA XC4085XLA XC4085XLA09BG352C XCV600E
ATM machine working circuit diagram

Abstract: T90500 ECTF PVC trunking
Text: distributed among multiple chassis in the system, the Hybrid TDM & ATM Switching Platforms design of a , channel boundary is required and only the continuous bit or byte stream is used for assembling ATM AAL1 , multiple ATM AAL1 Cells with a range of the VCI (Virtual Channel Identifier), or the VPI (Virtual Path , to minimizing the packetization delay in an ATM network by aggregating multiple circuits (or phone , interfaces for an ATM uplink connection application, the 16- bit Non-Multiplexed CPU interface, a primary


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