The Datasheet Archive

Top Results (6)

Part Manufacturer Description Datasheet Download Buy Part
LTC2391IUK-16#TRPB Linear Technology 16-Bit, 250ksps SAR ADC with 94dB SNR, QFN, 48 Pins, Tape and Reel
LT1529-5DWF#MILDWF Linear Technology LT1529 - 3A Low Dropout Regulators with Micropower Quiescent Current and Shutdown; Pins: 5
LT1120MJ8/883 Linear Technology LT1120 - Micropower Regulator with Comparator and Shutdown; Package: CERDIP; Pins: 8; Temperature: Military
LT1490CMS8#PBF Linear Technology LT1490 - Dual and Quad Micropower Rail-to-Rail Input and Output Op Amps; Package: MSOP; Pins: 8; Temperature Range: 0°C to 70°C
LT1490CMS8#TRPBF Linear Technology LT1490 - Dual and Quad Micropower Rail-to-Rail Input and Output Op Amps; Package: MSOP; Pins: 8; Temperature Range: 0°C to 70°C
LT1491CS#PBF Linear Technology LT1491 - Dual and Quad Micropower Rail-to-Rail Input and Output Op Amps; Package: SO; Pins: 14; Temperature Range: 0°C to 70°C

and pin diagram of IC 7476 Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
IC 7476

Abstract: 7476 truth table circuit diagram with IC 7476 7476 IC J-K Flip-Flop 7476 7476 logic diagram 7476 Connection diagram 7476 ttl 7476 J-K Flip-Flop logic ic 7476
Text: FAIRCHILD TTL/SSI . 9N76/5476, 7476 DUAL JK MASTER/SLAVE FLIP-FLOP WITH SEPARATE PRESETS, CLEARS AND CLOCKS DESCRIPTION - The TTL/SSI 9N76/5476, 7476 is a Dual JK Master/Slave flip-flop with separate , pulse. The clock pulse also regulates the state of the coupling transistors which connect the master and , slave. LOGIC AND CONNECTION DIAGRAM DIP (TOP VIEW) K, Q, 0, GND l<2 Q2 Q2 h FLATPAK (TOP VIEW) K, Q, Q , level Clear and preset are independent of clock TRUTH TABLE t n tn+1 J K Q L L On L H L H L H H H Qn


OCR Scan
PDF 9N76/5476, 11N76/7476 400ft IC 7476 7476 truth table circuit diagram with IC 7476 7476 IC J-K Flip-Flop 7476 7476 logic diagram 7476 Connection diagram 7476 ttl 7476 J-K Flip-Flop logic ic 7476
logic ic 7476 pin diagram

Abstract: and pin diagram of IC 7476 logic ic 7476 flip-flop pin diagram 7476 truth table pin diagram for IC 7476 pin configuration of 74LS76 IC IC 74LS76 logic ic 74LS76 pin diagram 74Ls76 truth table 74LS80
Text: f the C lock fo r predictab le operation. e. The J and K inputs of the 7476 and 74H76 m ust be , 54/ 7476 54H/74H76 54LS/74LS76 DESCRIPTION The "76'' is a Dual JK Flip-Flop w ith individ ual J, K, Clock, Set and Reset inputs. The 7476 and 74H76 are positive pulse triggered flip-flops. JK inform ation , PACKAGES PIN CONF. Fig A Fig A Fig A Fig A Fig A Fig A (See Section 9 for further Package and Ordering , N7476F PIN CONFIGURATION Flatpak S5476W [T H ]o , m q i INPUT AND OUTPUT LOADING AND


OCR Scan
PDF 54H/74H76 54LS/74LS76 74H76 74LS76 54H/74H 54S/74S 54LS/74LS logic ic 7476 pin diagram and pin diagram of IC 7476 logic ic 7476 flip-flop pin diagram 7476 truth table pin diagram for IC 7476 pin configuration of 74LS76 IC IC 74LS76 logic ic 74LS76 pin diagram 74Ls76 truth table 74LS80
pin diagram of 7476

Abstract: 7476 J-K Flip-Flop PIN CONFIGURATION 7476 7476 FUNCTION TABLE 7476 7476 PIN DIAGRAM Jk 74ls76 pin out 74LS76 flip-flop 74ls76 7476 PIN DIAGRAM input and output
Text: Clock for predictable operation. 3. The J and K inputs of the 7476 must be stable while the Clock is HIG , Signetics 7476 , LS76 Flip-Flops Dual J-K Flip-Flop Product Specification Logic Products DESCRIPTION The '76 is a dual J-K flip-flop with Individual J, K, Clock, Set and Reset inputs. The 7476 is , Flip-Flops 7476 , LS76 LOGIC DIAGRAM FUNCTION TABLE INPUTS OPERATING MODE SD Asynchronous set , e and duration of the short circuit should not exceed one second. 4. W ith the Clock input grounded


OCR Scan
PDF 74LS76 1N916, 1N3064, 500ns 500ns pin diagram of 7476 7476 J-K Flip-Flop PIN CONFIGURATION 7476 7476 FUNCTION TABLE 7476 7476 PIN DIAGRAM Jk 74ls76 pin out flip-flop 74ls76 7476 PIN DIAGRAM input and output
ci 7476

Abstract: 7476 PIN DIAGRAM pin diagram of 7476 jk flip flop 7476 pin diagram of ttl 7476 7476 7476 PIN DIAGRAM input and output 7476 ttl 7476 J-K Flip-Flop LS 7476
Text: , Clock, Set and Reset inputs. The 7476 is positive pulse-triggered. JK information is loaded into the , understood tobe40*iA l,H and -1.6mA l|L, and a74LS unit load (LSul) is20/uA lIH and -0.4mA l(L. PIN , stable one set-up time prior to the negative edge of the Clock for predictable operation. 3. The J and K inputs of the 7476 must be stable while the Clock is HIGH for conventional operation. December 4, 1985 , VCc = VCc MAX + 0.5V. Not more than one output should be shorted at a time and duration of the short


OCR Scan
PDF 74LS76 1N916, 1N3064, 500ris 500ns ci 7476 7476 PIN DIAGRAM pin diagram of 7476 jk flip flop 7476 pin diagram of ttl 7476 7476 7476 PIN DIAGRAM input and output 7476 ttl 7476 J-K Flip-Flop LS 7476
PIN CONFIGURATION 7476

Abstract: pin diagram of 7476 7476 PIN DIAGRAM 7476 FUNCTION TABLE pin diagram of ttl 7476 7476 pin configuration LS 7476 7476 PIN DIAGRAM input and output 74LS76 J-K Flip-Flop 7476
Text: the Clock for predictable operation. 3. The J and K inputs of the 7476 must be stable while the Clock , DESCRIPTION The '76 is a dual J-K flip-flop with individual J, K, Clock, Set and Reset inputs. The 7476 is , l|H and -0 .4 m A lIL. PIN CONFIGURATION LOGIC SYMBOL LOGIC SYMBOL (IEE/IEC) 76 LS76 CP , duration of the short circuit should not exceed one second. 4. With the Clock input grounded and all , Flip-Flops 7476 , LS76 TEST CIRCUITS AND WAVEFORMS NEGATIVE PULSE VM 10% / tT H lW ) * -lT L H


OCR Scan
PDF 74LS76 1N916, 1N3064, 500ns 500ns PIN CONFIGURATION 7476 pin diagram of 7476 7476 PIN DIAGRAM 7476 FUNCTION TABLE pin diagram of ttl 7476 7476 pin configuration LS 7476 7476 PIN DIAGRAM input and output J-K Flip-Flop 7476
pin diagram of 7476

Abstract: PIN CONFIGURATION 7476 74LS76 7476 PIN DIAGRAM input and output 7476 FUNCTION TABLE Jk 74ls76 pin out 7476 J-K Flip-Flop 7476 pin configuration TTL 7476 7476 logic diagram
Text: DESCRIPTION The '76 is a dual J-K flip-flop with individual J, K, Clock, Set and Reset inputs. The 7476 is , 81501 Signetics Logic Products Product Specification Flip-Flops 7476 , LS76 LOGIC DIAGRAM , stable one set-up time prior to the negative edge of the Clock for predictable operation. 3. The J and K inputs of the 7476 must be stable while the Clock is HIGH for conventional operation. December 4, 1965 , than one output should be shorted at a time and duration of the short circuit should not exceed one


OCR Scan
PDF 74LS76 1N916, 1N3064, 500ns 500ns pin diagram of 7476 PIN CONFIGURATION 7476 7476 PIN DIAGRAM input and output 7476 FUNCTION TABLE Jk 74ls76 pin out 7476 J-K Flip-Flop 7476 pin configuration TTL 7476 7476 logic diagram
jk flip flop 7476

Abstract: 7476 PIN DIAGRAM 7476 7476 ttl TTL 74ls76 7476 PIN DIAGRAM input and output pin diagram of 7476 PIN CONFIGURATION 7476 pin diagram of ttl 7476 7476 J-K Flip-Flop
Text: predictable operation. 3. The J and K inputs of the 7476 must be stable while the Clock is HIGH for , , Clock, Set and Reset inputs. The 7476 is positive pulse-triggered. JK information is loaded into the , understood to be 40>iA l,H and -1.6mA l,L. and a 74LS unit load (LSul) is 20juA l)H and -0.4mA l|L. 7476 , Flip-Flops 7476 , LS76 LOGIC DIAGRAM ld02900s FUNCTION TABLE OPERATING MODE INPUTS OUTPUTS SD Rd , should be shorted at a time and duration of the short circuit should not exceed one second. 4. With the


OCR Scan
PDF 74LS76 1N916, 1N3064, 500ns jk flip flop 7476 7476 PIN DIAGRAM 7476 7476 ttl TTL 74ls76 7476 PIN DIAGRAM input and output pin diagram of 7476 PIN CONFIGURATION 7476 pin diagram of ttl 7476 7476 J-K Flip-Flop
2007 - IC 7476

Abstract: INTERNAL DIAGRAM OF IC 7476 IC 7476 function applications IC 7476 circuit diagram with IC 7476 assignment on bluetooth 7476 IC 7476 Connection diagram PVH071902 of IC 7476 in file
Text: OUT Short circuit or overload at one of the outputs IN FS 7476 _en_02 Failsafe, analog and , Analog Inputs and 2 Analog Outputs AUTOMATIONWORX Data Sheet 7476 _en_02 © PHOENIX CONTACT - 10/2007 , all outputs: 8 A Short-circuit and overload protected outputs Status indicators Features of , or current signals Connection of sensors in 2 and 3-wire technology Current measuring range of 0 mA , of actuators in 2 and 3-wire technology Current measuring range of 0 mA to 20 mA Voltage measuring


Original
PDF Bm/39 IC 7476 INTERNAL DIAGRAM OF IC 7476 IC 7476 function applications IC 7476 circuit diagram with IC 7476 assignment on bluetooth 7476 IC 7476 Connection diagram PVH071902 of IC 7476 in file
7476 ic specifications

Abstract: ic 7476 IC 7476 JK logic diagram of ic 7476 7476 logic diagram 7476 ic
Text: TEXAS 75 26 5 TTL SN 5476, SN 7476 DUAL J-K FLIP FLOPS WITH PRESET AND CLEAR logic diagrams , 75 26 5 SN 5476, SN 54LS 76A , SN 7476 , S N 74 LS7 6A DUAL J K FLIP FLOPS WITH PRESET AND CLEAR , /IEEE S td 9 1 - 1 9 8 4 and IEC P u b lic a tio n 6 1 7 -1 2 schematics of inputs and outputs 76 , D e v ic e s logic sym bols* SN 5476, SN 54LS76A , SN 7476 , SN 74 LS 7 6A DUAL J-K FLIP-FLOPS WITH PRESET AND CLEAR schematics of inputs and outputs (continued) 'L S 7 6 A E Q U IV A L E N T O F


OCR Scan
PDF SN547G, SN54LS76A, SN7476, SN74LS76A 7476 ic specifications ic 7476 IC 7476 JK logic diagram of ic 7476 7476 logic diagram 7476 ic
7476 truth table

Abstract: 74ls76 jk flip-flop logic symbol and truth table jk flip flop 7476 7476 PIN DIAGRAM pin diagram of 7476 7476 PIN DIAGRAM input and output S5476F PIN CONFIGURATION 7476 7476 pin configuration 7476
Text: operation. e. The J and K inputs of the 7476 and 74H76 must be stable while the Clock is HIGH for , 54/ 7476 54H/74H76 54LS/74LS76 LOGIC SYMBOL DESCRIPTION The "76" is a DualJK Flip-Flop with individual J, K, Clock, Set and Reset inputs. The 7476 and 74H76 are positive pulse triggered flip-flops. JK information is loaded into the master while the Clock is HIGH and transferred to the slave on the HIGH-to-LOW Clock transition. The J and K inputs must be stable while the Clock is HIGH for conventional operation


OCR Scan
PDF 54H/74H76 54LS/74LS76 74H76 74LS76 7476 truth table 74ls76 jk flip-flop logic symbol and truth table jk flip flop 7476 7476 PIN DIAGRAM pin diagram of 7476 7476 PIN DIAGRAM input and output S5476F PIN CONFIGURATION 7476 7476 pin configuration 7476
7476 truth table

Abstract: No abstract text available
Text: 11-19 20-70 71 72 73 74-76 77 78-80 Information Binary outputs of rows 9 through 1, (MSB at , 2526-N,! DESCRIPTION PIN CONFIGURATION The 2526 is a high speed 5 184-bit Static Read-Only , purpose use. This device has TTL compatible inputs and outputs and requires+5V and -12 V power supplies. A READ input controls the entry of data from the ROM into output latches. Three-state outputs allow , Address 10 3 Address 9 BLOCK DIAGRAM Address 1 [7 O u tp u t Enable Address 5 VGG O u tp


OCR Scan
PDF 2526-N, 184-bit 64x9x9 512x9 0I0I00I0I 0I00I0T0T NQISM3AN03 S33dWVX3 N-92Se 7476 truth table
2007 - IC 7476

Abstract: features of ic 7476 applications IC 7476 of Ic 7476 transistor 076 7476 ic
Text: and Storage Temperature Range Semelab Plc reserves the right to change test conditions, parameter limits and package dimensions without notice. Information furnished by Semelab is believed to be both accurate and reliable at the time of going to press. However Semelab assumes no responsibility for any , furnished by Semelab is believed to be both accurate and reliable at the time of going to press. However , PAD 3 = Collector ABSOLUTE MAXIMUM RATINGS TCASE = 25°C unless otherwise stated VCBO VCEO VEBO IC


Original
PDF 2N2857XCSM IC 7476 features of ic 7476 applications IC 7476 of Ic 7476 transistor 076 7476 ic
74LS76P

Abstract: 74LS76D IC 7476 pinout logic ic 7476 flip-flop pin diagram and pin diagram of IC 7476 logic ic 7476 pin diagram 7476PC 74H76 74LS76 pinout IC 74LS76
Text: 76 CO NNECTIO N DIAGRAM PINOUT A /54/ 7476 0 / / o / c ^ ^S4H/74H76 Gf / ci 7 ^ 54LS/74LS76£ v / 6 / 6 DUAL JK FLIP-FLOP (With Separate Sets, Clears and Clocks) DESCRIPTION - The '76 and 'H76 are dual JK m aster/slave flip -flo p s with separate Direct Set, D irect Clear and Clock Pulse inputs , also regulates the state of the coupling transistors which connect the master and slave sections. The sequence of operation is as follows: 1) isolate slave from master; 2) enter inform ation from J and K


OCR Scan
PDF S4H/74H76 54LS/74LS76£ 54/74H 54/74LS CLS76) 74LS76P 74LS76D IC 7476 pinout logic ic 7476 flip-flop pin diagram and pin diagram of IC 7476 logic ic 7476 pin diagram 7476PC 74H76 74LS76 pinout IC 74LS76
2011 - TS820600T

Abstract: TYN608RG TS820-600B TS8206 TS820-600BTR TS820-600T TS820-600 TYN608 scr TYN608 ts820600b
Text: . Relative variation of gate trigger Figure 8. and holding current versus junction temperature 6.0 5.5 IGT , versus Figure 12. Non-repetitive surge peak on-state number of cycles current and corresponding values of , Table 5. Added TO-220FPAB package. Removed 700 V and 1000 V products. Changes 12/13 Doc ID 7476 , 's terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the , choice, selection or use of the ST products and services described herein. No license, express or implied


Original
PDF TN805, TN815 TS820, TYN608 TS820-6d TS820600T TYN608RG TS820-600B TS8206 TS820-600BTR TS820-600T TS820-600 TYN608 scr TYN608 ts820600b
2011 - TS820 600T

Abstract: No abstract text available
Text: Figure 6. K=[Zth(j-a)/Rth(j-a)] 1E+0 1E-1 Relative variation of gate trigger current and , cycles current and corresponding values of I2t ITSM(A), I2t (A2s) ITSM(A) 1000 100 Tj , , without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products


Original
PDF TN805, TN815 TS820, TYN608 TS820-600H TN805-600B TN815-x00B TS820-600B TS820 600T
2010 - TYN608

Abstract: TYN808 SCR 600V, 8A, 15mA Igt 7476 TN805 TN815 TS820 TYN08 TYN1008
Text: )/Rth(j-a)] 1E+0 1E-1 Relative variation of gate trigger current and holding current versus , 1E+2 -40 5E+2 -20 Relative variation of gate trigger Figure 8. and holding current versus , versus Figure 12. Non-repetitive surge peak on-state number of cycles current and corresponding values , conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products , , selection or use of the ST products and services described herein. No license, express or implied, by


Original
PDF TN805, TN815, TS820 TYN608, TYN808, TYN1008 TN805-xxxB TN815-xxxB TS820-xxxB TN805-xxxH TYN608 TYN808 SCR 600V, 8A, 15mA Igt 7476 TN805 TN815 TS820 TYN08 TYN1008
PIN CONFIGURATION 7476

Abstract: dc to dc chopper by thyristor DIODE D180 thyristor control ic with current sense thyristor thyristor bridge circuit Thyristor PIN CONFIGURATION Half-Controlled single phase bridge rectifier pin configuration
Text: interdigitated fast thyristor, central gate phase control thyristor limiting repetitive peak forward and , solder pin flat base cable TO 220 case disc B C E F T 4.Letter maximum turn-off time 8 µs , 5.Letter B C F G H B C F L M N 58 critical rate of rise forward voltage , for selfcommutated converters: critical rate of rise of forward voltage according immediately after to DIN IEC turn-off: 747-6 : 50 V/µs 50 V/µs 500 V/µs 500 V/µs 1000 V/µs 1000 V/µs 500 V


Original
PDF
IC 7476 function

Abstract: 41814 T1052
Text: repetitive peak forward off-state and reverse voltages non repetitive peak forward off-state voltage non , surge current Grenzlastintegral Pt-value Kritische Stromsteilheit critical rate of rise of on-state current "0 5 67% @RM, f = 50 Hz Kritische Spannungssteilheit critical rate of rise of , , RGK 2 10 n IL forward off-state and reverse Currents gate controlled delay time circuit , /Delivery for larger quantities on request 1) Werte nach DIN IEC 747-6 (ohne vorausgehende Kommutierung


Original
PDF T1052 IC 7476 function 41814
74573

Abstract: 74574 7486 XOR GATE 7486 full adder latch 74574 7408, 7404, 7486, 7432 7490 Decade Counter 74373 cmos dual s-r latch 2 bit magnitude comparator using 2 xor gates design a BCD counter using j-k flipflop
Text: Semiconductor Logic Device Cross-Reference Here is a comprehensive cross-reference of TTL and , UK ). Tables of both TTL and CMOS devices are provided along with tables grouping chips with the , descriptions of the chips are taken from manufacturer's data sheets and other sources; these descriptions are only a brief indication of the generic functionality of that chip and a particular chip may have , 7476 7483 7485 7486 7490 7493 74121 2 of 12 Function Quad 2-Input NAND Gate Quad 2


Original
PDF
co-600v

Abstract: CO-624VD 12KHZ CO-624V-D CO624V
Text: of the 3048A. The equivalent sideband level of the integrated phase noise was ­ 74.76 dBc. Per the , degrees 13 RMS jitter in seconds The sideband level of ­ 74.76 dBc for the integration of the , VCXO August 11, 1999 For applications requiring a PECL or ECL VCXO having an RMS jitter of < 1.0 ps within the bandwidth of 12KHz to 20 MHz, VI is offering our CO-600V Series. The phase noise on two VCXO's of VI's model CO-624V-D @ 155.52 MHz were measured on the HP 3048A Phase Noise Measurement


Original
PDF CO-600V 12KHz CO-624V-D CO-624VD CO-624V-D CO624V
1998 - din 41814

Abstract: 41814 T1052
Text: the specification of the products for which a warranty is granted exclusively pursuant the terms and conditions of the supply agreement. There will be no guarantee of any kind for the product and its , the suitability of the product for the intended application and the completeness of the product data , repetitive peak forward off-state and reverse voltages non repetitive peak forward off-state voltage non , surge current Grenzlastintegral Pt-value Kritische Stromsteilheit critical rate of rise of


Original
PDF T1052 din 41814 41814
d4094bc

Abstract: 4094BC 4094bcw
Text: . Connection Diagram Pin A ssignm ents fo r DIP and SOIC STROBE - DATA - CLOCK - Q 1Q2 - Q 31 2 3 4 5 6 7 , . w w w.fairchildsemi. com 4 CD4094BC Tim ing Diagram Test Circuits and Tim ing Diagram s , T TH E EXPRESS W R ITTEN AP P R O VA L OF TH E PR ESID ENT OF FAIRCHILD S EM IC O N D U C TO R C O R , -Bit Shift Register/Latch with 3-STATE Outputs General Description T h e C D4094BC consists of an 8-bit shift register and a 3STATE 8-bit latch. Data is shifted serially through the shift register on th e


OCR Scan
PDF CD4094BC CD4094BC D4094BC 4094BC 4094bcw
2526N

Abstract: signetics 2526 7476 truth table pin diagram of 7476 pin diagram of ttl 7476 PIN CONFIGURATION 7476 7x9 decoder 7476 PIN DIAGRAM 7476 PIN DIAGRAM input and output pin diagram decoder 7476
Text: requires +5V and -12V power supplies. A READ input controls the entry of data from the ROM into output , DIAGRAM BIPOLAR COMPATIBILITY All inputs of the 2526 can be driven directly by standard bipolar , rating only and functional operation of the device at these or any other conditions above those indicated , sent to the memory matrix; and the stored memory data I» moved to the date inputs of the output R8 , variation of 0°C to +70°C. Actual input requirements with respect to Vcc are V)H » Vcc - 1.85V and V|L -


OCR Scan
PDF 184-bit 64x9x9 512x9 2526N signetics 2526 7476 truth table pin diagram of 7476 pin diagram of ttl 7476 PIN CONFIGURATION 7476 7x9 decoder 7476 PIN DIAGRAM 7476 PIN DIAGRAM input and output pin diagram decoder 7476
BT 151 thyristor

Abstract: BT thyristor 151 500 R BT thyristor thyristor BT bsm 25 op 120-b2
Text: sym m etrically blocking A thyristor limiting average forw ard 930 current (A) at tc= 85° C Ceram ic disc W C eram ic disc P 1 Epoxy disc 19 mm high 4 Epoxy disc 35 mm high 6 Epoxy disc 8 mm high 7 Epoxy , echanical construction: m etric thread wire m etric thread cable stud solder pin flat-base cable press-pack , thyristor limiting repetitive peak fo r ward and reverse off-state voltage in 100 V, 18 = 1800 V (A , construction cathode: anode: cable m etric thread solder pin m etric thread cable flat base TO 220 case disc


OCR Scan
PDF 80oltage BT 151 thyristor BT thyristor 151 500 R BT thyristor thyristor BT bsm 25 op 120-b2
1999 - TT46N

Abstract: No abstract text available
Text: technical departments will have to evaluate the suitability of the product for the intended application and , exclusively pursuant the terms and conditions of the supply agreement. There will be no guarantee of any kind for the product and its characteristics. Should you require product information in excess of the , conclusion of Quality Agreements; - to establish joint measures of an ongoing product survey, and that we may make delivery depended on the realization of any such measures. If and to the extent necessary


Original
PDF
Supplyframe Tracking Pixel