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Top Results (6)

Part Manufacturer Description Datasheet Download Buy Part
LTC4000IGN#TRPBF Linear Technology LTC4000 - High Voltage High Current Controller for Battery Charging and Power Management; Package: SSOP; Pins: 28; Temperature Range: -40°C to 85°C
LTC4000EUFD#PBF Linear Technology LTC4000 - High Voltage High Current Controller for Battery Charging and Power Management; Package: QFN; Pins: 28; Temperature Range: -40°C to 85°C
LTC4000IUFD-1#TRPBF Linear Technology LTC4000-1 - High Voltage High Current Controller for Battery Charging with Maximum Power Point Control; Package: QFN; Pins: 28; Temperature Range: -40°C to 85°C
LTC4000IGN#PBF Linear Technology LTC4000 - High Voltage High Current Controller for Battery Charging and Power Management; Package: SSOP; Pins: 28; Temperature Range: -40°C to 85°C
LTC4000IUFD-1#PBF Linear Technology LTC4000-1 - High Voltage High Current Controller for Battery Charging with Maximum Power Point Control; Package: QFN; Pins: 28; Temperature Range: -40°C to 85°C
LTC4000IUFD#PBF Linear Technology LTC4000 - High Voltage High Current Controller for Battery Charging and Power Management; Package: QFN; Pins: 28; Temperature Range: -40°C to 85°C

Xc 4000 FPGA family Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
1996 - Xc 4000 FPGA family

Abstract: XC5000 HQ240 4006-E Logic Gates XC4005E PHYSICAL 32X8 sram 4006E 3300 XL 4003E
Text: Fall 1996 Seminar FPGA Solutions Fall Seminar - FPGA - 1 E 00 40 0EX XC 400 XC 00 95 XC XACT Xilinx FPGA Solutions XC5000 Family Description Max. Logic Gates XC4000 , applications Fall Seminar - FPGA - 14 E 00 40 0EX XC 400 XC XC4000EX Family XACT 4028EX , Seminar - FPGA - 3 E 00 40 0EX XC 400 XC High Density FPGA Leadership XACT XC4000 Series , functions Fall Seminar - FPGA - 6 E 00 40 0EX XC 400 XC XACT XC4000 Series CLB Architecture


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PDF XC5000 XC4000 3K125K XC5000 3K23K XC4000EX XC4000E XC5200 Xc 4000 FPGA family HQ240 4006-E Logic Gates XC4005E PHYSICAL 32X8 sram 4006E 3300 XL 4003E
1996 - FIR FILTER implementation xilinx

Abstract: fir filter design using vhdl fpga frame buffer vhdl examples USB Prog ISP 172 XC9572 XC5200 EPM7160E-10 XC95108 LogiCore xc4000 fir LIC AGENTS DATA
Text: FPGA - 1 E 00 40 0EX XC 400 XC 00 95 XC XACT Xilinx FPGA Solutions XC5000 Family , Depth X Width Fall Seminar - FPGA - 10 32X32 E 00 40 0EX XC 400 XC XC4000E Family , XC5200 25K 125K Max. Logic Gates Fall Seminar - FPGA - 3 E 00 40 0EX XC 400 XC High , I/O Fall Seminar - FPGA - 4 E 00 40 0EX XC 400 XC XC4000 Series: High Density , Specific E 00 40 0EX XC 400 XC XACT XC4000 Series FPGA Architecture System Integration


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PDF XC9500 XC5200 XC4000E/EX FIR FILTER implementation xilinx fir filter design using vhdl fpga frame buffer vhdl examples USB Prog ISP 172 XC9572 XC5200 EPM7160E-10 XC95108 LogiCore xc4000 fir LIC AGENTS DATA
1996 - xilinx xc95108 jtag cable Schematic

Abstract: xilinx FPGA IIR Filter XC95144 PQ100 Altera CPLD PCMCIA XC95144 xilinx xc5 XC95108 XC9500 xc9572 usb EPM7160E-10
Text: Seminar - CPLD - 17 Fall 1996 Seminar FPGA Solutions Fall Seminar - FPGA - 1 E 00 40 0EX XC 400 XC 00 95 XC XACT Xilinx FPGA Solutions XC5000 Family Description Max. Logic , Seminar - FPGA - 10 Fall Seminar - FPGA - 5 32X32 E 00 40 0EX XC 400 XC XC4000E Family , FPGAs XC5200 25K 125K Max. Logic Gates Fall Seminar - FPGA - 3 E 00 40 0EX XC 400 XC , 256 256 - 544 Fall Seminar - FPGA - 4 Fall Seminar - FPGA - 2 E 00 40 0EX XC 400 XC


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PDF Intro500 XC5200 XC4000E/EX xilinx xc95108 jtag cable Schematic xilinx FPGA IIR Filter XC95144 PQ100 Altera CPLD PCMCIA XC95144 xilinx xc5 XC95108 XC9500 xc9572 usb EPM7160E-10
XC17S20XLV08C

Abstract: XC17S20V08C XC17S05V08C XC17S30V08C
Text: (Version 1.1) Product Specification Introduction Spartan SPROM Features The Spartan™ family , interconnected. All devices are compatible and can be cascaded with other members of the family . Serial , Spartan FPGA devices Simple interface to the Spartan device requires only one user I/O pin Cascadable , ­ grammers. Spartan FPGA Compatible Spartan SPROM Configuration Bits XCS05 XC17S05 65,536 , . FPGA Master Serial Mode Summary The I/O and logic functions of the Configurable Logic Block (CLB) and


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PDF 5M-1982. MS-013-AC XC17S20XLV08C XC17S20V08C XC17S05V08C XC17S30V08C
1765DPC

Abstract: XC17128D Series XC17128DPC XC1765D Series XC17256DDD8M 3164A 1765DPC20C XC3042 part marking XC17128DPC20I XC17128DPD8C
Text: JIXILINX June 1, 1996 (Version 1.0) XC1700D Family of Serial Configuration PROMs Product Specification Features Extended family of one-time programmable (OTP) bit-serial read-only memories used for , edge on the clock input Simple interface to the FPGA requires only one user I/O pin Cascadable for , compatibility with different FPGA solutions XC17128D or XC17256D supports XC4000 fast configuration mode (12.5 , manufacturers. Description The XC1700 family of serial configuration PROMs (SCPs) provides an easy-to-use


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PDF XC1700D XC17128D XC17256D XC4000 1736D XC1718D XC1718L XC1736D XC1765D XC1765L 1765DPC XC17128D Series XC17128DPC XC1765D Series XC17256DDD8M 3164A 1765DPC20C XC3042 part marking XC17128DPC20I XC17128DPD8C
XC17256EV08I

Abstract: XC1765ELS08I XC17128EV08I XC1765ES08I XC1736ES08I XC1736EV08I XC1765EV08I xc17256x xc17128e-v08i XC1765ELS08C
Text: £ XILINX XC1700E Family of Serial Configuration PROMs January 28, 1998 (Version 1.0) Preliminary Product Specification Features Description • The XC1700 family of serial configuration PROMs (SCPs) provides an easy-to-use, cost-effective method for storing Xilinx FPGA , programmable (OTP) read-only memory designed to store configuration bitstreams of Xilinx FPGA devices Simple interface to the FPGA requires only one user I/O pin Cascadable for storing longer or multiple bitstreams


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PDF XC1700E XC1700 17256E XC1736E XC1765E XC1765X XC17128E XC17128X XC17256E XC17256X XC17256EV08I XC1765ELS08I XC17128EV08I XC1765ES08I XC1736ES08I XC1736EV08I XC1765EV08I xc17256x xc17128e-v08i XC1765ELS08C
XC1736ES08I

Abstract: XC17128EV08I XC17128EV08C XC1765ES08I XC17256EV08I XC17256EV08C XC1736ES08C XC1701LS020I XC1736EV08I xc17256elv08c
Text: for the noted FPGA devices. September 30, 1998 (Version 1.3) 3 XC1700E Family of Serial , £ XILINX September 30, 1998 (Version 1.3) XC1700E Family of Serial Configuration PROMs Product , configuration bitstreams of Xilinx FPGA devices Simple interface to the FPGA requires only one user I/O pin , ) for compatibility with different FPGA solutions Supports the XC4000EX/XL/XLA/XV fast configuration , . Description The XC1700 family of serial configuration PROMs (SPROMs) provides an easy-to-use, cost-effective


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PDF XC1700E XC4000EX/XL/XLA/XV 20-pin XC4000XLA XC4000XV XC1736ES08I XC17128EV08I XC17128EV08C XC1765ES08I XC17256EV08I XC17256EV08C XC1736ES08C XC1701LS020I XC1736EV08I xc17256elv08c
17256dpc

Abstract: XC17128DPD8C XC17128DPC XC17128DPD8I XC17256DDD8M XC17256DPD8C XC17256DPD8I XC17256DPC XC17256DV08I XC17128DPC20C
Text: £ XILINX November 25, 1997 (Version 1.1) XC1700D Family of Serial Configuration FROMs Product Specification Features · Extended family of one-time programmable (OTP) bit-serial read-only memories used , rising edge on the clock input Simple interface to the FPGA requires only one user I/O pin Cascadable for , compatibility with different FPGA solutions XC17128D or XC17256D supports XC4000 fast configuration mode (12.5 , manufacturers. Description The XC1700 family of serial configuration PROMs (SCPs) provides an easy-to-use


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PDF XC1700D XC17128D XC17256D XC4000 commerPC20I 1736D XC1718D XC1718L XC1736D XC1765D 17256dpc XC17128DPD8C XC17128DPC XC17128DPD8I XC17256DDD8M XC17256DPD8C XC17256DPD8I XC17256DPC XC17256DV08I XC17128DPC20C
XC17512LS020C

Abstract: No abstract text available
Text: £ XILINX XC1700E Family of Serial Configuration PROMs September 30, 1998 (Version 1.3) Product Specification Features Description • The XC1700 family of serial configuration PROMs (SPROMs) provides an easy-to-use, cost-effective method for storing Xilinx FPGA configuration bitstreams , ) read-only memory designed to store configuration bitstreams of Xilinx FPGA devices Simple interface to the FPGA requires only one user I/O pin Cascadable for storing longer or multiple bitstreams


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PDF XC1700E XC1700 XC4000EX/XL/XLA/Xmation 17256E XC1736E XC1765E XC1765X XC17128E XC17128X XC17256E XC17512LS020C
XC17128EV08C

Abstract: No abstract text available
Text: £ XILINX XC1700E Family of Serial Configuration PROMs July 21, 1998 (Version 1.1) Product Specification Features Description • The XC1700 family of serial configuration PROMs (SCPs) provides an easy-to-use, cost-effective method for storing Xilinx FPGA configuration bitstreams , ) read-only memory designed to store configuration bitstreams of Xilinx FPGA devices Simple interface to the FPGA requires only one user I/O pin Cascadable for storing longer or multiple bitstreams


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PDF XC1700E XC1700 XC4000EX/XL XC17128X XC17256E XC17256X 20-Pin XC17128EV08C
XC17256E

Abstract: xilinx xc5204 v08 marking
Text: for the noted FPGA devices. September 8, 1998 (Version 1.2) 5-13 XC1700E Family of Serial , £ XILINX September 8, 1998 (Version 1.2) XC1700E Family of Serial Configuration PROMs Product , configuration bitstreams of Xilinx FPGA devices Simple interface to the FPGA requires only one user I/O pin , ) for compatibility with different FPGA solutions Supports the XC4000EX/XL/XLA/XV fast configuration , . Description The XC1700 family of serial configuration PROMs (SPROMs) provides an easy-to-use, cost-effective


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PDF XC1700E XC4000EX/XL/XLA/XV 20-pin XC4000XLA XC4000XV XC17256E xilinx xc5204 v08 marking
1701LPC

Abstract: XC17512LS020I XC+872
Text: programmable (OTP) read-only memory designed to store configuration bitstreams of Xilinx FPGA devices Simple interface to the FPGA ; requires only one user I/O pin Cascadable for storing longer or multiple bitstreams Programmable reset polarity (active High or active Low) for compatibility with different FPGA solutions , , XC1702L, XC 1701L, XQ 1701L and the XC17512L are 3.3 V devices XC1701 is a 5 V device only Available in , XC1704L, XC1702L, XC1701L, and the XC 17512L are Xilinxs 3.3V series of high density serial configuration


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PDF XC1700L XQ1701L XC4000EX/XL/XLA/XV XC1704L, XC1702L, 1701L, 1701L XC17512L XC1701 1701LPC XC17512LS020I XC+872
1702L

Abstract: 17512l XC17512LS020I XC1701 XC17512LPD8C XC17512LS020C
Text: address counter, incremented by each rising edge on the clock input Simple interface to the FPGA ; requires , (active High or active Low) for compatibility with different FPGA solutions Supports XC4000EX/XL/XLA/XV fast configuration mode (15.0 MHz) Low-power CMOS Floating Gate process XC1704L, XC1702L, XC 1701L, XQ , , and the XC 17512L are Xilinxs 3.3V series of high density serial configuration PROMs (SPROMs). Included within this family are the XC1701 (5V) and the XQ 1701L (3.3V) SPROMs to provide an easy-to-use


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PDF XC1700L XQ1701L XC4000EX/XL/XLA/XV XC1704L, XC1702L, 1701L, 1701L XC17512L XC1701 20-pin 1702L 17512l XC17512LS020I XC17512LPD8C XC17512LS020C
2004 - XC4VLX15-FF668

Abstract: axi4 XC4VLX15-FF668-10 FIFO Generator User Guide axi wrapper LocalLink XC6SLX150T-FGG484-2 artix7 ucf file XQR XQ XILINX/fifo generator xilinx spartan
Text: Notes. Table 2: Supported FPGA Families and Sub-Families FPGA Family Virtex-7 Virtex-7 -2L Virtex , and Sub-Families FPGA Family Virtex-7 Virtex-7 -2L Virtex-7 -2G Virtex-7 XT Kintex-7 Kintex-7 -2L , .3 Table 6: Supported FPGA Families and Sub-Families (Cont'd) FPGA Family Virtex-6 -1L XQ Spartan-6 XQ , Supported FPGA Device Families (1) Zynq-7000, Artix-7, Virtex-7, Kintex-7, Virtex-6, Virtex-5, Virtex , customized to utilize block RAM, distributed RAM or built-in FIFO resources available in some FPGA families


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PDF DS317 XC4VLX15-FF668 axi4 XC4VLX15-FF668-10 FIFO Generator User Guide axi wrapper LocalLink XC6SLX150T-FGG484-2 artix7 ucf file XQR XQ XILINX/fifo generator xilinx spartan
1996 - 1736DPC

Abstract: xc17128dpd8c XC17256DPD8C xilinx MARKING CODE XC4000 XC17256DPC20C Marking 8DF XC17128DPC 1736D XC1736DPD8C XC1765DPC
Text: XC1700D Family of Serial Configuration PROMs ® June 1, 1996 (Version 1.0) Product Specification Features Description · The XC1700 family of serial configuration PROMs (SCPs) provides an easy-to-use, cost-effective method for storing Xilinx FPGA configuration bitstreams. · · · · · · · · · · Extended family of one-time programmable (OTP) bit-serial read-only , , incremented by each rising edge on the clock input Simple interface to the FPGA requires only one user I/O


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PDF XC1700D XC1700 1736D XC1718D XC1718L XC1736D XC1765D XC1765L XC17128D XC17128L 1736DPC xc17128dpd8c XC17256DPD8C xilinx MARKING CODE XC4000 XC17256DPC20C Marking 8DF XC17128DPC 1736D XC1736DPD8C XC1765DPC
1996 - xapp058

Abstract: XBRF006 PP062 XAPP055 20C50 XC4000 XC6200 Xc 4000 FPGA family XC5000 XC4000E
Text: Coun 2 Efficient Shift Re · XAPP05 4000 Series RAM ting FIFOs in XC PP053 Implemen e XC4000E · , /mentor/b1_521h.tar.Z (HP-UX) Q A schematic originally targeted for the XC4000 family is now , . (Other family combinations may also cause this error.) Certain symbols are primitives in the schematic , contains EDIF descriptions for XC4000E primitives. Since OFD is not a primitive in the XC4000E family , design to a new device family is to use the Convert Design utility in PLD_DA before running the


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PDF XC4000 XC4000/XC4000E 4025ehq240-3 xapp058 XBRF006 PP062 XAPP055 20C50 XC6200 Xc 4000 FPGA family XC5000 XC4000E
XC17512LS020C

Abstract: No abstract text available
Text: configuration PROMs (SCPs). Included within this family are the XC1701 (5V) and the XQ1701L (3.3V) SCPs to provide an easy-touse, cost-effective method for storing large Xilinx FPGA configuration bitstreams. â , rising edge on the clock input Simple interface to the FPGA ; requires only one user I/O pin , ) for compatibility with different FPGA solutions Supports XC4000EX/XL/XV fast configuration mode (15.0 MHz) Low-power CMOS Floating Gate process XC1704L, XC1702L, XC 1701L, XQ 1701L and the XC17512L


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PDF XC1700L XG1701L XC1704L, XC1702L, XC1701L, 17512L XC1701 XQ1701L multiplC17512L 20-Pin XC17512LS020C
XC17256DPD8C

Abstract: XC17256DPD8I
Text: family . For device programming, the XACT development system compiles the FPGA design file into a , £ XILINX XC1700D Family of Serial Configuration PROMs June 1, 1996 (Version 1.0) Product Specification Features Description Extended family of one-time programmable (OTP) bit-serial read-only , , incremented by each rising edge on the clock input Simple interface to the FPGA requires only one user I/O , active Low) for compatibility with different FPGA solutions XC17128D or XC17256D supports XC4000 fast


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PDF XC1700D XC17128D XC17256D XC4000 1736D XC1718D XC1718L XC1736D XC1765D XC1765L XC17256DPD8C XC17256DPD8I
XC17512LS020C

Abstract: No abstract text available
Text: configuration PROMs (SPROMs). Included within this family are the XC1701 (5V) and the XQ 1701L (3.3V) SPROMs to provide an easy-to-use, cost-effective method for storing large Xil­ inx FPGA configuration , by each rising edge on the clock input Simple interface to the FPGA ; requires only one user I/O , active Low) for compatibility with different FPGA solutions Supports XC4000EX/XL/XLA/XV fast configuration mode (15.0 MHz) Low-power CMOS Floating Gate process XC1704L, XC1702L, XC 1701L, XQ 1701L and


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PDF XC1700L XG1701L XC1704L, XC1702L, XC1701L, 17512L XC1701 1701L MIL-PRF-38535 XC17512LS020C
1736DPC

Abstract: XC1765DS08C XC1736DS08C XC17256LV08I XC17128DPD8C XC1736DS08I XC17256DPD8C XC17256DDD8M XC17256D-V08I XC1765D-PC20C
Text: family . For device programming, the XACT development system compiles the FPGA design file into a standard , fi XILINX XC1700D Family of Serial Configuration PROMs June 1,1996 (Version 1.0) Features • Extended family of one-time programmable (OTP) bit-serial read-only memories used for storing the , clock input • Simple interface to the FPGA requires only one user I/O pin • Cascadable for storing , compatibility with different FPGA solutions • XC17128D or XC17256D supports XC4000 fast configuration mode


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PDF XC1700D XC17128D XC17256D XC4000 commerci5LPC20I 1736D XC1718D XC1718L XC1736D XC1765D 1736DPC XC1765DS08C XC1736DS08C XC17256LV08I XC17128DPD8C XC1736DS08I XC17256DPD8C XC17256DDD8M XC17256D-V08I XC1765D-PC20C
Not Available

Abstract: No abstract text available
Text: rising edge on the clock input Sim ple interface to the FPGA ; requires only one user I/O pin , ) for com patibility with different FPGA solutions Supports XC4000EX/XL fast configuration m ode (15.0 , method for storing Xilinx FPGA configuration bitstreams. When the FPGA is in m aster serial mode, it , appears on the SCP DATA output pin that is connected to the FPGA DIN pin. The FPGA generates the , hen the FPGA is in slave mode, the SCP and the FPGA must both be clocked by an incoming signal


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PDF XC4000EX/XL 20-pin 20-Pln 1701L XC1701L XC1701 XC17512L
Not Available

Abstract: No abstract text available
Text: €¢ • • • • • • Ultra-high-speed FPGA family with two members - 50-85 MHz system , output sink current and 4 mA source current JEDEC compliant 3.3 V version of XC3100A FPGA family The , Specification Features The XC3100L family follows the XC4000 speed-grade nomenclature, indicating device , process The XC3100L family offers the following enhancements over the popular XC3000 family . The XC3100L family has additional interconnect resources to drive the l-inputs of TBUFs driving horizontal


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PDF XC3100L XC3100L XC4000 XC3100A XC3000A, XC3000L PP132 PG132
Xilinx XC3090A

Abstract: crystal KDS 4m his 3020a
Text: architecture and features to the X C 3000A family , but operates at a nominal supply voltage of 3.3 V. The XC , FPGA architecture - Com patible arrays ranging from 1,000 to 7,500 gate com plexity - Extensive , , and others Additional XC3100A Features · Ultra-high-speed FPGA fam ily with six members - 50-85 , function at 3.0 - 3.6 V XC 3000L - Low-voltage versions of XC3000A devices XC 3100L - Low-voltage versions , FPGA is shown in Figure 2. The developm ent system provides schem atic capture and auto place-and-route


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PDF XC3000 XC3000A/L, XC31OOA/L) XC3000A, XC3000L, XC3100A, XC3100L XC3142L XC3190L XC3020A Xilinx XC3090A crystal KDS 4m his 3020a
1996 - XILINX XC2000

Abstract: pipelined matrix multiplication fpga XC9500 XC8100 XC7300 XC5200 XC4000EX XC4000E XC3100A XC3000A
Text: speed extension to XC3000A · Full PCI Compliance XC3100A FPGA Family Highest speed solutions , XC3000A · Full PCI Compliance XC3100A FPGA Family Highest speed solutions · VersaRingTM I/O Flexibility · Dedicated arithmetic logic · System Perf. to 50MHz XC5200 FPGA Family Cost Optimized, high , XC3100A FPGA Family Highest speed solutions · System Performance to 70MHz · On-chip, synchronous , & XC4000EX FPGA Families High Density, Performance Optimized XC5200 FPGA Family Cost Optimized, high


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PDF XC4000E XC4000E 55MHz, XILINX XC2000 pipelined matrix multiplication fpga XC9500 XC8100 XC7300 XC5200 XC4000EX XC3100A XC3000A
1996 - xilinx 1736a

Abstract: LEAPER-10 driver LEAPER-10 free vHDL code of median filter univision ALPS 904 C XC4000E-FPGAS -ELECTRICAL-CHARACTERISTIC V3-19 XC1765D Micromaster
Text: , they chose the world's leading control logic, they chose the FPGA family - the world's leading FPGA family XC4000 Series. Based on the "alpha7," - the XC4000 Series.d a prototype system , ISP Products in Production . 13 XC4000 Family Update: 5 Million Units Sold . 13 XC4000EX Family Begins Production . 13 Xilinx Discontinuance Policy . 14 XC4000A/H FPGA Devices Discontinued . 14 DEVELOPMENT SYSTEMS New CPLD Software Updates


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PDF XC9500 XC4000 XC4000EX xilinx 1736a LEAPER-10 driver LEAPER-10 free vHDL code of median filter univision ALPS 904 C XC4000E-FPGAS -ELECTRICAL-CHARACTERISTIC V3-19 XC1765D Micromaster
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