The Datasheet Archive

XC9500 datasheet (5)

Part Manufacturer Description Type PDF
XC9500 Xilinx XC9500 In-System Programmable CPLD Family Original PDF
XC9500 Xilinx XC9500: 5V ISP CPLD Family Original PDF
XC9500 Xilinx The Programmable Logic Data Book Original PDF
XC9500XL Xilinx XC9500XL: 3.3V ISP CPLD Family Original PDF
XC9500XV Xilinx XC9500XV: 2.5V ISP CPLD Family Original PDF

XC9500 Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
1997 - XC95144

Abstract: XC9500 xapp 2-bit adder layout XC9572 XC9536 XC95216 XC95180 XC95108 x5878
Text: ® Designing with XC9500 CPLDs XAPP 073 - January, 1997 (Version 1.0) Application Note Summary This application note will help designers understand the XC9500 architecture and how to get the best performance from these devices. Xilinx Family XC9500 Introduction To get the best , successful designs. These design techniques apply to all XC9500 devices because the architecture is uniform across the family. Figure 1 shows the XC9500 architecture. Note the regular structure of high speed


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PDF XC9500 XC9500 XC95144 xapp 2-bit adder layout XC9572 XC9536 XC95216 XC95180 XC95108 x5878
1999 - 100-PIN TQFP XILINX DIMENSION

Abstract: xilinx xc9536 digital clock xc9536-pc44 XC95216XL XC95108XL xc95144 pin diagram XC9536 XC95144 XC9536XL Series XC9500 pinout
Text: is a 3.3 V-core derivative of the popular 5 V-core XC9500 family. Each XC9500XL device comprises , scalability. Development System Like the current XC9500 family, the XC9500XL family will be supported in all , ), announced today it will begin volume shipments this month of the newest member of the 5-volt XC9500 family , Semiconductor Corporation (USC), Taiwan. During 1998, all other members of the XC9500 family will be , to Xilinx and the XC9500 CPLD family an easy choice. We've completed one design, a complex board


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PDF XC95144 1998--Xilinx, XC9500 100-PIN TQFP XILINX DIMENSION xilinx xc9536 digital clock xc9536-pc44 XC95216XL XC95108XL xc95144 pin diagram XC9536 XC9536XL Series XC9500 pinout
1996 - X5880

Abstract: XC9500 pinout xc9536 44 pin vqfp XC9572 XC9536 XC95288 XC95216 XC95180 XC95144 XC95108
Text: ® XC9500 In-System Programmable CPLD Family January, 1997 (Version 1.1) Preliminary , technology Supports parallel programming of multiple XC9500 devices Advanced system features include , Each XC9500 device is a subsystem consisting of multiple Function Blocks (FBs) and I/O Blocks (IOBs , Figure 1. Family Overview The XC9500 CPLD family provides advanced in-system programming and test , also included on all family members. As shown in Table 1, logic density of the XC9500 devices ranges


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PDF XC9500 X5880 XC9500 pinout xc9536 44 pin vqfp XC9572 XC9536 XC95288 XC95216 XC95180 XC95144 XC95108
1998 - PLCC-48 footprint

Abstract: XC95108 XC95144 XC95216 XC95288 XC9536 XC9572 XC9500 XC9500 pinout
Text: 0 XC9500 In-System Programmable CPLD Family R December 14, 1998 (Version 3.0) 0 1* Features Family Overview · The XC9500 CPLD family provides advanced in-system programming and , FastFLASH technology Supports parallel programming of multiple XC9500 devices As shown in Table 1, logic density of the XC9500 devices ranges from 800 to over 6,400 usable gates with 36 to 288 , XC9500 family is fully pin-compatible allowing easy design migration across multiple density options in


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PDF XC9500 PLCC-48 footprint XC95108 XC95144 XC95216 XC95288 XC9536 XC9572 XC9500 pinout
1999 - xc95144 pinout

Abstract: XC9500 pinout XC95144 XC95216 XC95288 XC95108 XC9572 XC9500 xc9536 44 pin vqfp XC9536
Text: 0 XC9500 In-System Programmable CPLD Family R September 15, 1999 (Version 5.0) 0 1* Features Family Overview · The XC9500 CPLD family provides advanced in-system programming and , FastFLASH technology Supports parallel programming of multiple XC9500 devices As shown in Table 1, logic density of the XC9500 devices ranges from 800 to over 6,400 usable gates with 36 to 288 , XC9500 family is fully pin-compatible allowing easy design migration across multiple density options in


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PDF XC9500 Program/er00 xc95144 pinout XC9500 pinout XC95144 XC95216 XC95288 XC95108 XC9572 xc9536 44 pin vqfp XC9536
1996 - XC9500

Abstract: XC95108 XC95144 XC95180 XC95216 XC95288 XC9536 XC9572
Text: ® XC9500 In-System Programmable CPLD Family August 1, 1996 (Version 1.1) Preliminary , mA drive. Architecture Description Each XC9500 device is a subsystem consisting of multiple , enable signals drive directly to the IOBs. See Figure 1. Description The XC9500 CPLD family provides , , the nine devices of the XC9500 family range in logic density from 800 to over 12,800 usable gates , in Table 2. The XC9500 family is fully pin-compatible allowing easy design migration across


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PDF XC9500 36V18 XC95108 XC95144 XC95180 XC95216 XC95288 XC9536 XC9572
2003 - XC95144

Abstract: DS06 xc95144 pinout XC9572 XC9536 XC95288 XC95216 XC95108 XC9500 HW130
Text: k 0 XC9500 In-System Programmable CPLD Family R DS063 (v5.1) September 22, 2003 0 , Supports parallel programming of multiple XC9500 devices High-performance - · 5 ns pin-to-pin , High-drive 24 mA outputs - The XC9500 CPLD family provides advanced in-system programming and test , also included on all family members. As shown in Table 1, logic density of the XC9500 devices ranges , and associated I/O capacity are shown in Table 2. The XC9500 family is fully pin-compatible allowing


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PDF XC9500 DS063 XC9500 36V18 Func500 XC95288. XC95144 DS06 xc95144 pinout XC9572 XC9536 XC95288 XC95216 XC95108 HW130
1996 - xilinx MTBF

Abstract: XC3042-70 XC9500 XC4005E test board
Text: 18 Figure 1: Simplified XC9500 I/O Architecture R DESIGN HINTS AND ISSUES Benchmarks Confirm XC9500 CPLD The Xilinx XC9500 CPLD family provides the , issues, Xilinx XC9500 CPLDs feature abundant routing resources, wide function block fanin and flexible product term allocation. The XC9500 fitter also optimizes the initial placement to maximize the design , /O pins. The XC9500 family provides the most routing resources of any available CPLD family. All


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PDF XC9500 xilinx MTBF XC3042-70 XC4005E test board
1998 - xc9572-44 pin

Abstract: XAPP073 X5901 XC9572 XC9536 XC95216 XC95144 XC95108 XC9500 DAT3 DIODE
Text: ® Designing with XC9500 CPLDs XAPP073 January, 1998 (Version 1.3) Application Note Summary This application note will help designers understand the XC9500 architecture and how to get the best performance from these devices. Xilinx Family XC9500 Introduction To get the best , successful designs. These design techniques apply to all XC9500 devices because the architecture is uniform across the family. Figure 1 shows the XC9500 architecture. Note the regular structure of high speed


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PDF XC9500 XAPP073 XC9500 xc9572-44 pin X5901 XC9572 XC9536 XC95216 XC95144 XC95108 DAT3 DIODE
vqfp package pinout

Abstract: No abstract text available
Text: £ XILINX February 10, 1999 (Version 4.0) XC9500 In-System Programmable CPLD Family Features , 5V FastFLASH technology Supports parallel programming of multiple XC9500 devices Family Overview The XC9500 CPLD family provides advanced in-system programming and test capabilities for high , members. As shown in Table 1, logic density of the XC9500 devices ranges from 800 to over 6,400 usable , shown in Table 2. The XC9500 fam ily is fully pin-compatible allowing easy design migration across


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PDF XC9500 36V18 vqfp package pinout
1998 - XC9500

Abstract: XC95108 XC95144 XC95216 XC95288 XC9536 XC9572 xc95144 package pinout
Text: 0 XC9500 In-System Programmable CPLD Family ® January 16, 1998 (Version 2.1) 0 3 , multiple XC9500 devices The XC9500 CPLD family provides advanced in-system programming and test , also included on all family members. As shown in Table 1, logic density of the XC9500 devices ranges , and associated I/O capacity are shown in Table 2. The XC9500 family is fully pin-compatible allowing easy design migration across multiple density options in a given package footprint. The XC9500


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PDF XC9500 36V18 XC95108 XC95144 XC95216 XC95288 XC9536 XC9572 xc95144 package pinout
2000 - 44 VQFP package

Abstract: XC17S00 vqfp 44 HW-137-DIP8 vq44 tqfp 64 socket PLCC44 socket plcc20 socket XC9500XL HW-133-PQ160
Text: Family XC9500 /XL XC9500 XC9500 /XL XC9500XL XC9500 XC9500 XC9500 /XL XC9500XL XC9500XL XC95001 XC9500 /XL XC9500 /XL Package Types PLCC44 VQFP 44 CSP 48 VQFP 64 PLCC 84 PQFP 100 TQFP 100 CSP , XC1800 Serial PROMs XC9500 /XL CPLDs Supports all Xilinx package types · Electrical Requirements , versions of the HW-133-PQ160 adapter. The current and correct adapter for programming XC9500 devices has , the obsolete XC7200/7300 product families. Added package adapters for the XC9500 /XL series in CSP 48


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PDF HW-130 DS019 XC1700 XC1800 XC9500/XL XC9500 HW-137-LCC44/VQ44 XC7200/7300 44 VQFP package XC17S00 vqfp 44 HW-137-DIP8 vq44 tqfp 64 socket PLCC44 socket plcc20 socket XC9500XL HW-133-PQ160
1999 - PLCC-48 footprint

Abstract: X5880 XC9500 pinout X5902
Text: 0 R XC9500 In-System Programmable CPLD Family 0 1* February 10, 1999 (Version 4.0 , FastFLASH technology Supports parallel programming of multiple XC9500 devices Family Overview The XC9500 , shown in Table 1, logic density of the XC9500 devices ranges from 800 to over 6,400 usable gates with 36 , Table 2. The XC9500 family is fully pin-compatible allowing easy design migration across multiple density options in a given package footprint. The XC9500 architectural features address the requirements


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PDF XC9500 36V18 PLCC-48 footprint X5880 XC9500 pinout X5902
1991 - teradyne z1800 tester manual

Abstract: dfp 740 Teradyne Teradyne spectrum teradyne tester test system xilinx jtag cable z1800 how to setup the digital functional processor PC on teradyne z1800 XC2064 XC3090
Text: Device Support · XC9500 Family (5 Volt devices) · XC9500XL Family (3.3 Volt devices) · XC9500XV Family (2.5 Volt devices) XC9500 XC9500XL XC9500XV 36 36XL 36XV 72 72XL , Programming Xilinx XC9500 on a Teradyne Z1800 or Spectrum Preface JTAG Programmer , Programming XC9500 on a Teradyne Z1800 or Spectrum R The Xilinx logo shown above is a registered , Xilinx, Inc. All Rights Reserved. June 1999 Programming XC9500 on a Teradyne Z1800 or Spectrum


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PDF XC9500 Z1800 XC9500 XC2064, XC3090, XC4005, XC5210, XC-DS501, teradyne z1800 tester manual dfp 740 Teradyne Teradyne spectrum teradyne tester test system xilinx jtag cable how to setup the digital functional processor PC on teradyne z1800 XC2064 XC3090
1995 - XC9500 pinout

Abstract: XC9500 XC95108 36V18
Text: Introducing the FastFLASH XC9500 T he new XC9500 family is the second generation of Xilinx , manufacturing capability. The XC9500 family provides a total product life cycle support solution from initial , magnitude more than other comparable CPLDs. This high endurance level allows the XC9500 devices to be used in applications requiring frequent field upgrades and reconfigurations. In addition, the XC9500 , 's Most Complete Solution for In-System Programmable CPLDs. of the PCB is necessary. The XC9500 family


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PDF XC9500 XC9500 XC95108, XC9500 pinout XC95108 36V18
1999 - XAPP0

Abstract: XAPP067 XC9500 x06701041102 3AFE 1000
Text: Application Note: XC9500 /XL/XV Family R XAPP067 (v2.0) May 13, 2002 Using Serial Vector Format Files to Program XC9500 /XL/XV Devices InSystem Summary This application note describes how to program XC9500TM /XL/XV devices in-system, using standard Serial Vector Format (SVF) stimulus files. Introduction XC9500 /XL/XV devices use a standard 4-wire Test Access Port (TAP) for both , . The XC9500 /XL/XV Boundary Scan architecture is shown in Figure 1. The Xilinx iMPACT software helps


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PDF XC9500/XL/XV XAPP067 XC9500TM/XL/XV 1a-1993) XAPP0 XAPP067 XC9500 x06701041102 3AFE 1000
2003 - XC1800

Abstract: HW-137-DIP8 HW-130 Programmer XC1700 HW-130 XC18V00 Programmer HW-130 PLCC44 socket plcc20 socket HW-130-J
Text: Selection Product Family Adapter P/N Package Types XC9500 /XL PLCC44 HW-133-PC44 XC9500 VQFP 44 HW-133-VQ44 XC9500 /XL CSP 48 HW-133-CS48 XC9500XL VQFP 64 HW-133-VQ64 XC9500 PLCC 84 HW-133-PC84 XC9500 PQFP 100 HW-133-PQ100 XC9500 /XL TQFP 100 HW-133-TQ100 XC9500XL CSP 144 HW-133-CS144 XC9500XL TQFP 144 HW-133-TQ144 XC9500 (1) PQFP 160 HW , Specifications · · · · · · · · · · · · XC1700 Serial PROMs XC18V00 ISP PROMs XC9500 /XL CPLDs


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PDF HW-130 DS019 XC1700 XC18V00 XC9500/XL XC7200/7300 XC1800 HW-137-DIP8 HW-130 Programmer Programmer HW-130 PLCC44 socket plcc20 socket HW-130-J
1996 - XC9572 Family equivalent

Abstract: XC9500 XC7200 XC7372 XC7354 XC7336 XC73108 XC7272A XC7236A 49/XC9500 Family
Text: design. Automatic part selection may be appropriate. Xilinx Family XC7200, XC7300, and XC9500. , ® XBRF 018 July 1, 1997 (Version 1.0) Converting XC7200/XC7300 Designs to XC9500 Solutions Application Brief Summary Retargeting XC7200/XC7300 designs to the XC9500 CPLD family can be as simple as , XC9500 simplifies design translation. This document assumes a version 4.2 or later Xilinx design file for the original XC7200/XC7300 format. Xilinx M1 design software translation to the XC9500 is also


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PDF XC7200/XC7300 XC9500 XC9572 Family equivalent XC7200 XC7372 XC7354 XC7336 XC73108 XC7272A XC7236A 49/XC9500 Family
1998 - XC95144

Abstract: XC9500 XAPP068 XC95108 XC95216 XC95288 XC9536 XC9572 XC95216 Family
Text: Summary This application note discusses the in-system programming speed of the XC9500 devices. Xilinx Family 1 XC9500 Introduction XC9500 devices receive programming vectors and instructions via , to program an XC9500 device includes two components: the information download time and the flash , is capable of efficiently downloading information to the XC9500 devices at the maximum speed of 10MHz. In order to minimize the production programming costs, XC9500 devices are fully erased and ready


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PDF XAPP068 XC9500 XC9500 appli00 XC9536 XC9572 XC95108 XC95144 XC95108 XC95216 XC95288 XC9536 XC9572 XC95216 Family
1997 - XAPP076

Abstract: XC9500
Text: Embedded Instrumentation Using XC9500 CPLDs ® XAPP076 January, 1997 (Version 1.0) Application Note Summary This application note shows how to build embedded test instruments into XC9500 CPLDs. Xilinx Family XC9500 Introduction Creating a Signature Analyzer Systems that use , information that saves maintenance effort and money. Now, using the advanced features of the XC9500 CPLD , signature patterns. Figure 1 shows a typical schematic for a signature analyzer. The XC9500 family has


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PDF XC9500 XAPP076 XC9500
1996 - XC95000

Abstract: XC9500
Text: JTAG Support in the XC9500 CPLD Family T 34 he new XC9500 family of CPLDs can mitigate the , devices, increased testing costs have been a significant challenge to manufacturers. The XC9500 family , boards in the field, and those changes can be fully verified. The XC9500 CPLD family simplifies , are also minimized since XC9500 devices are programmed insystem, alleviating the lead integrity problems associated with external programming methods. The XC9500 family includes seven devices that range


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PDF XC9500 XC95000
HQFP

Abstract: xc955
Text: HXILINX June 1, 1996 (Version 1.0) XC9500 In-System Programmable CPLD Family Prelim inary , grades) Advanced 0.6^m CM OS 5V FastFLASH technology · · Architecture Description Each XC9500 , 1. · · · · · · · · · · Description The XC9500 CPLD fam ily provides advanced in-system , XC9500 family range in logic density from 800 to over 12,800 usable gates with 36 to 576 registers, respectively. M ultiple package options and associated I/O capacity are shown in Table 2. The XC9500 family is


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PDF XC9500 HQFP xc955
1999 - XC9536-PC44

Abstract: PC44 HQ208 XC9572 XC9536 XC95288 XC95216 XC95108 XC9500 xc9572 data sheet
Text: begun volume shipments of the newest member of the XC9500 family of aggressively-priced complex , now comprise the XC9500 CPLD family-the XC9536, XC9572, XC95108, XC95216 and the XC95288 devices-and range in density from 36 to 288 macrocells in a variety of packages. The XC9500 family features , to take advantage of the XC9500 family's in-system programming (ISP) capability that enables easier , pricing and features of the XC9500 family," said Evert Wolsheimer, vice president and general manager of


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PDF 1997--Xilinx, XC9500 XC9536, XC9572, XC95108, XC95216 XC95288 XC9536-PC44 PC44 HQ208 XC9572 XC9536 XC95108 xc9572 data sheet
1998 - XCR3000XL

Abstract: vqfp 44 HW-137-DIP8 HW-136-CS144 HW-137-PC44/VQ44 vqfp44 HW-136-VQ100 xc17v00 HW-133-BG256 HQFP
Text: 48 HW-133-CS48 XC9500XL /XV VQFP 64 HW-133-VQ64 XC9500 PLCC 84 HW-133-PC84 XC9500 PQFP 100 HW-133-PQ100 XC9500 /XL/XV TQFP 100 HW-133-TQ100 XC9500XL /XV CSP 144 HW-133-CS144 XC9500XL /XV TQFP 144 HW-133-TQ144 XC9500 (1) PQFP 160 HW-133-PQ160 XC9500 /XL/XV PQFP/HQFP 208 HW-133-HQ208 XC9500XL /XV BGA 256 HW-133-BG256 XC9500XL /XV FBGA 256 HW-133-FG256 XC9500XL /XV CSP 280 HW-133-CS280 XC9500 BGA 352 HW


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PDF HW-130 DS019 XC1700/XC17S00/XL XC17V00/XC17S00A XC18V00 XC9500/XL/XV XCR3000XL XC7200/7300 XC9500/XL XC1800 vqfp 44 HW-137-DIP8 HW-136-CS144 HW-137-PC44/VQ44 vqfp44 HW-136-VQ100 xc17v00 HW-133-BG256 HQFP
2001 - matched filter in vhdl

Abstract: XAPP012 vhdl code for crossbar switch Insight Spartan-II demo board XAPP029 verilog code for cdma transmitter verilog code for 16 kb ram FPGA Virtex 6 pin configuration xapp005 verilog code for crossbar switch
Text: PC UNIX 72 KB XAPP111 XC9500XL 160 KB XAPP112 XC9500XL 30 KB XAPP113 XC9500 90 KB XAPP114 , 50 KB XAPP175 400 KB XAPP176 Virtex Virtex Virtex XC9500 Virtex Virtex/-E XC9500XL CPLD CoolRunner , Edge-Triggered and Dual-Port RAM Capability Using Serial Vector Format Files to Program XC9500 Devices In-System on Automatic Test Equipment and Third Party Tools In-System Programming Times Using the XC9500 JTAG Boundary Scan Interface Title Using In-System Programmability in Boundary Scan Systems Using the XC9500


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PDF Q4-01 XC3000 XC4000E XC4000 XC4000/XC5200 matched filter in vhdl XAPP012 vhdl code for crossbar switch Insight Spartan-II demo board XAPP029 verilog code for cdma transmitter verilog code for 16 kb ram FPGA Virtex 6 pin configuration xapp005 verilog code for crossbar switch
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