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2012 - XC7K325TFFG900-2

Abstract:
Text: implemented in the Kintex®-7 XC7K325TFFG900-2 FPGA using the ISE® Design Suite: Embedded Edition 14.x. The , implemented in the Kintex-7 XC7K325TFFG900-2 FPGA using the ISE Design Suite: Embedded Edition 14.x. The , .1) November 2 , 2012 Product Specification Introduction The KC705 Embedded Kit MicroBlazeTM Processor , (v1.1) November 2 , 2012 Product Specification www.xilinx.com 1 AXI Interface Based KC705 , (v1.1) November 2 , 2012 Product Specification www.xilinx.com 2 AXI Interface Based KC705


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PDF KC705 DS669 XC7K325TFFG900-2 XC7K325TFFG900 PC28F00AP30TF XC7K325T-ffg900 pc28f00ap30 adv7511 pcie microblaze RS232-UART pc28f00 DSP48E1s
2012 - XC7K325TFFG900

Abstract:
Text: implemented in the Kintex®-7 XC7K325TFFG900-2 FPGA using the ISE® Design Suite: Embedded Edition 14.x. The , . This system is implemented in the Kintex-7 XC7K325TFFG900-2 FPGA using the ISE Design Suite: Embedded , (v2.0) April 23, 2013 Product Specification www.xilinx.com 2 AXI Interface Based KC705 , 3 0 0 0 0 0 3 8 8 2 11 11 0 3 3 3 out of 445 7% out of 890 1 , 16 4 2 10 40 8 10 40 11 1 10 3 10 100% 25% 0% 2 % 0% 0% 1% 0% 0% 0% 0% 0


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PDF KC705 DS669 KC705 XC7K325TFFG900 kintex7 XC7K325TFFG900 -2 XC7K325TFFG900-2
2007 - XC7K325TFFG900

Abstract:
Text: Provided N/A Tested Design Tools Design Entry Tools Simulation( 2 ) Synthesis Tools Xilinx VivadoTM , /support 1. 2 . 3. For a complete list of supported derivative devices, see the Embedded Edition Derivative , present in the system. DS406 July 25, 2012 Product Specification www.xilinx.com 2 LogiCORE IP , reset input. An example of using the Processor System Reset Module core is shown in Figure 2 . DS406 , Module (v4.00a) X-Ref Target - Figure 2 %XT?#LK %XT?2ESET?)N #,+?). #LOCK 'ENERATOR $#-?,OCKED


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PDF DS406 XC7K325TFFG900 XC7K325T-ffg900 XC7K325T kintex 7 virtex7
2010 - XC7K325TFFG900

Abstract:
Text: size from 16 bytes to 2 GB) Medium decode speed Parity generation, parity error detection Configuration , Specifics Supported Device Family (1) See Table 1. Resources Used ( 2 ) v4 Core LUTs Slice Flip-Flops IOB Flip-Flops IOBs GCLKs (3) 506 333 270 55 2 v3 Core 553 566 97 50 1 Provided with Core Product , /support 1. For a complete listing of supported devices, see the release notes for this core. 2 . Depends , ) XC5VLX50T-FF1136- 2 /C/I (4) XC5VLX110-FF1153-2C/I (4) ( 2 ), (3) Core Version PCI32/66 Signaling Environment


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PDF 32-Bit DS206 32-bit, XC7K325TFFG900 XC6SLX45-CSG324 XC3SD3400AFG676 XC6SLX25-CSG324-2C XC6SLX16-FTG256 XC7K325T-ffg900 spartan ucf file 6 XC7K160Tffg676 XC6SLX45-FGG484 XC6SLX16-CSG324
2010 - XC7K160Tffg676

Abstract:
Text: /O with adjustable block size from 16 bytes to 2 GB) Medium decode speed Parity generation, parity , Utilization ( 2 ) LUTs Slice Flip-Flops IOB Flip-Flops IOBs GCLK (3) v4 Core 565 404 94 94 2 v3 Core 724 , release notes for this core. 2 . Resource utilization depends on core configuration and design requirements , . Table 1: Core Implementation Supported Device (1),( 2 ) Virtex-5 XC5VFX70T-FF1136-2C/I (3) (regional , .15 www.xilinx.com 2 LogiCORE IP 64-Bit Initiator/Target v3 & v4 for PCI Table 1: Core Implementation


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PDF 64-Bit DS205 64-bit, XC7K160Tffg676 XC7K160T-FBG676 XC7K325TFFG900 XC7K325T-FFG676 XC6SLX45-FGG484 XC6SLX45-CSG484 XC6SLX16CSG324 XC7K410TFFG900 XC7V585T-FFG1761 XC6SLX45-CSG324
2010 - xc7a100tcsg324

Abstract:
Text: size from 16 bytes to 2 GB) Medium decode speed Parity generation, parity error detection Configuration , . Resources Used ( 2 ) v4 Core 506 333 270 55 2 v3 Core 553 566 97 50 1 Provided with Core Product , v14. 2 Vivado Design Suite v2012. 2 (5) Mentor Graphics ModelSim Cadence Incisive Enterprise Simulator , complete listing of supported devices, see the release notes for this core. 2 . Depends on configuration of , available status. Table 1: Core Implementation Supported Devices (1), ( 2 ), (3) Core Version PCI32/66


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PDF 32-Bit DS206 32-bit, xc7a100tcsg324 Spartan-6 XC6SLX45-CSG324 XC3SD1800A-FG676 SPARTAN DSP XC7A200T-FBG484 XC6SLX9CSG225 XC6SLX4-TQG144-2C XC6SLX9-CSG225 Xilinx ISE Design Suite 14.2 XC6SLX16-CSG225 XC7A50T
2010 - XC7Z020CLG400

Abstract:
Text: ( 2 ) 404 732 IOB Flip-Flops 94 176 IOBs 94 89 GCLK (3) 2 1 , €¢ Up to three base address registers (MEM or I/O with adjustable block size from 16 bytes to 2 GB , a complete listing of supported devices, see the release notes for this core. 2 . Resource , Xilinx for latest available status. Table 1: Core Implementation Supported Device (1),( 2 ) Core , v4.18 www.xilinx.com 2 LogiCORE IP 64-Bit Initiator/Target v3 & v4 for PCI Table 1: Core


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PDF 64-Bit DS205 64-bit, XC7Z020CLG400 XC7A200T-FBG484 XC7K160Tffg676 XC7Z010-CLG400 XC7Z020CLG484 XC7Z045FFG900
2010 - xc7a100tcsg324

Abstract:
Text: and hardware • Core Specifics Resources Used ( 2 ) v3 Core LUTs Delivered through the , Flip-Flops 270 97 IOBs 55 50 GCLKs (3) 2 1 CardBus compliant • See Table 1 , registers (MEM or I/O with adjustable block size from 16 bytes to 2 GB) ISE: UCF Vivado: XDC , the release notes for this core. 2 . Depends on configuration of the interface and design. Unused , 1: Core Implementation Supported Devices (1), ( 2 ), (3) Core Version Signaling Environment


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PDF 32-Bit DS206 32-bit, xc7a100tcsg324 XC7K160Tffg676 XC7K325TFFG676 XC7A200T-FBG484 XC7Z020CLG400 XC7K325T-FFG676 XC7K325T-FBG900-1C/I XC7K160T-FFG676 XC6SLX4-TQG144-2C xc6slx25tcsg324
2010 - xc7a100tcsg324

Abstract:
Text: Family (1) LogiCORE IP Facts Core Specifics See Table 1. Resource Utilization ( 2 ) LUTs Slice Flip-Flops IOB Flip-Flops IOBs GCLK (3) v4 Core 565 404 94 94 2 v3 Core 724 732 176 89 1 Provided , three base address registers (MEM or I/O with adjustable block size from 16 bytes to 2 GB) Medium decode , Implementation Tools Simulation ISE® Design Suite v14. 2 Vivado Design Suite v2012. 2 (5) Mentor Graphics ModelSim , notes for this core. 2 . Resource utilization depends on core configuration and design requirements


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PDF 64-Bit DS205 64-bit, xc7a100tcsg324 XC7A200T-FBG484 XC6SLX16CSG324 Xilinx ISE Design Suite 14.2 XC6SLX100-FGG676 XC6SLX45-FGG484 XC6SLX16-CSG324 XC6SLX45-CSG324 XC6SLX9CSG324 XC6SLX45-CSG484
2013 - VX690T

Abstract:
Text: Vivado Design Suite User Guide Release Notes, Installation, and Licensing UG973 (v2013. 2 , MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and ( 2 ) Xilinx shall not be liable , in Chapter 2 . 03/20/2013 2013.1 Initial Xilinx release. Vivado Design Suite 2013 Release Notes UG973 (v2013. 2 ) June 19, 2013 www.xilinx.com 2 Table of Contents Revision History . . . , . . . . . . . . . . . . . . . 2 Chapter 1: Release Notes 2013.2 What’s New . . . . . . . . . .


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PDF UG973 v2013 UG900) XTP025) UG344) DS593) DS097) vivado2013-1 VX690T XC7K325T-ffg900 XC7K325TFFG900
2011 - XC7K325TFFG900

Abstract:
Text: Device Family(1) Supported User Interfaces Resources Zynq-7000( 2 ), Virtex-7(3), Kintex-7(3), Artix-7 (3 , Synthesis Support Provided by Xilinx @ www.xilinx.com/support Notes: 1. 2 . 3. 4. 5. 6. For a complete , memory mapped design: DS843 July 25, 2012 Product Specification www.xilinx.com 2 LogiCORE IP , %84?30)?#,+ !8)#,+ $OMAIN 2EGISTER-ODULE 30)# 2 30)32 30)$42 30)$22 30)332 4X/##2EG 30)4RANSFER $ONE , )NTERRUPT#ONTROLLER )0)% 2 )0)32 $')% 2 30)#LK 'ENERATOR 3#+?) #-$#OMPARE AND "EHAVIOR 3IGNALS 33?/ 33?4 33


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PDF DS843 M68HC11 Zynq-7000 XC7K325TFFG900 W25Q64VSFIG WINBOND W25Q80 SPARTAN 6 spi numonyx N25Q256 XPS ipic burst axi4 example Quad SPI XC7K325T-ffg900 NUMONYX xilinx spi XC7V285TFFG784-3
2011 - Not Available

Abstract:
Text: Specifics Supported Device Family(1) Zynq-7000( 2 ), Virtex-7(3), Kintex-7(3), Artix-7 (3), Virtex-6(4 , mapped interface Configurable SPI modes: 1. • Standard SPI mode 2 . • Dual SPI mode , , 2012 Product Specification www.xilinx.com 2 LogiCORE IP AXI Quad Serial Peripheral Interface , flash memory page size. 2 . The valid values for the C_FIFO_DEPTH parameter in this mode are 0 or , mode is selected when C_SPI_MODE is set to 2 . The behavior of the ports in the Quad mode is: â


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PDF DS843 M68HC11 Zynq-7000
2011 - N25Q256

Abstract:
Text: ) Supported User Interfaces LogiCORETM IP Facts Core Specifics ZynqTM-7000, Virtex-7( 2 ), Kintex-7( 2 ), Artix-7 ( 2 ), Virtex-6(3), Spartan-6(4) AXI4-Lite Resources Configuration See Tables 22 to 26. Provided , SPI mode) IO1 (MISO - in Standard SPI mode) SCK SS Notes: 1. 2 . 3. 4. 5. · · · · · · In Dual , , 2011 Product Specification www.xilinx.com 2 LogiCORE IP AXI Quad Serial Peripheral Interface , ) (5) ( 2 ) AXI-Lite Interface Module Slave Select Register (SPISSR) Command Register Address


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PDF DS843 M68HC11 N25Q256 WINBOND W25Q80 XC7K325TFFG900 W25Q64VSFIG XC6VLX130TFF1156 W25Q64vs XC7K325T axi4 w25q64bv
2011 - XC7VX1140T-FLG1926

Abstract:
Text: , NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and ( 2 ) Xilinx shall not be liable (whether in contract , features in Table 1-1. Chapter 2 , revised ODIV2 attribute in Table 2-1 and removed REFCLK_CTRL from Table , CPLL_RXOUT_DIV and CPLL_TXOUT_DIV in Table D- 2 . Renamed CPLL_TXOUT_DIV to TXOUT_DIV and CPLL_RXOUT_DIV to , Table B- 2 . 04/04/12 1.4 Added GTH transceivers throughout. Chapter 1: Updated Table 1-1. Chapter 2 : Updated description of O and ODIV2 ports in Table 2-1. Updated CLKSWING_CFG type to Binary in


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PDF UG476 XC7VX1140T-FLG1926
TP4303F-V1.2

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Text: 1 2 4 3 PRODUCT NUMBER 73937-XYYY 73937-XYYYLF 17.00 REF 118.00 REF 3.45 REF , /29/00 1 2 revision T T T 1 2 3 METRAL SIGNAL HEADER 10 MOD, 5 ROW PRESS-FIT METRAL product family MM size scale 2 :1 A dwg no 73937 code 213 sheet 1 of 5 T sheet title 2 engr index www.fciconnect.com COPY projection , 2006-04-18 PDM: Rev:T STATUS:Released Printed: Sep 16, 2009 . 1 2 4 3 18.00 MIN


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PDF 73937-XYYY 73937-XYYYLF V06-0544 DG09-0256 V03-0029 V03-1284 V04-0no GS-22-008. TP4303F-V1.2 TP4303E-V1.2 XF20259.2 RH1034-1.2 SUN4004-4.2 BGR25-1600.2 PSB50601HL-V1.2 SLB9655TT1.2 PSB50601HLV1.2
RH1034-1.2

Abstract:
Text: d isto rtio n factor. Functions • 4 a u d io sw itch circu its o f 2 inputs and • • 2 au d io sw itch circu its o f 3 in p u ts and 2 au d io am p lify in g c irc u its o f 2dB . • CTL E [T OUT rrLL AVIN fT" 2 a u d io am p lify in g c irc u its o f 12dB . output. output. ~ "| CTLF Ü "7 1A !N T V _LZJ 2 (R) C +1 (R) “ 771 G N D (R) _!£] (R) T71TUIN _ül (R) TTI A O V UT i_J 1(R) "Til A O V UT -IlJ 2 (0) CT LD Q ÏÏ c+ in rrr 2 (R


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PDF LA7155M VCHI-18 VCLOW-18 RH1034-1.2 TP4303E-V1.2 TP4303F-V1.2 PEF55208EV1.2 PEF2091NV5.2 PEB43650TSV1.2 PEB4266TV1.2 PEB4264T-V1.2 TPS535G2.2 H495DAN01.2
7+segment+display+d5611+a/b

Abstract:
Text: 1 _ L N O TE S 1. CO LORED S T R IP E SEE CHART 2 . PRO DUCT TO RUN L E N G T H OF R IB A S SHOWN F O R C O L O R OF S T R IP E S P E C I F IC A T I O N : P S - 7 7 2 0 - 0 0 1 SPEC S M E S -7 7 2 0 -0 0 0 2 F O R A D D T IO N A L (IN S U L . D IA IN F O R M A T IO N . .0 6 0 MAX) 3. SEE A P P L IC A T IO N 4 . W IRE S P E C I F IC A T I O N S : SLO T 26 S IZ E SEE S M E S -7 7 2 0 -0 0 0 2 A F O R U S E WITH: TIN N E D T IN N E D , AND S T R A N D E D T O P C O A T AWG S


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PDF

Abstract:
Text: MâïSUMÎ 2 -Input 1-Output 3-C ircuit Video Switch MM1232 Monolithic IC MM1232 This is a video switch for video/audio signal switching, with 2 -input and 1-output circuits built in. One ot the three circuits has a clamp function. 1. 3 circuits built in, 2 -input and 1-output 2 . Clamp function 3. Current , .6 -1 3.0V 10MHz 70dB (at 4.43MHz) SOP-16B (MM1232XF) DIP-16B (MM1232XD) 1. TV 2 . VCR 3. Other , L IN 2A LN3A ENIB H IN2B IN3B MâïSUMÎ 2 -Input 1-Output 3-C ircuit Video Switch


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PDF MM1232 10MHz 43MHz) OP-16B MM1232XF) DIP-16B MM1232XD) 43MHz RH1034-1.2 COGEMAsrl0565.2
2006 - RH1034-1.2

Abstract:
Text: Symbol Conditions - . 2 + , B 5 > . Values 25 +> Units = = * H9= H9= # # , B 5 , B 5 5 2 5 2 $5 I25 $5 I25 J@> 4 ' . $./ , B 5 - . 0 > DE , # >5 >5 ? ? ?>5 ?>5 N N N>5 N>5 ! ! 2 2 22 22 2 2 2 @ 2 @ 2 " 2 " 25 25 2 2 2 ? 2 ? 2N 2N " " N 6: L* 5 5 2 2 5 5 2 2 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 < - . / 0 K6, # ?> ?> ?>N ?>N N>@ N>@ N>! N>! !>" !>" 2 2 22> 2 22> 2 2 > 2 > 2 @>@ 2 @>@ 2 ">" 2 ">" 25> 25> 2 >? 2 >? 2 ?>N 2


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PDF 5SMCJ150CA 5SMCJ150CA RH1034-1.2 TP4303F-V1.2 IFL04-100RN508X203.2 ThinkEngine_2
1999 - RH1034-1.2

Abstract:
Text: ·Features / 1-output switches. 1) Three 2 -input 5) Excellent frequency characteristics (10MHz, ­ 1dB Typ.). 6) Wide dynamic range (2.6Vp-p Typ.). 7) Fast switching speed (50ns Typ.). 2 ) 5V power , 16 IN1a Sa CTLa 2 OUTa 14 IN2b 3 Sb GND 4 OUTb 5 13 VCC 12 CTLb OUTc 6 11 , R6 25k R2 200 CTL I2 0.6mA Q1 Q6 Q3 Q2 I1 0.25mA 2 R3 400 Q5 Q4 , Conditions - - Note 1 Note 2 f = 1MHz, VIN = 1VP-P f = 4.43MHz, VIN = 1VP-P 10MHz / 1MHz, VIN = 1VP


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PDF BA7606 BA7606F BA7606F 10MHz, 10MHz) 20mVP-P. BA7606 RH1034-1.2 L6278-1.2 TP4303F-V1.2 XF20259.2 ZS2306KE-1.2
RH1034-1.2

Abstract:
Text: . ELCO M 2 1 0 9 7 / 2 -01 00-5007-0 1 2 -16 3 -1 1 0 M 21097 / 4 -11 00-7024-023-234-110 M 21097 / 5 -01 00-7023-017-000-110 -03 00-5007-0 1 2 -23 4 -1 1 0 -12 00-7024-023-235-110 , -09 00-7023-041-000-110 -20 00-7024-029-235-110 -10 00-7023-041-000-111 M 2 1 0 9 7 / 2 -25 0 0 -5 0 0 7 -0 2 2 -1 6 3 -1 1 0 -21 00-7024-029-236-110 -27 0 0 -5 0 0 7 -0 2 2 - 2 3 4 -1 1 0 -22 00-7024-029-234-111 M 28731 / 9 -0 1 0 9 5 3 -8 0 1 6 -0 2 0 -1 9 9


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2008 - RH1034-1.2

Abstract:
Text: Solderless splices CLOSED-END øD ød E F L E L Style 2 F Style 1 Style 2 , ) (1.0 to 2.5) (2.0 to 5.5) (4.0 to 9.0) CE1(CE-100) CE2(CE-230) CE5(CE-550) CE8(CE-800) 2 -SDW 0.5-SD 1-SD 2 -SD 5.5-SD 8-SD 2 1 20.8 (.819) 9.5 (.374) 21.0 (.827) 9.5 (.374) 27.0(1.063) 12.0 (.472 , o o YA- 2 YA-4 o o o o o o o o o o o o o o o o o Insulation Material BCT-0514 o o o o o o o , with the JIS mark conform to JIS C2807. 2 ) "Applicable Wires" indicates the total cross-sectional area


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PDF E42024 LR20812 YS-2622 YS-2216 YS-1614 YS-12 CE-800) RH1034-1.2 UL E42024
1998 - RH1034-1.2

Abstract:
Text: Solderless splices CLOSED-END ød ød øD E L Style 2 F E L Style 1 F File No.: E42024 LR20812 686022 Dimensions mm (in.) Tool No. YS-2622 YS-2216 YS-1614 YS-1210 YS-8S YA-1 YA- 2 YA-4 o o o , ) (4.0 to 9.0) CE1(CE-100) CE2(CE-230) CE5(CE-550) CE8(CE-800) 2 -SDW 0.5-SD 1-SD 2 -SD 5.5-SD 8-SD 2 1 , ) 12.0 (.472) Note:1) Products with the JIS mark conform to JIS C2807. 2 ) "Applicable Wires" indicates , ) Part numbers 1-SD and 2 -SD are CSA certified with a rating of 300V; all other models are certified with


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PDF E42024 LR20812 YS-2622 YS-2216 YS-1614 YS-1210 CE-800) RH1034-1.2 c2807
2000 - RH1034-1.2

Abstract:
Text: 'XDO 3RUW 65$0 Thirty-six 2 ,304-bit Dual Port High Performance SRAM Blocks 82,900 RAM Bits RAM , Embedded Computational Units 3URJUDPPDEOH , 2 less than 3 ns Tco Programmable Slew Rate Control , 7DEOH to 7DEOH . Logic Cell diagrams and waveforms are provided from )LJXUH to )LJXUH . Figure 2 , 5DWHV # 9&&, 2 9 )DVW 6OHZ 6ORZ 6OHZ Rising Edge 2.8 V/ns 1.0 V/ns Falling Edge 2.86 V/ns 1.0 V/ns 7DEOH 2XWSXW 6OHZ 5DWHV # 9&&, 2 9 )DVW 6OHZ Rising Edge 1.7 V/ns


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PDF 304-bit RH1034-1.2
RH1034-1.2

Abstract:
Text: Material -PPS, brown color (UL 94 V-O) Profile H eight- 2 ,90 mm (.114") FFC / FPC Thickness 0,3±0,05 mm (,012±.002") PCB Thickness 0,8 - 1, 2 mm (.031 - .047") c No.ofPos. Mounting Hole Pattern (Connector , 5 7 / 4 .0 . 2 5 2 / 6 .4 .4 5 1 /1 1 .4 5 .1 9 7 / 5 .0 . 2 9 1 / 7.4 .4 9 0 /1 2 .4 5 . 2 3 6 / 6 .0 .3 3 0 / 8 .4 .5 3 0 /1 3 .4 5 . 2 7 6 / 7 .0 .3 7 0 / 9.4 .5 6 9 /1 4 .4 , /1 6 .4 5 .3 9 4 /1 0 .0 .4 8 8 /1 2 .4 .6 8 7 /1 7 .4 5 .4 3 3 /1 1 .0 .5 2 8 /1 3 .4


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PDF 945724m RH1034-1.2
Supplyframe Tracking Pixel