The Datasheet Archive

SF Impression Pixel

Search Stock

Xilinx
XC2064-33PC68C
Distributors Part Package Stock Lead Time Min Order Qty 1 10 100 1,000 10,000 Buy
Bristol Electronics XC2064-33PC68C 11 1 $14.4 $14.4 $14.4 $14.4 $14.4 Buy Now
Chip One Exchange XC2064-33PC68C 199,118 - - - - - Get Quote
Xilinx
XC2064-33PD48C INSTOCK
Distributors Part Package Stock Lead Time Min Order Qty 1 10 100 1,000 10,000 Buy
Chip One Exchange XC2064-33PD48C 29,161 - - - - - Get Quote

XC2064-33 Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
XC2064

Abstract: XC2018-125 XC1736A XC2018 XC3000 XC1765PD8C xc1765 HA 12038 XC2064-70 xc206470pc68c
Text: crystal Q) C1.C2 10-40 pF Y1 1 - 20 MHz AT cut series resonant XTAL1 XTAL2 48 DIP 33 30 68 PLCC 46 43 , numbers of data frames. For the XC2064, POWER-ON DELAY IS 214 CYCLES FOR NON-MASTER MODE—11 TO 33 mS , timeout is initiated to allow time for power to stabilize. This time-out (11 to 33 ms) is determined by a


OCR Scan
PDF XC2064/XC2018 XC2064/2018 84-Pin XC2064 XC2018-125 XC1736A XC2018 XC3000 XC1765PD8C xc1765 HA 12038 XC2064-70 xc206470pc68c
AXP 209

Abstract: UPD65031 UPD65070 intel 80487 UPD65006 SCX6206 HG62B40 UPD65022 mb86901 SCX6218
Text: -25 L R3000AHM-20 LR3000AHC-25 LR3000AHC- 33 Mostek Footprint # 64 69 85 121 148 181 Device # , -33PG84X XC2018-50PG84X XC2018-70PG84X XC2064-100PG68X XC2064-33PG68X XC2064-50PG68X XC2064-70PG68X XC3020


OCR Scan
PDF A1280-PG176 A1240-PG132 MB86920 MB86930 MB86940 MB87067 MB87068 MB8764 MBL80286 AXP 209 UPD65031 UPD65070 intel 80487 UPD65006 SCX6206 HG62B40 UPD65022 mb86901 SCX6218
1995 - XC3030-70PC84C

Abstract: EPM5128LC EP330PC-15 A1020 transistor A1010B-PL68C EPM5128GM EP330PC15 XC3042-70PC84C EP330PC A1020A-PL84C
Text: . d. 3.3 -V part. e. Confirm availability with TEMIC sales representative. Rev. D (22/06/95 , . d. 3.3 -V part. e. Confirm availability with TEMIC sales representative. 6-2 C Temperature , . b. Feasibility required. c. Limitations may apply to RAM size. d. 3.3 -V part. e. Confirm , . d. 3.3 -V part. e. Confirm availability with TEMIC sales representative. 6-4 C Temperature , apply to RAM size. d. 3.3 -V part. e. Confirm availability with TEMIC sales representative. Rev. D


Original
PDF A1010A-PL44C A1010B-PL44C ULC/A1010 44-PLCC A1010A-PL44I A1010B-PL44I A1010A-1PL44C A1010B-1PL44C A1020A-1PL44C XC3030-70PC84C EPM5128LC EP330PC-15 A1020 transistor A1010B-PL68C EPM5128GM EP330PC15 XC3042-70PC84C EP330PC A1020A-PL84C
Not Available

Abstract: No abstract text available
Text: 1 .C 2 1 0 - 4 0 pF V I 1 - 2 0 M H z A T cut series resonant XTAL1 XTAL2 4 8 DIP 33 , time­ out is initiated to allow time for power to stabilize. This time-out (11 to 33 ms) is , , flip-flops in the Logic Cell Array can be toggled at clock rates from 33 -70 MHz, depending on the speed


OCR Scan
PDF XC2064/XC2018 XC2064/2018 84-Pin
XILINX XC 2064

Abstract: 1736a XC2064-70PC68C 333CJ 1765PD development board xc2018 XC2064-70-PC68C XC1736A pg68
Text: series resonant XTAL1 4 8 DIP 6 8 PLCC 68 PGA 8 4 PLCC 8 4 PGA 33 46 J10 56 K11 XTAL2 30 43 L10 53 , NON-MASTER MODE- 11 TO 33 mS 216 CYCLES FOR MASTER MODE- 43 TO 130 mS USER I/O PINS WITH HIGH IMPEDANCE , to 33 ms) is determined by a counter driven by a self-generated, internal sampling clock that drives , this arrangement, flip-flops in the Logic Cell Array can be toggled at clock rates from 33 -70 MHz


OCR Scan
PDF XC2064/XC2018 68-Pin 84-Pin XILINX XC 2064 1736a XC2064-70PC68C 333CJ 1765PD development board xc2018 XC2064-70-PC68C XC1736A pg68
kb3940

Abstract: XC2064-70PC44C
Text: XC2018L Vcc 5.0 3.3 5.0 3.3 V V V V Typ. Logic Capacity (gates) 6 0 0 -1 ,0 0 0 6 0 0 -1 ,0 0 0 1,000 , Compatible arrays with logic cell complexity equiva lent from 600 to 1,500 gates · Available in 5-V and 3.3 , family operates with nominal 3.3 V supply. The LCA logic functions and interconnections are deter mined , AAA,- f R2 ? 48 DIP 6 8P LC C 68 PGA 8 4P L C C 84 PGA 33 46 J10 56 AM · Suggested , pow erto stabilize. This time-out (11 to 33 ms) is determined by a counter driven by a self-generated


OCR Scan
PDF XC2000 XC2064 XC2064L XC2018 XC2018L XC2000L TQ100 VQ100 XC2064 kb3940 XC2064-70PC44C
NEC B1100

Abstract: b1100 nec UPD65031 MCA600ECL PD65031 UPD650 UPD65012 upd65022 UPD65006 upd65051
Text: XC3064 XC3090 XC2018-100PG84X X C 2 0 18-33 PG84X XC2018-50PG84X XC2018-70PG84X XC2064-100PG68X XC2064-33PG68X


OCR Scan
PDF EP1800 EPM5192 EPM5130 B6010 B2022 B2023 B2020 HD61811Y HD63450Y10 HD63450Y12 NEC B1100 b1100 nec UPD65031 MCA600ECL PD65031 UPD650 UPD65012 upd65022 UPD65006 upd65051
XC2018

Abstract: XC2000 Family XC2064 XILINX xc2018
Text: XC2000 Logic Cell Array Families Overview Introduced in 1985, the XC2000 family has seen continu ously increasing sales for 8 years. In 1993, Xilinx intro duced the ZERO+ Family of 3.3 V devices, intended for the fast growing market of battery-operated portable comput ers and instruments. While the XC3000/XC3100 families offer more speed, a wider range of device capacities and more packaging options, and the XC4000 family offers more advanced systems features, the XC2064 and XC2018 are the world


OCR Scan
PDF XC2000 XC3000/XC3100 XC4000 XC2064 XC2018 XC3020 XC4002A XC2000 Family XILINX xc2018
XC2018

Abstract: XC2018 PC84 XC2064 XC3042A pinout xc206470pc44c x5397 XC2000 XC7354
Text: equivalent from 600 to 1,500 gates • Available in 5-V and 3.3 -V versions • 100% factory tested â , XC2064 5.0 V 600-1,000 64 58 12,038 XC2064L 3.3 V 600-1,000 64 58 12,038 XC2018 5.0 V 1,000-1,500 100 74 17,878 XC2018L 3.3 V 1,000-1,500 100 74 17,878 The XC2000 family operates with a nominal 5.0 V supply. The XC2000L family operates with nominal 3.3 V supply. The LCA logic functions and , Oscillator XTAL1 XTAL2 48 DIP 33 30 68PLCC 46 43 68 PGA J10 L10 84PLCC 56 53 84 PGA K11 L11 2-195


OCR Scan
PDF XC2000 Log176 XC4002A XC4003A XC4003 XC4003H XC4004A XC4005A XC4005 XC4005H XC2018 XC2018 PC84 XC2064 XC3042A pinout xc206470pc44c x5397 XC2000 XC7354
XC2064

Abstract: XC3030A xc3142 Xilinx XC3090A XC3190 xact xc3090 xc2064 fpga Xilinx XC3090 PP175 X04008
Text: No file text available


OCR Scan
PDF XC2064 XC2O10 XC2064L XC2O10L XC3020 XC3030 XC3042 XC3064 XC3090 XC3020A XC3030A xc3142 Xilinx XC3090A XC3190 xact xc3090 xc2064 fpga Xilinx XC3090 PP175 X04008
1995 - XC2064

Abstract: xc2064-70pc44c x5397 Matrix Crystal x5399 xc206470pc44c XC4002A XC4000 XC3020 XC2018
Text: ZERO+ Family of 3.3 V devices, intended for the fast growing market of battery-operated portable , complexity equiva- VCC 5.0 V 3.3 V 5.0 V 3.3 V Typ. Logic Capacity (gates) 600 ­ 1,000 600 ­ 1 , supply. The XC2000L family operates with nominal 3.3 V supply. lent from 600 to 1,500 gates · · , requirements. Available in 5-V and 3.3 -V versions 100% factory tested Selectable configuration modes , PGA XTAL1 33 46 J10 56 K11 XTAL2 30 43 L10 53 L11 X5404 XC2000 Logic Cell Array


Original
PDF XC2000 XC2018 XC2064 TQ100 VQ100 XC2064L XC2018L Mil-STD-883C X6120 XC2064 xc2064-70pc44c x5397 Matrix Crystal x5399 xc206470pc44c XC4002A XC4000 XC3020 XC2018
xilinx XC3000 Architecture

Abstract: CB100 Xilinx XC3090 PG68 Xilinx XC3090A XC2064 fpga programming XC2000 Xilinx XC3030A
Text: No file text available


OCR Scan
PDF XC2000, XC3000, XC4000 xilinx XC3000 Architecture CB100 Xilinx XC3090 PG68 Xilinx XC3090A XC2064 fpga programming XC2000 Xilinx XC3030A
Not Available

Abstract: No abstract text available
Text: · Available in 5-V and 3.3 -V versions · 100% factory tested · Selectable configuration modes · , XC2018 XC2018L Vcc 5.0 3.3 5.0 3.3 V V V V Typ. Logic Capacity (gates) 6 0 0 -1 ,0 0 0 600 -1 ,0 0 0 1 , with nominal 3.3 V supply. The LCA logic functions and interconnections are deter mined by data stored , 1 Y1 T 48 DIP 68 PLCC 68 PGA 84 PLCC 84 PGA X ' XTAL1 33 46 J10 56 K11 XTAL2 30 43 L10 53 , high-impedance and a time-out is initiated to allow time for power to stabilize. This time-out (11 to 33 ms) is


OCR Scan
PDF XC2000 2064-70P TQ100 VQ100 XC2064 XC2018 MIL-STD-883C XC2064L XC2018L
Not Available

Abstract: No abstract text available
Text: XC2000L Low-Voltage Logic Cell Array Family Preliminary Product Specification Features Description • Part of the ZERO+ Family of 3.3 V FPGAs The XC2000L family of FPGAs is optimized for operation from a 3.3 V (nominal) supply. Aside from the electrical and timing parameters listed in this , , low-supply-voltage FPGA family with two device types - JEDEC-compliant 3.3 V version of the XC2000 LCA Family - , . PLCC PGA PC44 PD48 '50 c XC2064 -70 " c I ~~~ -100 - 33 VQ64 PC68 Cl Cl g— CODE


OCR Scan
PDF XC2000L XC2000L XC2000 XC2000 XC2064 XC2018 XC2064L XC2018L
Not Available

Abstract: No abstract text available
Text: equiva­ lent from 600 to 1,500 gates • Available in 5-V and 3.3 -V versions • 100% factory , €¢ Performance equivalent to TTL SSI/MSI Device Vcc XC2064 XC2064L XC2018 XC2018L 5.0 3.3 5.0 3.3 V V V V Typ. Logic Capacity (gates) User CLBs Max Config. bits 6 0 0 -1 , family operates with nominal 3.3 V supply. The LCA logic functions and interconnections are deter , XTAL1 33 46 J10 56 K11 XTAL2 30 43 L10 53 L11 X5404 XC2000 Logic Cell Array Families


OCR Scan
PDF XC2000 XC2064 XC2064L XC2018 XC2018L XC2000L
1996 - TCA780

Abstract: TFK U 111 B TFK U 4614 B TFK S 186 P TFK U 217 B TFK BP w 41 n TFK BPW 41 N Tfk 880 TFK 148 TDSR 5150 G
Text: 245 3 N 281 4 N 25 4 N 26 4 N 27 4 N 28 4 N 29 4 N 29 A 4 N 30 4 N 31 4 N 32 4 N 33 4 N 35 , N 28 4 N 32 4 N 32 4 N 32 4 N 32 4 N 32 4 N 33 4 N 35 4 N 37 4 N 38 4 N 38 A See EP600 , -67202 AL-35 Page 33 of 128 Approximate ReplacemenMfg SIL SIL SIL SIL SIL SIL DG387ACJ SIL SIL


Original
PDF 1N3245 1N3611GP 1N3612GP 1N3613GP 1N3614GP 1N3725 1N3957GP 1N4001GP 1N4002GP 1N4003GP TCA780 TFK U 111 B TFK U 4614 B TFK S 186 P TFK U 217 B TFK BP w 41 n TFK BPW 41 N Tfk 880 TFK 148 TDSR 5150 G
Not Available

Abstract: No abstract text available
Text: equiva­ lent to 1,000 and 1,500 gates • Available in 5-V and 3.3 -V versions • 100% factory , 5.0 V 3.3 V 5.0 V 3.3 V Typ. Logic Capacity (gates) 800-1,000 800 -1,000 1,200-1,500 1 , operates with nominal 3.3 V supply. The LCA logic functions and interconnections are deter­ mined by , 33 30 68P LC C 46 43 68 PGA J10 L10 84PLC C 56 53 8 4 PGA K11 , high-impedance and a time-out is initiated to allow time for power to stabilize. This time-out (11 to 33 ms) is


OCR Scan
PDF XC2000 XC2064 XC2064L XC2018 XC2018L VQ100 2018L MIL-STD-883C
1998 - ulc xc3030

Abstract: PQFP 176 Xilinx XC3090 EPM7128 altera EP300 Temic ulc xc3030 EPM7128 PLCC PLSI2032 Actel A1020 PLUS405
Text: No file text available


Original
PDF ULC/A1010 ULC/A1020 ulc xc3030 PQFP 176 Xilinx XC3090 EPM7128 altera EP300 Temic ulc xc3030 EPM7128 PLCC PLSI2032 Actel A1020 PLUS405
XC-2064-50

Abstract: QILE68P-410T QILE68P410T QILE-84P-410T
Text: Lo g ic CellTM A rra y M 2 0 6 4 /M 2 0 1 8 Features/Benefits · CMOS programmable Logic Cell Array (LCA) for replacement of standard logic · Completely reconfigurable by the user in the final system · High performance equivalent to TTL SSI/MSI - 33 MHz flip-flop toggle rate (- 33 speed grade) - 50 , ) SPEED G R A D E - 33 ( 33 MHz Toggle Rate) -50 (50 MHz Toggle Rate) -70 (70 MHz Toggle , AT cut : : R1 A A A R2 XTAL1 48 DIP 68P LCC 68 PGA 84PLCC 84 PGA 33 46 J10 56 K11


OCR Scan
PDF 68/84-pin thresho821542-1 QILE68P-410T QILE84P-410T M2064/18 XC-2064-50 QILE68P410T QILE-84P-410T
Not Available

Abstract: No abstract text available
Text: Logic Cell™ A rray M 2 0 6 4 /M 2 0 1 8 Features/Benefits • CMOS programmable Logic Cell Array (LCA) for replacement of standard logic • Completely reconfigurable by the user in the final system • High performance equivalent to TTL SSI/MSI - 33 MHz flip-flop toggle rate (- 33 speed grade , . ' T _ NUMBER OF PINS SPEED GRADE - 33 ( 33 MHz Toggle Rate) -50 (50 MHz Toggle Rate) -70 (70 MHz , ^ V J10 L10 56 53 84 PGA R2 = b Cl 30 46 84PLCC R1 HoF 33


OCR Scan
PDF M2064 M2018
1995 - XC2064

Abstract: XC3030 PQ240 xc5204 XC3090 XC3064 XC3042 XC3030A XC3020A XC3020
Text: No file text available


Original
PDF XC2064 XC2018 XC2064L XC2018L XC4002A XC4003A XC4004A XC4005A XC4003H XC4005H XC2064 XC3030 PQ240 xc5204 XC3090 XC3064 XC3042 XC3030A XC3020A XC3020
1999 - PDP-11

Abstract: computer schematics 8086 XILINX xc2018 8086 vhdl XC2064 XC3090 XC2018 PDP11 drawing using 8086 8086 project
Text: , running on a 33 megahertz technologies such as our Silicon Xpresso software that allows you 80386, could


Original
PDF 8086-based PDP-11 computer schematics 8086 XILINX xc2018 8086 vhdl XC2064 XC3090 XC2018 PDP11 drawing using 8086 8086 project
xc2064 pcb

Abstract: Y148 K6A60 XC-2064-50 XC2018-50
Text: ADV M C R O PLA/PLE/ARRAYS , E , | H n 5 a g | Logic CellTM Array M 2 0 6 4 /M 2 0 1 8 Features/Benefits · CMOS programmable Logic Cell Array (LCA) fo r replacement o f standard logic · Completely reconflgurable by the user In the final system · High perform ance equivalent to TTL SSI/MSI - 33 MHz flip-flo p toggle rate (- 33 speed grade) - 50 MHz flip-flop toggle rate (-50 speed , PGA 33 46 J10 56 K11 SUGGESTED COMPONENT VALUES R1 1 - 4 M il R2 0 - 1 Kfl (may be required


OCR Scan
PDF si13E xc2064 pcb Y148 K6A60 XC-2064-50 XC2018-50
1995 - XC2064

Abstract: XC2018 PC84 XC3030A XC3064 XC3090 XC3042 xc5210 PQ160 XC3030 XC3020A XC3020
Text: No file text available


Original
PDF XC2064 XC2018 XC2064L XC4003 XC4005 XC4006 XC4008 XC4010 XC4010D XC4013 XC2064 XC2018 PC84 XC3030A XC3064 XC3090 XC3042 xc5210 PQ160 XC3030 XC3020A XC3020
ULC EPM5128

Abstract: 85C090 EP1200 PAL18P8 epm5130 XC3020 85C060 PLS100 ACT1010 ulc xc3030
Text: No file text available


OCR Scan
PDF GAL16V8 PAL16P8 PAL18P8 PAAAL16L8 PAL10L8 PAL14L4 PAL16L2 PAL16RP8 PAL16RP4 PAL16R8 ULC EPM5128 85C090 EP1200 epm5130 XC3020 85C060 PLS100 ACT1010 ulc xc3030
Supplyframe Tracking Pixel