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XC2018 PC84 Datasheets Context Search

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1997 - XC2000

Abstract: XC2018 PC84 XILINX XC2000 xc5200 XC3000 XC2018 D24E XC3000A XC3100 XC3100A
Text: family has two members, the XC2064 and XC2018 . Even the larger XC2018 should fit in the smallest XC5200 , family. Table 2: Density Comparison XC2000/ XC3000 XC2064 XC2018 XC3020 XC3030 XC3042 XC3064 , Resources Between XC5202, XC5206, XC5210 and XC3195, XC2018 Resource Max Logic Gates Maximum CLB , Boundary-scan Internal oscillator Configuration modes PC44, VQ64, PC84 , PQ100, VQ100, Packages , PC84 , PQ100, VQ100, PQ160, TQ144, TQ176, PG191, PQ208 PC84 , PC84 , PQ160, TQ144, TQ176


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PDF XC2000/ XC3000 XC5200 XC5200 XC4000 XC3100A XC2000/XC3000 XC2000 XC2018 PC84 XILINX XC2000 XC2018 D24E XC3000A XC3100
1995 - XC2064

Abstract: XC3030 PQ240 xc5204 XC3090 XC3064 XC3042 XC3030A XC3020A XC3020
Text: XC2018 XC2064L XC2018L XC3020 XC3030 XC3042 XC3064 XC3090 XC3020A XC3030A XC3042A XC3064A , PC84 WC84 PG84 CQ100 PQ100 TQ100 VQ100 CB100 PG120 PP132 PG132 TQ144 PG144 PG156 PQ160


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PDF XC2064 XC2018 XC2064L XC2018L XC4002A XC4003A XC4004A XC4005A XC4003H XC4005H XC2064 XC3030 PQ240 xc5204 XC3090 XC3064 XC3042 XC3030A XC3020A XC3020
1996 - XILINX XC2000

Abstract: XC2000 XC3000 XC2018 XC2018 PC84 XC5200 XILINX XC2018 D24E XC4000 XC3100A
Text: members, the XC2064 and XC2018 . Even the larger XC2018 should fit in the smallest XC5200 device, the , . Table 2: Density Comparison XC2000/ XC3000 XC2064 XC2018 XC3020 XC3030 XC3042 XC3064 XC3090 , Between XC5202, XC5206, XC5210 and XC3195, XC2018 Resource Max Logic Gates Maximum CLB flip-flops , Boundary-scan Internal oscillator Configuration modes PC44, VQ64, PC84 , PQ100, VQ100, Packages TQ144 , 8 mA Yes Yes Yes 7 XC5210 16,000 1,296 0 192 165,488 1,296 PC84 , PQ100, VQ100


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PDF XC2000/ XC3000 XC5200 XC5200 XC4000 XC3100A XC2000/XC3000 XILINX XC2000 XC2000 XC2018 XC2018 PC84 XILINX XC2018 D24E
1996 - XC2000

Abstract: XC2018 PC84 XILINX XC2000 XC2000 FPGAs XC3000 XC5200 VQ64 XC3000A XC3100 XC3100A
Text: members, the XC2064 and XC2018 . Even the larger XC2018 should fit in the smallest XC5200 device, the , . Table 2: Density Comparison XC2000/ XC3000 XC2064 XC2018 XC3020 XC3030 XC3042 XC3064 XC3090 , Between XC5202, XC5206, XC5210 and XC3195, XC2018 Resource Max Logic Gates Maximum CLB flip-flops , Boundary-scan Internal oscillator Configuration modes PC44, VQ64, PC84 , PQ100, VQ100, Packages , PC84 , PQ100, VQ100, PQ160, TQ144, TQ176, PG191, PQ208 PC84 , PC84 , PQ160, TQ144, TQ176


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PDF XC2000/ XC3000 XC5200 XC5200 XC4000 XC3100A XC2000/XC3000 XC2000 XC2018 PC84 XILINX XC2000 XC2000 FPGAs VQ64 XC3000A XC3100
1995 - XC2064

Abstract: XC2018 PC84 XC3030A XC3064 XC3090 XC3042 xc5210 PQ160 XC3030 XC3020A XC3020
Text: XC2064 XC2018 XC2064L XC2018L XC3020 XC3030 XC3042 XC3064 XC3090 XC3020A XC3030A XC3042A , CHART PC44 x PQ44 WC44 PD48 x VQ64 PC68 x WC68 PG68 x PC84 WC84 PG84 CQ100 PQ100 TQ100


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PDF XC2064 XC2018 XC2064L XC4003 XC4005 XC4006 XC4008 XC4010 XC4010D XC4013 XC2064 XC2018 PC84 XC3030A XC3064 XC3090 XC3042 xc5210 PQ160 XC3030 XC3020A XC3020
XC2064

Abstract: XC3030A xc3142 Xilinx XC3090A XC3190 xact xc3090 xc2064 fpga Xilinx XC3090 PP175 X04008
Text: 68 Ceramic PGA PG68 Plastic PLCC PC84 84 Ceramic PGA PG84 Plastic PQFP PQ100 Plastic TQFP TQ100 , XC2018 XC2064L XC2018L XC3020 XC3030 XC3042 XC3064 XC3090 XC3020A XC3030A XC3042A XC3064A XC3090A XC3020L


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PDF XC2064 XC2O10 XC2064L XC2O10L XC3020 XC3030 XC3042 XC3064 XC3090 XC3020A XC3030A xc3142 Xilinx XC3090A XC3190 xact xc3090 xc2064 fpga Xilinx XC3090 PP175 X04008
1996 - VHDL code for generate sound

Abstract: XC3020A - PQ100 xilinx xact viewlogic interface user guide foundation field bus XILINX xc2018 XC7336A XC2064A XC9500 XC8100 XC4000
Text: Packages Speed Grades XC2018 PC44, VQ64, PC68, PC84 , PG84, TQ100 -33, -50, -70, -100, -130 XC2064a PC44, PC68, PD48, PG68 -33, -50, -70, -100, -130 XC2018La PC84 , VQ64, VQ100 -10 XC2064La VQ64, PC68 -10 XC3020a PC68, PC84 , PG84, CB100, CQ100, PQ100 -50, -70, -100, -125 XC3030a PC44, PC68, PC84 , PG84, PQ100, TQ100 -50, -70, -100, -125 XC3042a PC84 , PG84, CB100, CQ100, PQ100, TQ100, PG132, -50, -70, -100, -125 PP132 XC3064a b PC84 , PG132, PP132, PQ160 -50


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xilinx XC3000 Architecture

Abstract: CB100 Xilinx XC3090 PG68 Xilinx XC3090A XC2064 fpga programming XC2000 Xilinx XC3030A
Text: . Component Availability Pins Type Code XC2064 XC2018 XC2064L XC2018L XC3020 XC3030 XC3042 XC3064 XC3090 , &8 Ceramic PGA PG68 Plastic PLCC PC84 84 Ceramic PGA PG84 Plastic PQFP PQ100 Plastic TQFP TQ100


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PDF XC2000, XC3000, XC4000 xilinx XC3000 Architecture CB100 Xilinx XC3090 PG68 Xilinx XC3090A XC2064 fpga programming XC2000 Xilinx XC3030A
Not Available

Abstract: No abstract text available
Text: XC2018 XC2064L XC2018L -5 0 -70 -100 BIB ' * c f~ "c PG68 1 (Cl) Cl 100 PLAST. PLCC CERAM. PGA PC84 PG84 TQ100 VQ100 C IM ~“ “ c MB 1 Cl


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PDF XC2000L XC2000L XC2000 XC2000 XC2064 XC2018 XC2064L XC2018L
1996 - netcon

Abstract: XC5204PC84 XC7354 XC40000 XC5204-PC84 XILINX XC2000 DS-344 XC7000 XC5200 Xilinx XC3042A
Text: parameters, see The Programmable Logic Data Book. Device a Packages Speed Grades XC2018 PC44, PC68, PC84 , PG84, TQ100, VQ64 -33, -50, -70, -100, -130 XC2064a PC44, PC68, PD48, PG68 -33, -50, -70, -100, -130 XC2018La PC84 , VQ64, VQ100 -10 XC2064La PC68, VQ64 -10 XC3020a CB100, CQ100, PC68, PC84 , PG84, PQ100 -50, -70, -100, -125 XC3030a PC44, PC68, PC84 , PG84, PQ100, TQ100 -50, -70, -100, -125 XC3042a CB100, CQ100, PC84 , PG84, PG132, PP132, PQ100


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1996 - ORCAD BOOK

Abstract: DS-35 XcxxX OSC52 XC5204PC84 orcad orcad schematic symbols library XC5200 VST386 xact reference guide
Text: Grades XC2018 PC44, PC68, PC84 , PG84, TQ100, VQ64 -33, -50, -70, -100, -130 XC2064a PC44, PC68, PD48, PG68 -33, -50, -70, -100, -130 XC2018La PC84 , VQ64, VQ100 -10 XC2064La PC68, VQ64 -10 XC3020a CB100, CQ100, PC68, PC84 , PG84, PQ100 -50, -70, -100, -125 XC3030a PC44, PC68, PC84 , PG84, PQ100, TQ100 -50, -70, -100, -125 XC3042a CB100, CQ100, PC84 , PG84, PG132, PP132, PQ100, TQ100 -50, -70, -100, -125 XC3064a b PC84 , PG132, PP132, PQ160 -50


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1996 - OSC52

Abstract: xilinx xc3000 vq100 XC5200 XC4025 XC4000E XC4000A XC3100A XC3000 xact reference guide
Text: . Device a Packages Speed Grades XC2018 PC44, PC68, PC84 , PG84, TQ100, VQ64 -33, -50, -70, -100, -130 XC2064a PC44, PC68, PD48, PG68 -33, -50, -70, -100, -130 XC2018La PC84 , VQ64, VQ100 -10 XC2064La PC68, VQ64 -10 XC3020a CB100, CQ100, PC68, PC84 , PG84, PQ100 -50, -70, -100, -125 XC3030a PC44, PC68, PC84 , PG84, PQ100, TQ100 -50, -70, -100, -125 XC3042a CB100, CQ100, PC84 , PG84, PG132, PP132, PQ100, TQ100 -50, -70, -100, -125 XC3064a b PC84 , PG132


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1995 - XC2018 PC84

Abstract: DS401 XC3042 pc84 CORE i3 ARCHITECTURE CORE i3 INTERNAL ARCHITECTURE XC3020 "Tape drive" xc4005 pg156 XC7000 HP700
Text: families. Device XC2018 XC2064 XC2018L XC2064L XC3020 XC3030 XC3042 XC3064* XC3090* XC3020A , XC3142 XC3164* XC3190* XC3195* XC3120A June 1995 Packages PC44 PC44 PC84 PC68 CB100 PC44 CB100 PQ100 PC84 CB164 PQ208 CB100 PC44 VQ100 CB100 TQ144 PC84 CB164 TQ176 PC84 PC84 PC84 PC84 PC84 CB100 PC44 CB100 TQ100 PC84 CB164 PQ208 PC84 CB100 PC68 PC68 VQ64 VQ64 CQ100 PC68 CQ100 TQ100 PG132 CQ164 Speed Grades PC84 PD48 VQ100 PG84 PG68 TQ100 VQ64


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XC2018

Abstract: XC2018 PC84 XC2064 XC3042A pinout xc206470pc44c x5397 XC2000 XC7354
Text: XC2064 5.0 V 600-1,000 64 58 12,038 XC2064L 3.3 V 600-1,000 64 58 12,038 XC2018 5.0 V 1,000-1,500 100 , center of the device. The XC2064 has 64 such blocks arranged in an 8-row by 8-column matrix. The XC2018 , numbers of data frames. For the XC2064, configuration requires 12,038 bits for each device. For the XC2018 , and the XC2018 uses 197. The configuration bit stream begins with preamble bits, a preamble code and , , initialization will require about 160 additional cycles of the internal sampling clock (197 for the XC2018 ) to


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PDF XC2000 Log176 XC4002A XC4003A XC4003 XC4003H XC4004A XC4005A XC4005 XC4005H XC2018 XC2018 PC84 XC2064 XC3042A pinout xc206470pc44c x5397 XC2000 XC7354
XILINX xc2018

Abstract: XC3042-70PG84B XC2018 XC3195A SPEED 5962-8994802MMC XC4010-6PG191B
Text: ib tr Equivalent “B” Grade P/N Mark Loc XC2018 -33PG84B Speed -33 Package 5962-8863801XC PG84 TOP 5962-8863802XC XC2018 -50PG84B -50 PG84 TOP 5962-8863803XC XC2018 -70PG84B -70 PG84 TOP 5962-8863804XC XC2018 -100PG84B -100 PG84 TOP


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PDF PG191 5962-9230503MXC XC4010-5PG191B 5962-9230501MYC XC4010-10CB196B CB196 5962-9230502MYC XC4010-6CB196B XILINX xc2018 XC3042-70PG84B XC2018 XC3195A SPEED 5962-8994802MMC XC4010-6PG191B
1995 - XC2064

Abstract: xc2064-70pc44c x5397 Matrix Crystal x5399 xc206470pc44c XC4002A XC4000 XC3020 XC2018
Text: XC2064 and XC2018 are the world's lowest cost FPGAs, and they remain the most economical solution for , XC2064 XC2064L XC2018 XC2018L ­ I/O functions ­ Digital logic functions ­ Interconnections · , . The XC2018 has 100 logic blocks arranged in a 10 by 10 matrix. Each logic block has a combinatorial , , configuration requires 12,038 bits for each device. For the XC2018 , the configuration of each device requires 17,878 bits. The XC2064 uses 160 configuration data frames and the XC2018 uses 197. The


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PDF XC2000 XC2018 XC2064 TQ100 VQ100 XC2064L XC2018L Mil-STD-883C X6120 XC2064 xc2064-70pc44c x5397 Matrix Crystal x5399 xc206470pc44c XC4002A XC4000 XC3020 XC2018
kb3940

Abstract: XC2064-70PC44C
Text: Field-Programmable: - I/O functions - Digital logic functions - Interconnections Device XC2064 XC2064L XC2018 , -column matrix. The XC2018 has 100 logic blocks arranged in a 10 by 10 matrix. Each logic block has a , , configura tion requires 12,038 bits for each device. For the XC2018 , the configuration of each device requires 17,878 bits. The XC2064 uses 160 configuration data frames and the XC2018 uses 197. The , , initialization will require about 160 additional cycles of the internal sampling clock (197 for the XC2018 ) to


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PDF XC2000 XC2064 XC2064L XC2018 XC2018L XC2000L TQ100 VQ100 XC2064 kb3940 XC2064-70PC44C
1996 - XC17256DDD8B

Abstract: XC3042-100PG84B XC1765DDD8B XC3042 5962-9471701MPA xc2018-70pg84b XC304270pg84b XC3042-70PG132B XC3042-50PG84B xc3042-50pg84
Text: 5962-8863803XC 5962-8863804XC Equivalent "B" Grade P/N XC2018 -33PG84B XC2018 -50PG84B XC2018 -70PG84B XC2018 -100PG84B Speed -33 -50 -70 -100 Package PG84 PG84 PG84 PG84 Mark Loc TOP TOP


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PDF 9230503MXC XC4010-5PG191B 5962-9230501MYC XC4010-10CB196B 5962-9230502MYC XC4010-6CB196B 5962-9230503MYC XC4010-5CB196B 5962-9230501MZC 5962-9230502MZC XC17256DDD8B XC3042-100PG84B XC1765DDD8B XC3042 5962-9471701MPA xc2018-70pg84b XC304270pg84b XC3042-70PG132B XC3042-50PG84B xc3042-50pg84
Not Available

Abstract: No abstract text available
Text: XC2018 XC2018L Vcc 5.0 3.3 5.0 3.3 V V V V Typ. Logic Capacity (gates) 6 0 0 -1 ,0 0 0 600 -1 ,0 0 0 1 , XC2064 has 64 such blocks arranged in an 8-row by 8-column matrix. The XC2018 has 100 logic blocks , cycles of the internal sampling clock (197 for the XC2018 ) to clear the internal memory before another , XC2018 , the configuration of each device requires 17,878 bits. The XC2064 uses 160 configuration data frames and the XC2018 uses 197. The configuration bit stream begins with preamble bits, a preamble code


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PDF XC2000 2064-70P TQ100 VQ100 XC2064 XC2018 MIL-STD-883C XC2064L XC2018L
Not Available

Abstract: No abstract text available
Text: K XC2064/ XC2018 Logic Cell™Array Product Specification FEATURES • Fully , speed grades. Part Number XC2064 XC2018 Logic Capacity (gates) 1200 1800 , -column matrix. The XC2018 has 100 logic blocks arranged in a 10 by 10 matrix. logic block inputs and the , . Typical global clock buffer power is about 3 mW / MHz for the XC2064 and 4 mW / MHz for the XC2018 . With , ,038 bits for each device. For the XC2018 , the configuration of each device requires 17,878 bits. The


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PDF XC2064/XC2018 XC2064/2018 84-Pin
XC3090-100PG175

Abstract: XC4025E-4PG299 xc3042-50pg84 XC3090-70PG175 XC3042-100PG84 XC3042-100PG132 XC4010-6CB196B XC4005E-4PG156B xc4010-6pg191 XC3142A-5
Text: DD8 : 7 Mark Loc TOP TOP Equivalent " B" Grade P/N XC2018 -33PG84B XC2018 -50PG84B XC2018 -70PG84B XC2018 -100PG84B Speed -33 -50 -70 -100 Package PG84 PG84 PG84 PG84 Mark Loc TOP TOP TOP TOP


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PDF Mil-l-38535 XC3090-100PG175 XC4025E-4PG299 xc3042-50pg84 XC3090-70PG175 XC3042-100PG84 XC3042-100PG132 XC4010-6CB196B XC4005E-4PG156B xc4010-6pg191 XC3142A-5
Not Available

Abstract: No abstract text available
Text: €¢ Performance equivalent to TTL SSI/MSI Device Vcc XC2064 XC2064L XC2018 XC2018L 5.0 3.3 5.0 , -column matrix. The XC2018 has 100 logic blocks arranged in a 10 by 10 matrix. Each logic block has a , the XC2064, configura­ tion requires 12,038 bits for each device. For the XC2018 , the configuration of each device requires 17,878 bits. The XC2064 uses 160 configuration data frames and the XC2018 , sampling clock (197 for the XC2018 ) to clear the internal memory before another configuration may begin


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PDF XC2000 XC2064 XC2064L XC2018 XC2018L XC2000L
1995 - XC2018

Abstract: 80196 programs 80196 internal architecture diagram IMS2000 XILINX xc2018 XC6200 xilinx 8051 XC3020 XC4002A memory space of 80196
Text: CONTROL XC2018 FPGA 256 x 4 RAM DATA CHANNEL SIGNALLING MICROCONTROLLER Operational mode: ­ Interface logic TIMING XC2018 FPGA TIMESLOT AND CONVERSION CONTROL NIBBLE , selects appropriate inspection criteria ­ Downloaded to XC2018 FPGAs Reconfigurable Logic Applications , : Printer Controller XC2018 implements printer ­ interface logic Configuration programs for ­ several


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1998 - XC3042-50PG84B

Abstract: XC4010E-4CB196B XC4010-5CB196B 5962-9752501QXC XC4010-6CB196B 5962-9752301QXC XC2018 XC3042-70PG84B XC3042-100PG84 5962-9752201QXC
Text: Grade P/N XC2018 -33PG84B XC2018 -50PG84B XC2018 -70PG84B XC2018 -100PG84B Speed -33 -50 -70 -100


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PDF MIL-PRF-38535 ISO-9000 Mil-I-38535 XC3042-50PG84B XC4010E-4CB196B XC4010-5CB196B 5962-9752501QXC XC4010-6CB196B 5962-9752301QXC XC2018 XC3042-70PG84B XC3042-100PG84 5962-9752201QXC
Not Available

Abstract: No abstract text available
Text: ) Configurable Logic Blocks 100 User l/Os Conflguratlon Program (bits) 17878 XC2018 1800 74 in , . See the XC2018 Commercial data sheet for a full descrip tion. DESCRIPTION The Logic CellTM Array , stored ORDERING INFORMATION XC2018 - 50 PG84B · B = MIL-STD-883, CLASS B. FULLY COMPLIANT 33 (33 , CONNECTED TO PIN C2. DIMENSIONS IN INCHES XC2018 : 84-Pin PGA Package STATIC BURN-IN CIRCUITS NOTES


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PDF XC2018B MIL-STD-883 XC2018 memory10 TSC0026
Supplyframe Tracking Pixel