The Datasheet Archive

Top Results (6)

Part Manufacturer Description Datasheet Download Buy Part
VTERB-BLK-XM-U4 Lattice Semiconductor Corporation LICENSE VITERBI DECODER XP
VTERB-BLK-X2-UT4 Lattice Semiconductor Corporation LICENSE VITERBI DECODER XP2
VTERB-BLK-P2-U4 Lattice Semiconductor Corporation IP CORE VITERBI DECODER ECP2
VTERB-BLK-PM-UT4 Lattice Semiconductor Corporation IP CORE VITERBI DECODER ECP2M
VTERB-BLK-X2-U4 Lattice Semiconductor Corporation IP CORE VITERBI DECODER XP2
VTERB-BLK-P2-UT4 Lattice Semiconductor Corporation IP CORE VITERBI DECODER ECP2

Viterbi Decoder datasheet (2)

Part Manufacturer Description Type PDF
Viterbi Decoder Lattice Semiconductor Viterbi Decoder Data Sheet Original PDF
Viterbi Decoders Altera Viterbi Decoders White Paper Original PDF

Viterbi Decoder Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
2000 - GSM Viterbi

Abstract: Viterbi Decoder Trellis branch metric Viterbi Trellis Decoder Convolutional viterbi trellis 5/6 decoder GSM state transition diagram SP11
Text: How to Implement a Viterbi Decoder on the StarCore SC140 Application Note Abstract The application note describes how to implement an efficient Viterbi decoder on the StarCore SC140. It begins , description of the StarCore SC140 special instructions that allow you to program an efficient Viterbi decoder , Implement a Viterbi Decoder on the StarCore SC140 Page i Table of Contents Chapter 6: Optimizations to the Viterbi Decoder Kernel . . . . . . . . . . . . . . . . 47 6.1 Memory Map of the Kernel . .


Original
PDF SC140 SC140. SC140 GSM Viterbi Viterbi Decoder Trellis branch metric Viterbi Trellis Decoder Convolutional viterbi trellis 5/6 decoder GSM state transition diagram SP11
Not Available

Abstract: No abstract text available
Text: ispLever CORE TM Viterbi Decoder User’s Guide October 2005 ipug04_02.0 Lattice Semiconductor Viterbi Decoder User’s Guide Introduction Lattice’s Viterbi Decoder core is a , given in the next section. Viterbi Decoder Basics Viterbi decoding is an efficient algorithm for , Figure 1, which uses a Viterbi decoder for decoding the convolutionally coded data. The digital data , demodulated and then decoded using the Viterbi decoder . The decoded output is equivalent to the transmitted


Original
PDF ipug04 LFX1200B, FE680,
2010 - Not Available

Abstract: No abstract text available
Text: Block Viterbi Decoder User’s Guide June 2010 IPUG32_02.7 Table of Contents Chapter 1 , . 10 Configuring the Block Viterbi Decoder , . 12 Interfacing with the Block Viterbi Decoder , change without notice. IPUG32_02.7, June 2010 2 Block Viterbi Decoder User’s Guide Lattice , . 34 IPUG32_02.7, June 2010 3 Block Viterbi Decoder User’s Guide Chapter 1


Original
PDF IPUG32 2004-OFDM LFXP2-17E-7F484C D-2009 12L-1
1999 - X9009

Abstract: verilog code for BPSK qpsk implementation using verilog qpsk modulation VHDL CODE branch metric 2 bit address decoder coding using verilog hdl BPSK modulation VHDL CODE verilog code for branch metric unit branch metric unit VHDL coding verilog code for digital modulation
Text: Soft-Decision Viterbi Decoder April 19, 1999 Product Specification AllianceCORETM Facts Core , Trace-Back Length Number of ACS Element 1/2 7 3 55 4 Soft-Decision Viterbi Decoder Branch Metric Unit , : Soft-Decision Viterbi Decoder Block Diagram General Description A Viterbi decoder performs a maximum , 2 shows the simplified data path from the Convolutional Encoder to the Viterbi Decoder . The source , applications. The Viterbi Decoder netlist can also be delivered with customized parameter settings differing


Original
PDF V50-6 X9009 verilog code for BPSK qpsk implementation using verilog qpsk modulation VHDL CODE branch metric 2 bit address decoder coding using verilog hdl BPSK modulation VHDL CODE verilog code for branch metric unit branch metric unit VHDL coding verilog code for digital modulation
2000 - about the decoder ic

Abstract: ic 7495 shift registers SC140 SP10 SP11 SP12 SP14 Viterbi Trellis Decoder
Text: Freescale Semiconductor, Inc. How to Implement a Viterbi Decoder on the StarCore SC140 , implement an efficient Viterbi decoder on the StarCore SC140. It begins with an overview of convolutional , instructions that allow you to program an efficient Viterbi decoder . The note describes how to efficiently , concludes with optimized assembly code for a complete Viterbi decoder according to the GSM TCH/FS standard , Viterbi Decoder on the StarCore SC140 This Product, For More Information On Go to: www.freescale.com


Original
PDF SC140 SC140. SC140 about the decoder ic ic 7495 shift registers SP10 SP11 SP12 SP14 Viterbi Trellis Decoder
1998 - ram memory testbench vhdl

Abstract: testbench vhdl ram 16 x 4 ram memory testbench vhdl code acs transistor Viterbi Decoder Viterbi ram memory vhdl Viterbi Trellis Decoder viterbi EPF10K30A EPF6016
Text: Viterbi Decoder Megafunction Solution Brief 33 Target Applications: Data Communications , General Description The Viterbi decoder megafunction is used to decode convolutional codes. It can also , interference (ISI). Figure 1 shows the symbol for the Viterbi decoder megafunction. Figure 1. Viterbi Decoder Symbol Bits2Smu[X.0] Web RstX CLK Oeb Viterbi Decoder LoadData AdSmu[X , adapted to a wide variety of applications. Figure 2 shows the block diagram for the Viterbi decoder


Original
PDF EPF10K30A, EPF6016, ram memory testbench vhdl testbench vhdl ram 16 x 4 ram memory testbench vhdl code acs transistor Viterbi Decoder Viterbi ram memory vhdl Viterbi Trellis Decoder viterbi EPF10K30A EPF6016
2005 - Viterbi Decoder

Abstract: viterbi introduction to viterbi decoder
Text: . "Parallel Viterbi Decoder Fails When Number of Code Sets 5 and N = 2" on page 1. 2. "Parallel Viterbi Decoder May Fail to Assert sink_ena_master" on page 2. 3. "Parallel Viterbi Decoder May Produce Spurious source_val Assertions" on page 3. Parallel Viterbi Decoder Fails When Number of Code Sets 5 and N = 2 For the parallel Viterbi decoder , if you choose 5 or more for Number of Code Sets with every code set with N = 2 and in Viterbi mode, the Viterbi decoder fails in one of two ways. If


Original
PDF
2000 - 5 to 32 decoder using 3 to 8 decoder vhdl code

Abstract: branch metric BPSK modulation VHDL CODE verilog code for BPSK 5 to 32 decoder using 3 to 8 decoder verilog qpsk modulation VHDL CODE QPSK using xilinx vhdl code for modulation X9009 Viterbi Decoder
Text: Soft-Decision Viterbi Decoder January 10, 2000 Product Specification AllianceCORETM Facts , RST X9008 Figure 1: Soft-Decision Viterbi Decoder Block Diagram General Description Branch Metric Unit (BMU) A Viterbi decoder performs a maximum likelihood detection of 1-bit data transmitted , from the Convolutional Encoder to the Viterbi Decoder . The Branch Metric Unit calculates the , for easy adaptation to a wide variety of applications. The Viterbi Decoder netlist can also be


Original
PDF
2000 - branch metric

Abstract: Convolutional Encoder details and application GSM Viterbi SC140 SP10 SP11 SP12 SP14
Text: Freescale Semiconductor, Inc. How to Implement a Viterbi Decoder on the StarCore SC140 , implement an efficient Viterbi decoder on the StarCore SC140. It begins with an overview of convolutional , instructions that allow you to program an efficient Viterbi decoder . The note describes how to efficiently , concludes with optimized assembly code for a complete Viterbi decoder according to the GSM TCH/FS standard , . 46 How to Implement a Viterbi Decoder on the StarCore SC140 This Product, For More Information


Original
PDF SC140 SC140. SC140 branch metric Convolutional Encoder details and application GSM Viterbi SP10 SP11 SP12 SP14
MIL-STD-188-182

Abstract: MIL-STD-188-183 MIL-STD-188-183A MIl-STD-188-181B MIL-STD-188-181 16 bit qpsk VHDL CODE MIl-STD-188181B MIL-STD 188-181B Viterbi Decoder Convolutional
Text: Dual Constraint Length Viterbi Decoder March, 1999, ver. 2.1.1_ Data Sheet (PN F805SC , Re-Programmable for Customized Interfaces and Processing Algorithms Viterbi Decoder Modes: v Dual Constraint , =7 rate 3/4, Punctured k=7 rate 7/8, and k=9, rate 3/4. Viterbi Decoder Function r (2:0 , Nova Engineering, Inc. Viterbi Decoder Data Sheet P1 = 171 (octal) Encoder Data In P2 = , Figure FEC-3: Viterbi Decoder Block Diagram Page 2 Nova Engineering, Inc. Viterbi Decoder Data


Original
PDF F805SC) MIL-STD-188-181 MIL-STD-188-182 MIL-STD-188-183 860-ming MIL-STD-188-182 MIL-STD-188-183 MIL-STD-188-183A MIl-STD-188-181B MIL-STD-188-181 16 bit qpsk VHDL CODE MIl-STD-188181B MIL-STD 188-181B Viterbi Decoder Convolutional
1998 - branch metric

Abstract: Viterbi Decoder viterbi algorithm IS-136 DSP56600 DSP56300 Viterbi Trellis Decoder texas trellis 5/6 decoder branch metric report Convolutional decoder
Text: code polynomials, the assembly code needed for implementation of a Viterbi decoder . Motorola , . . . . . . . . . . . . . . . 2-3 2.3 Viterbi Decoder . . . . . . . . . . . . . . . . . . . . . . . , 5-3 MOTOROLA Viterbi Decoder Implementation iii 5.2 5.3 Conclusions . . . . . . . . . , -Bit Enhanced Viterbi Decoder PROGRAM LISTING . . . . . . B-3 APPENDIX C 24-Bit Algorithm Program Listing . . . . . . . . . . . . . . C-1 C.1 24-Bit Enhanced Viterbi Decoder PROGRAM LISTING . . . . . . C


Original
PDF DSP56300 DSP56600 APR40/D branch metric Viterbi Decoder viterbi algorithm IS-136 DSP56600 Viterbi Trellis Decoder texas trellis 5/6 decoder branch metric report Convolutional decoder
1998 - vhdl code for march c algorithm

Abstract: Viterbi Decoder Viterbi Trellis Decoder sample vhdl code for memory write vhdl code for branch metric unit viterbi trans metrics viterbi algorithm ram memory vhdl Viterbi ram memory vhdl
Text: Viterbi Decoder February 8, 1998 Product Specification AllianceCORETM Facts CAST, Inc , memory (RAM) word length Value 16 8 4 30 5 -4 8 Viterbi Decoder RstX Clk LoadData , General Description Viterbi_Memory A Viterbi decoder is used for decoding convolutional codes. It , example only. The Viterbi Decoder can be delivered in a specific format (see Ordering Information). The Viterbi Decoder core can be customized to include: Core Modifications Viterbi_AcsUnit ·


Original
PDF
2003 - Trellis

Abstract: viterbi IESS-308/309 Viterbi Trellis Decoder viterbi decoder for tcm decoders viterbi convolution express card DVB IESS-308/309 XAPP551 XC3S100E
Text: 0 Viterbi Decoder v6.2 DS247 October 10, 2007 Product Specification 0 Introduction The Viterbi Decoder is used in many Forward Error Correction (FEC) applications and in systems where data are transmitted and subject to errors before reception. The Viterbi Decoder is compatible with , , compact Viterbi Decoder · Available for VirtexTM-II, Virtex-II Pro, Virtex-4, Virtex-5, SpartanTM , decoder · Serial architecture for small area This core implements a Viterbi Decoder for decoding


Original
PDF DS247 IESS-308/309. Trellis viterbi IESS-308/309 Viterbi Trellis Decoder viterbi decoder for tcm decoders viterbi convolution express card DVB IESS-308/309 XAPP551 XC3S100E
1997 - vhdl code for branch metric unit

Abstract: branch metric Viterbi Decoder viterbi algorithm branch metric unit VHDL design viterbi Signal Path Designer Viterbi Trellis Decoder AC121 A32200DX
Text: codes. The Viterbi decoder performs maximumlikelihood decoding to achieve optimum performance. However, the Viterbi decoder requires extensive hardware for computation and storage. The Viterbi algorithm , codes. The Viterbi decoder is especially good for short constraint length, and it makes decoding , time, and each branch represents a transition to other states at the next stage. The Viterbi decoder , e V i te rb i D e c o d e r A rc h i te c tu re The Viterbi decoder is divided into three


Original
PDF AC121 vhdl code for branch metric unit branch metric Viterbi Decoder viterbi algorithm branch metric unit VHDL design viterbi Signal Path Designer Viterbi Trellis Decoder AC121 A32200DX
2003 - Viterbi Trellis Decoder

Abstract: Viterbi Decoder branch metric viterbi algorithm viterbi parallel viterbi convolution polynomials LFX1200B Convolutional viterbi convolution
Text: Viterbi Decoder March 2003 IP Data Sheet Features General Description Parameterizable Viterbi decoder Viterbi decoding is an efficient algorithm for decoding convolutionally encoded sequences. In the Viterbi Decoder , the convolutional code sequences that have been corrupted by channel , Decoder Top-level Block Diagram din_0 dout din_1 din_2 clk valid Viterbi Decoder pd_out , 1 ip1016_01 Lattice Semiconductor Viterbi Decoder Figure 2. 1/2 Rate Convolutional


Original
PDF LFX1200B, FE680, Viterbi Trellis Decoder Viterbi Decoder branch metric viterbi algorithm viterbi parallel viterbi convolution polynomials LFX1200B Convolutional viterbi convolution
L64711

Abstract: OXF*9 L64709 H14002 L6471 L64714 L64713 viterbi algorithm 65 ber l64711 LSI
Text: . Preface v Chapter 6, Viterbi Decoder Module, describes the structure and operation of the Viterbi decoder module. Chapter 7, Deinterleaver Module, describes how the data stream is reordered , Output 4.4.6 Viterbi Decoder Output 4.4.7 Viterbi Depuncture/Synchronization Output Synchronization 5.1 Synchronization Scheme 5.2 Viterbi Decoder Synchronization 5.3 Reed-Solomon Deinterleaver Synchronization 5.4 Descrambler Synchronization Viterbi Decoder Module 6.1 Viterbi Decoder Architecture 6.1.1 Features 6.1.2 Code


OCR Scan
PDF L64709 DB14-000011-00, 415-940-6rs L64711 OXF*9 H14002 L6471 L64714 L64713 viterbi algorithm 65 ber l64711 LSI
2003 - XCV5LX50

Abstract: branch metric parallel viterbi convolution Convolutional Encoding Viterbi Decoding Using DSP
Text: 0 Viterbi Decoder v6.1 DS247 May 17, 2006 0 Product Specification Introduction The Viterbi Decoder is used in many Forward Error Correction (FEC) applications and in systems where data are transmitted and subject to errors before reception. The Viterbi Decoder is compatible with many common , Generator Features · High-speed, compact Viterbi Decoder · Available for VirtexTM-II, Virtex-II Pro , DS247_01_051806 BMU Costs to each state ACS TB Figure 1: Viterbi Decoder Block Diagram


Original
PDF DS247 IESS-308/309. XCV5LX50 branch metric parallel viterbi convolution Convolutional Encoding Viterbi Decoding Using DSP
1997 - vhdl code for branch metric unit

Abstract: vhdl program for branch metric unit branch metric unit VHDL design digital clock using logic gates counting second vhdl code for 8 bit ram Signal Path Designer
Text: metric in the last stage. T h e V i te rb i D e c o d e r A rc h i te c tu re The Viterbi decoder is , trace-back technique. Technical Data Freeway's (TDF) VHDL model of the Viterbi decoder is based on the trace-back technique and is described in more detail in the data sheet. The Viterbi decoder block diagram is , . The Viterbi decoder performs maximumlikelihood decoding to achieve optimum performance. However, the Viterbi decoder requires extensive hardware for computation and storage. The Viterbi algorithm is used not


Original
PDF A32he A32200DX vhdl code for branch metric unit vhdl program for branch metric unit branch metric unit VHDL design digital clock using logic gates counting second vhdl code for 8 bit ram Signal Path Designer
scrambler satellite

Abstract: qualcomm IQ AN1650-1 AN1650-2 R0702 Viterbi Decoder Q1650 InMarSat modulator IESS-308 encoder puncture qualcomm
Text: Qualco/wva Q1650 k=7 MULTI-CODE RATE VITERBI DECODER 2.5, 10, 25 Mbps Data Rates Technical Data Sheet Powered by ICminer.com Electronic-Library Service CopyRight 2003 2 Q1650 Viterbi Decoder , CopyRight 2003 Q1650 Viterbi Decoder 3 CONTENTS Title Page FEATURES , .6 Convolutional Encoder.6 Viterbi Decoder , ICminer.com Electronic-Library Service CopyRight 2003 4 Q1650 Viterbi Decoder 4 FEATURES • Stand-Alone


OCR Scan
PDF Q1650 Q1650 scrambler satellite qualcomm IQ AN1650-1 AN1650-2 R0702 Viterbi Decoder InMarSat modulator IESS-308 encoder puncture qualcomm
2003 - Viterbi Trellis Decoder

Abstract: IESS-308/309 phase noise 5VLX30 IESS-308/309 6VLX75T FPGA Virtex-6 LXT spartan-6fpgas viterbi IESS-308/309 viterbi convolution XC3S100E
Text: 0 Viterbi Decoder v7.0 DS247 June 24, 2009 Product Specification 0 Introduction The Viterbi Decoder is used in many Forward Error Correction (FEC) applications and in systems where data are transmitted and subject to errors before reception. The Viterbi Decoder is compatible with many , 3 to 9 This core implements a Viterbi Decoder for decoding convolutionally encoded data. For , Traceback Best path to each state TB Decoded data DS247_01_051806 Figure 1: Viterbi Decoder


Original
PDF DS247 IESS-308/309. Viterbi Trellis Decoder IESS-308/309 phase noise 5VLX30 IESS-308/309 6VLX75T FPGA Virtex-6 LXT spartan-6fpgas viterbi IESS-308/309 viterbi convolution XC3S100E
2001 - CS3411

Abstract: Viterbi Decoder CS3410 viterbi IESS-308/309 CS3311 IESS-308 Convolutional Encoder details and application CSC3411AA base-10
Text: CS3411 TM High Speed Viterbi Decoder Virtual Components for the Converging World The CS3411 Viterbi Decoder is a high performance implementation suitable for a range of Forward Error , consumption and silicon area. Noise Data In CS3311 Convolutional Encoder CS3411 Viterbi Decoder , of products 1 CS3411 High Speed Viterbi Decoder CONVOLUTIONAL CODES FOR ERROR , Viterbi decoder is typically used for systems that are power-limited systems. As a result, the CS3411 is


Original
PDF CS3411 CS3411 CS3311 DS3411 Viterbi Decoder CS3410 viterbi IESS-308/309 CS3311 IESS-308 Convolutional Encoder details and application CSC3411AA base-10
1998 - branch metric

Abstract: Viterbi Decoder Viterbi Trellis Decoder Viterbi Trellis Decoder texas DSP56300 DSP56600 IS-136
Text: needed for implementation of a Viterbi decoder . Motorola, Incorporated Semiconductor Products Sector , . . . . . . . . . . . . . . . . 2-3 2.3 Viterbi Decoder . . . . . . . . . . . . . . . . . . . . . . , . . . . . . . . 5-3 MOTOROLA Viterbi Decoder Implementation For More Information On This , Program Listing . . . . . . . . . . . B-1 B.1 16-Bit Enhanced Viterbi Decoder PROGRAM LISTING . . . . . , -Bit Enhanced Viterbi Decoder PROGRAM LISTING . . . . . . C-3 iv Viterbi Decoder Implementation For


Original
PDF DSP56300 DSP56600 APR40/D branch metric Viterbi Decoder Viterbi Trellis Decoder Viterbi Trellis Decoder texas DSP56600 IS-136
1997 - how to make satellite decoder circuit

Abstract: block diagram satellite transponder Viterbi Decoder satellite decoder circuit diagram dvb circuit diagram viterbi decoder soft bit 128QFP Transponder motorola 128-QFP MC92300CG
Text: Product Preview VITERBI Decoder for Digital TV DTVVIT This product preview describes a high performance device, a Viterbi Decoder , for Digital-TV applications according to the EBU defined DVB , ] Viterbi Decoder - Capability Specification · · · · · · BITCLK VC0,VC1[2:0] VO VLCK VFF , Implements K=7, (1718,1338) Viterbi decoder for rates 1/2, 2/3, 3/4, 5/6 and 7/8 with a survivor depth of 96 , Description The Viterbi Decoder contains the Viterbi core logic, which operates the K=7 convolutional code


Original
PDF MC92300 50MBits/s how to make satellite decoder circuit block diagram satellite transponder Viterbi Decoder satellite decoder circuit diagram dvb circuit diagram viterbi decoder soft bit 128QFP Transponder motorola 128-QFP MC92300CG
2004 - Viterbi Decoder

Abstract: DSP56300 DSP56600 IS-136
Text: polynomials, the assembly code needed for implementation of a Viterbi decoder . © Freescale Semiconductor , Viterbi Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 2.4 , . . . . . . . . . . . . . . . . . . . . . . . . 5-3 Viterbi Decoder Implementation For More , Program Listing . . . . . . . . . . . B-1 B.1 16-Bit Enhanced Viterbi Decoder PROGRAM LISTING . . . . . , -Bit Enhanced Viterbi Decoder PROGRAM LISTING . . . . . . C-3 iv Viterbi Decoder Implementation For


Original
PDF DSP56300 DSP56600 APR40/D Viterbi Decoder DSP56600 IS-136
Qualcomm application note

Abstract: AN1650-2 AN1650-1 Setting Soft-Decision Thresholds for Viterbi Qualcomm Application Note AN1650-2 IESS-308 sCRAMBLER IESS-308 InMarSat demodulator qualcomm Application Note AN1650 encoder puncture qualcomm
Text: Qualco/wva Q1650 k=7 MULTI-CODE RATE VITERBI DECODER 2.5, 10, 25 Mbps Data Rates Technical Data Sheet This Material Copyrighted By Its Respective Manufacturer 2 Q1650 Viterbi Decoder 2 , Manufacturer Q1650 Viterbi Decoder 3 CONTENTS Title Page FEATURES , .6 Convolutional Encoder.6 Viterbi Decoder , Copyrighted By Its Respective Manufacturer 4 Q1650 Viterbi Decoder 4 FEATURES • Stand-Alone Full-Duplex


OCR Scan
PDF Q1650 Q1650 Qualcomm application note AN1650-2 AN1650-1 Setting Soft-Decision Thresholds for Viterbi Qualcomm Application Note AN1650-2 IESS-308 sCRAMBLER IESS-308 InMarSat demodulator qualcomm Application Note AN1650 encoder puncture qualcomm
Supplyframe Tracking Pixel