The Datasheet Archive

VP2611 datasheet (5)

Part Manufacturer Description Type PDF
VP2611 Mitel Semiconductor H.261 Encoder Original PDF
VP2611 Zarlink Semiconductor H.261 Encoder Original PDF
VP2611/CG/GH1N Zarlink Semiconductor Encoder, H.261 Encoder Original PDF
VP2611/CG/GH1R Zarlink Semiconductor Encoder, H.261 Encoder (Video Compression Source Coder) Original PDF
VP2611CGGH1R Zarlink Semiconductor H.261 Encoder Original PDF

VP2611 Datasheets Context Search

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Not Available

Abstract: No abstract text available
Text: , CBUS3:0, are used when writing instructions to the VP2611. The remaining bits, CBUS7.4, should be pulled low while the instruction is strobed into the VP2611. The instructions listed in Table 3 are , Si GEC PLESSEY S E M I C O N D U C T O R S VP2611 H.261 ENCODER (Supersedes January 1996 , VP2615 H.261 Decoder The VP2611 Video Compression Source Coder forms part of a chip set used in video , through the device is only 3 macro block periods. The VP2611 contains all the elements necessary for the


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PDF VP2611 DS3478 VP510 VP520S VP2612 VP2614 VP2615 VP2611 CLK54) GH128
2006 - DS3487

Abstract: H261 VP2611 VP2612 VP2614 VP2615 VP510 VP520 VP520S
Text: a typical Sub-block being output from the VP2611. DCLK DMODE 15 7 8 9 15 8 , writing instructions to the VP2611. The remaining bits, CBUS7:4, should be pulled low while the instruction is strobed into the VP2611. The instructions listed in Table 3 are described below in greater , visit http://products.zarlink.com/obsolete_products/ VP2611 VP2611 H.261 Encoder Supersedes , store s QFP package The VP2611 Video Compression Source Coder forms part of a chip set used in


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PDF VP2611 DS3487 H261 VP2611 VP2612 VP2614 VP2615 VP510 VP520 VP520S
Not Available

Abstract: No abstract text available
Text: differential motion vectors and macroblock addresses from the absolute values received from the VP2611. These , DESCRIPTIONS DBUS7:0 The input data bus from VP2611. The data type is defined by the value present on DMODE3 , VP2611. Thus it will be compatible with any future upgrades to the VP2611 that increase the size of the , frames. MTICK This output pulses high once for every Macroblock received from the VP2611. The pulse is , address was received from the VP2611. ft is anticipated that this should be used to clock a counter in


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PDF DS3511 VP2612 HB3923-1) VP2612 27MHz VP2611 37fciÃ
DS3487

Abstract: VP520S VP520 VP510 VP2615 VP2614 VP2612 VP2611 H261 1996 yuv rgb conversion frame buffer
Text: a typical Sub-block being output from the VP2611. DCLK DMODE 15 7 8 9 15 8 , writing instructions to the VP2611. The remaining bits, CBUS7:4, should be pulled low while the instruction is strobed into the VP2611. The instructions listed in Table 3 are described below in greater , VP2611 VP2611 H.261 Encoder Supersedes June 1996 edition, DS3487 - 4.0 DS3487 - 4.1 , Addresses and control generated internally for DRAM frame store s QFP package The VP2611 Video


Original
PDF VP2611 DS3487 VP2611 VP520S VP520 VP510 VP2615 VP2614 VP2612 H261 1996 yuv rgb conversion frame buffer
2002 - DS3487

Abstract: H261 VP2611 VP2612 VP2614 VP2615 VP510 VP520 VP520S
Text: a typical Sub-block being output from the VP2611. DCLK DMODE 15 7 8 9 15 8 , writing instructions to the VP2611. The remaining bits, CBUS7:4, should be pulled low while the instruction is strobed into the VP2611. The instructions listed in Table 3 are described below in greater , VP2611 VP2611 H.261 Encoder Supersedes June 1996 edition, DS3487 - 4.0 DS3487 - 4.1 , Addresses and control generated internally for DRAM frame store s QFP package The VP2611 Video


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PDF VP2611 DS3487 VP2611 H261 VP2612 VP2614 VP2615 VP510 VP520 VP520S
MACROBIOCK

Abstract: No abstract text available
Text: from the VP2611. DCLK DMODE DBUS _ 15X X X I 7 I 1 1 1 CM _ n _ n _ n _ n L_n_n_ X X , , are used when writing instructions to the VP2611. The remaining bits, CBUS7:4, should be pulled low while the instruction is strobed into the VP2611. The instructions listed in Table 3 are described below , MITEL QPvynrnMni inrm o Supersedes June 1996 edition, DS3487 - 4.0 VP2611 H.261 Encoder , Transmission System VP2611 PIN DESCRIPTIONS YUV7:0 This input bus accepts YUV data one pixel at a time


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PDF DS3487 VP2611 MACROBIOCK
gc132

Abstract: No abstract text available
Text: writing instructions to the VP2611. The remaining bits, CBUS7:4, should be pulled low while the instruction is strobed into the VP2611. The instructions listed in Table 3 are described below in greater , DS3478 - 2.3 VP2611 H.261 ENCODER (Supersedes version in December 1993 Digital Video & DSP 1C , 37b6SBE D0S3Z03 1^7 VP2611 PIN DESCRIPTIONS R/W1 Read/Write control for external DRAM 1 , the VP2611 to code a new frame. It must be held high for at least one SYSCLK cycle and then must be


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PDF DS3478 VP2611 HB3923-1) VP510 VP520CIF/QCIF VP2612 VP2614 VP2615 P2611 37bflS22 gc132
Not Available

Abstract: No abstract text available
Text: , specified in figure 10. Only the four LSBs, CBUS3:0, are used when writing instructions to the VP2611. The remaining bits, CBUS7:4, should be pulled low while the instruction is strobed into the VP2611. The , S i GEC PLESSEY ADVANCE INFORMATION S E M I C O N D U C T O R S VP2611 H.261 ENCODER , – On chip motion vector estimator with +/-7 pixel search The VP2611 Video Compression Source C , Hz frame rates. The pipeline latency through the device is only 3 macro block periods. The VP2611


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PDF VP2611 H83923-1) VP2611 CLK54) 002433b
1999 - DS3487

Abstract: H261 VP2611 VP2612 VP2614 VP2615 VP510 VP520 VP520S
Text: a typical Sub-block being output from the VP2611. DCLK DMODE 15 7 8 9 15 8 , writing instructions to the VP2611. The remaining bits, CBUS7:4, should be pulled low while the instruction is strobed into the VP2611. The instructions listed in Table 3 are described below in greater , VP2611 VP2611 H.261 Encoder Supersedes June 1996 edition, DS3487 - 4.0 DS3487 - 4.1 , Addresses and control generated internally for DRAM frame store s QFP package The VP2611 Video


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PDF VP2611 DS3487 VP2611 H261 VP2612 VP2614 VP2615 VP510 VP520 VP520S
Not Available

Abstract: No abstract text available
Text: ction s w ill be forced low. This diagram shows a typical Sub-block being output trom the VP2611. , into the VP2611. The instructions listed in Table 3 are described below in greater detail; Input VAR , © M ITEL _ VP2611 H.261 Encoder DS3487 - 4.0 June 1996 SE M IC O N D U C T O , and control generated internally for DRAM frame store QFP package DESCRIPTION The VP2611 Video , Conferencing Transmission System VP2611 PIN DESCRIPTIONS YUV7:0 This input bus accepts YUV data one pixel


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PDF VP2611 DS3487 VP2611
2001 - Not Available

Abstract: No abstract text available
Text: . This diagram shows a typical Sub-block being output from the VP2611. DCLK DMODE DBUS 15 X 7 2 8 0 9 , writing instructions to the VP2611. The remaining bits, CBUS7:4, should be pulled low while the instruction is strobed into the VP2611. The instructions listed in Table 3 are described below in greater , VP2611 H.261 Encoder Supersedes June 1996 edition, DS3487 - 4.0 DS3487 - 4.1 December 1998 VP2611 FEATURES DESCRIPTION The VP2611 Video Compression Source Coder forms part of a chip set


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PDF VP2611 DS3487 VP2611
1999 - Pin and function compatible VP2612

Abstract: VP520S VP510 VP2615 VP2614 VP2612 VP2611 H261 TXA11 16 line to 4 line coder multiplexer
Text: addresses from the absolute values received from the VP2611. These values are variable length coded, and , this Chip Enable should be used. PIN DESCRIPTIONS DBUS7:0 The input data bus from VP2611. The , +7/-8 motion vectors produced by the VP2611. Thus it will be compatible with any future upgrades to , Macroblock received from the VP2611. The pulse is 3 clock cycles in duration, and the leading edge will occur 6 SCLK cycles after the Macroblock address was received from the VP2611. It is anticipated that


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PDF VP2612 HB3923-2 VP2611 64kbits/s VP2615 VP2614 VP520S VP510 DS3511 Pin and function compatible VP2612 VP2612 H261 TXA11 16 line to 4 line coder multiplexer
1994 - Not Available

Abstract: No abstract text available
Text: absolute values received from the VP2611. These values are variable length coded, and bit packed for , be used. PIN DESCRIPTIONS DBUS7:0 The input data bus from VP2611. The data type is defined by , +7/-8 motion vectors produced by the VP2611. Thus it will be compatible with any future upgrades to , high once for every Macroblock received from the VP2611. The pulse is 3 clock cycles in duration, and the leading edge will occur 6 SCLK cycles after the Macroblock address was received from the VP2611.


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PDF DS3511 VP2612 HB3923-1) VP2611 64kbits/s VP2615 VP2614 VP520 VP2612
2002 - H261

Abstract: VP2611 VP2612 VP2614 VP2615 VP510 VP520S 16 line to 4 line coder multiplexer
Text: addresses from the absolute values received from the VP2611. These values are variable length coded, and , this Chip Enable should be used. PIN DESCRIPTIONS DBUS7:0 The input data bus from VP2611. The , +7/-8 motion vectors produced by the VP2611. Thus it will be compatible with any future upgrades to , Macroblock received from the VP2611. The pulse is 3 clock cycles in duration, and the leading edge will occur 6 SCLK cycles after the Macroblock address was received from the VP2611. It is anticipated that


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PDF VP2612 HB3923-2 VP2611 64kbits/s VP2615 VP2614 VP520S VP510 DS3511 H261 VP2612 16 line to 4 line coder multiplexer
2002 - H261

Abstract: VP2611 VP2612 VP2614 VP2615 VP510 VP520S "Overflow detection"
Text: addresses from the absolute values received from the VP2611. These values are variable length coded, and , this Chip Enable should be used. PIN DESCRIPTIONS DBUS7:0 The input data bus from VP2611. The , +7/-8 motion vectors produced by the VP2611. Thus it will be compatible with any future upgrades to , Macroblock received from the VP2611. The pulse is 3 clock cycles in duration, and the leading edge will occur 6 SCLK cycles after the Macroblock address was received from the VP2611. It is anticipated that


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PDF VP2612 HB3923-2 VP2611 64kbits/s VP2615 VP2614 VP520S VP510 DS3511 H261 VP2612 "Overflow detection"
Not Available

Abstract: No abstract text available
Text: the four LSBs, CBUS3:0, are used when writing instructions to the VP2611. The remaining bits, CBUS7:4 , VP2611 H.261 Encoder S E M IG O tV ID L IO lfO ß Supersedes June 1996 edition, DS3487 - 4.0 , System VP2611 PIN DESCRIPTIONS R/W1 YUV7:0 This input bus accepts YUV data one pixel at a , . FRMIN REQYUV This input should be pulled high to prepare the VP2611 to code a new frame. It must , begins. The VP2611 will respond to the rising edge of FRMIN by asserting REQYUV appproximately 184


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PDF VP2611 DS3487 pi115 CLK54) GH128
1996 - Not Available

Abstract: No abstract text available
Text: Sub-block being output from the VP2611. DCLK DMODE 15 7 8 9 15 8 9 15 8 9 , specified in figure 10. Only the four LSBs, CBUS3:0, are used when writing instructions to the VP2611. The remaining bits, CBUS7:4, should be pulled low while the instruction is strobed into the VP2611. The , VP2611 JANUARY 1996 ADVANCE INFORMATION DS3478 - 3.0 VP2611 H.261 ENCODER (Supersedes , store s QFP package The VP2611 Video Compression Source Coder forms part of a chip set used in


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PDF VP2611 DS3478 HB3923-2) VP2611
2003 - VP510

Abstract: VP2615 VP2614 VP2612 VP2611 H261 DS3487 VP520S VP520 PAL colour coder block diagram
Text: a typical Sub-block being output from the VP2611. DCLK DMODE 15 7 8 9 15 8 , writing instructions to the VP2611. The remaining bits, CBUS7:4, should be pulled low while the instruction is strobed into the VP2611. The instructions listed in Table 3 are described below in greater , VP2611 VP2611 H.261 Encoder Supersedes June 1996 edition, DS3487 - 4.0 DS3487 - 4.1 , Addresses and control generated internally for DRAM frame store s QFP package The VP2611 Video


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PDF VP2611 DS3487 VP2611 VP510 VP2615 VP2614 VP2612 H261 VP520S VP520 PAL colour coder block diagram
Not Available

Abstract: No abstract text available
Text: addresses from the absolute values received from the VP2611. These values are variable length coded, and , used this Chip Enable should be used. PIN DESCRIPTIONS DBUS7:0 The input data bus from VP2611. , +7/-8 motion vectors produced by the VP2611. Thus it will be compatible with any future upgrades to , Macroblock received from the VP2611. The pulse is 3 clock cycles in duration, and the leading edge will occur 6 SCLK cycles after the Macroblock address was received from the VP2611. It Is anticipated that


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PDF DS35H VP2612 HB3923-2f VP2611 64kbits/s VP2612 27MHz
2006 - philips hd6

Abstract: H261 "Overflow detection" VP520S VP510 VP2615 VP2614 VP2612 VP2611 "TOPS"
Text: received from the VP2611. These values are variable length coded, and bit packed for temporary storage in , . PIN DESCRIPTIONS DBUS7:0 The input data bus from VP2611. The data type is defined by the value , VP2611. Thus it will be compatible with any future upgrades to the VP2611 that increase the size of the , frames. MTICK This output pulses high once for every Macroblock received from the VP2611. The pulse is , address was received from the VP2611. It is anticipated that this should be used to clock a counter in


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PDF VP2612 HB3923-2 VP2611 64kbits/s VP2615 VP2614 VP520S VP510 philips hd6 H261 "Overflow detection" VP2612 "TOPS"
Not Available

Abstract: No abstract text available
Text: Sub-block being output from the VP2611. DCLK DMODE du bs i _ 15 X L_n_n 7 X xx , , C BU S 3:0, are used when w riting instructions to the VP2611. The rem aining bits, CBUS7:4, should be pulled low while the instruction is strobed into the VP2611. The instructions listed in Table , VP2611 @ M ITEL H.261 Encoder SE M IC O N D U C T O R Supersedes January 1996 edition , 8 sub block format ■Outputs run length coded coefficients The VP2611 Video Compression


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PDF VP2611 DS3487 VP2611
Not Available

Abstract: No abstract text available
Text: functions will be forced low. This diagram shows a typical Sub-block being output from the VP2611. , writing instructions to the VP2611. The remaining bits, CBUS7:4, should be pulled low while the instruction is strobed into the VP2611. The instructions listed in Table 3 are described below in greater , . The VP2611 contains all the elements necessary for the compression algorithm. It incorporates a , : Typical Video Conferencing Transmission System / VP2611 PIN DESCRIPTIONS R/W1 Read/Write


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PDF DS3478 TheVP2611
V2611

Abstract: "TOPS" data bus sytem "sub data bus" TXA11 VP520S VP510 VP2615 VP2614 VP2612 VP2611
Text: addresses from the absolute values received from the VP2611. These values are variable length coded, and , this Chip Enable should be used. PIN DESCRIPTIONS DBUS7:0 The input data bus from VP2611. The , +7/-8 motion vectors produced by the VP2611. Thus it will be compatible with any future upgrades to , Macroblock received from the VP2611. The pulse is 3 clock cycles in duration, and the leading edge will occur 6 SCLK cycles after the Macroblock address was received from the VP2611. It is anticipated that


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PDF VP2612 HB3923-2 VP2611 64kbits/s VP2615 VP2614 VP520S VP510 DS3511 V2611 "TOPS" data bus sytem "sub data bus" TXA11 VP2612
VMUX

Abstract: No abstract text available
Text: vectors and macroblock addresses from the absolute values received from 1he VP2611. These values are , input data bus from VP2611. The data type is defined by the value present on DMODE3:p TXE2 Active , produced by the VP2611. Thus it will be compatible with any future upgrades to the VP2611 that increase , output pulses high once for every Macroblock received from the VP2611. The pulse is 3 clock cycles in , VP2611. It is anticipated that this should be used to clock a counter in the system processor, so that


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PDF VP2612 HB3923-2) VP2612 27MHz VP2611 VMUX
2001 - TXA13

Abstract: No abstract text available
Text: differential motion vectors and macroblock addresses from the absolute values received from the VP2611. These , of the text. The input data bus from VP2611. The data type is defined by the value present on , accept ±15 motion vectors, rather than the +7/-8 motion vectors produced by the VP2611. Thus it will be , FEC stuffed frames. MTICK This output pulses high once for every Macroblock received from the VP2611. , Macroblock address was received from the VP2611. It is anticipated that this should be used to clock a


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PDF VP2612 HB3923-2 DS3511 VP2611 64kbits/s VP2615 VP2614 VP520S VP510 TXA13
Supplyframe Tracking Pixel