The Datasheet Archive

Top Results (6)

Part Manufacturer Description Datasheet Download Buy Part
SM320C31GFM33 Texas Instruments 32-BIT, 33MHz, OTHER DSP, CPGA141
TMS320LC31PQA-33 Texas Instruments 32-BIT, 33MHz, OTHER DSP, PQFP132
TMS320C30-33GEL Texas Instruments 32-BIT, 33MHz, OTHER DSP, CPGA181
SMJ320C31GFM33 Texas Instruments 32-BIT, 33MHz, OTHER DSP, CPGA141
TMS320C25-33FNL Texas Instruments 16-BIT, 33MHz, OTHER DSP, PQCC68
TMS320C31PQA33 Texas Instruments 32-BIT, 33MHz, OTHER DSP, PQFP132

V/33MHz Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
Not Available

Abstract: No abstract text available
Text: Q/2 ( 33MHz ) ' Q/2 ( 33MHz ) Q/2 ( 33MHz ) Q/2 ( 33MHz ) · 0 /2 ( 33MHz ) Q/2 ( 33MHz ) - 0/2 ( 33MHz ) Q/2 ( 33MHz ) · 0° Phase Shift ai 33MHz OPT2 0PT1 OPTO Q 1 0 011 012 Q13 0PT2 OPTI OPTO 010 011 , ) MC88PL117 FIL OE/MR PLL EN REF_SEL Q/2 lr> ( 33MHz )-SYNCO SYNC1 FEEDBACK 0PT2 0PT1 OPTO 00 Q1 Q2 Q3 04 , Q (66MHz) ' Q (66MHz) 0 (66MHz) Q (66MHz) ' Q/2 ( 33MHz ) Q/2 ( 33MHz ) Q/2 ( 33MHz ) Q/2 ( 33MHz ) Q/2 ( 33MHz ) Q/2 ( 33MHz ) · Q/2 ( 33MHz ) · 0° Phase Shift al 33MHz FIL OE/MR PLL EN REF_SEL Q/3 In (133M


OCR Scan
PDF C88PL117 88PL117 BR1333
1994 - WP-90516-19.66MHZ

Abstract: Mpc601
Text: Q/2 In ( 33MHz ) OE/MR PLL_EN REF_SEL SYNC0 SYNC1 FEEDBACK L H L OPT2 OPT1 OPT0 L L L ∅2 ∅1 ∅0 L H MULT1 MULT0 0° Phase Shift at 33MHz Q0 Q1 Q2 Q3 Q4 , ) MC88PL117 FIL H H L Q/2 In ( 33MHz ) OE/MR PLL_EN REF_SEL SYNC0 SYNC1 FEEDBACK L H H OPT2 , _Q (133MHz) 2X_Q (133MHz) Q (66MHz) Q (66MHz) Q (66MHz) Q (66MHz) Q/2 ( 33MHz ) Q/2 ( 33MHz ) Q/2 ( 33MHz ) Q/2 ( 33MHz ) Q/2 ( 33MHz ) Q/2 ( 33MHz ) Q/2 ( 33MHz ) Q/2 ( 33MHz ) QFEED QFEED FIL Q0 Q1


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PDF MC88PL117 MC88PL117 88PL117 MC88PL117/D* TIMINGMC88PL117/D BR1333 WP-90516-19.66MHZ Mpc601
1996 - MIPS 24k processor

Abstract: 80960SA 80960KB 80960KA 80960JF 80960JD 80960JA 80960HD 80960HA 80960CF
Text: 15 10.51 10 6.89 6.86 5 0 SA/SB 20Mhz KA/KB 25Mhz CA 33Mhz CF 33Mhz CF , PERFORMANCE 6 5 4.05 4 3.55 3.1 3 2 1 0 JA 33Mhz JF 33Mhz JD 25/50Mhz HA 40Mhz , 2000 1500 1207 1000 704 600 500 0 SA/SB 20Mhz KA/KB 25Mhz CA 33Mhz CF 33Mhz Figure 5. NET Relative Performance 8 CF 40Mhz i960® Microprocessor Benchmark Report , 400 262 236 HT 20/60Mhz HD 33/66Mhz 200 0 JA 33Mhz JF 33Mhz JD 25/50Mhz


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PDF sustainin12 20Mhz 25Mhz 33Mhz 40Mhz 25/50Mhz MIPS 24k processor 80960SA 80960KB 80960KA 80960JF 80960JD 80960JA 80960HD 80960HA 80960CF
2012 - 202003A

Abstract: No abstract text available
Text: DATA SHEET AAT2113B 3.3MHz , Fast Transient 1.5A Step-Down Converter in an 2mm x 2mm Package , of 3.3V and a fixed output voltage of 1.2V or an adjustable output. The 3.3MHz switching frequency , : 1.0V to 2.5V High Efficiency, Low Noise Architecture 3.3MHz Switching Frequency No External , DATA SHEET AAT2113B 3.3MHz , Fast Transient 1.5A Step-Down Converter in an 2mm x 2mm Package Pin , Information are Subject to Change Without Notice. · May 24, 2012 DATA SHEET AAT2113B 3.3MHz , Fast


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PDF AAT2113B AAT2113B 02003A 202003A
33MHz

Abstract: smd marking mp asxp
Text: max. Jitter 20µA max. ± 250ps max. for F<= 33MHz , ±100ps typ. ± 100ps max. for F> 33MHz , ±50ps typ. Peak to peak ± 250ps max. for F<= 33MHz , ±100ps typ. ± 125ps max. for F> 33MHz , ±75ps typ. ± 50ps max. for F<= 33MHz , ±30ps typ. ± 30ps max. for F> 33MHz , ±20ps typ. ± 50ps max. for F<= 33MHz , ±30ps typ. ± 30ps max. for F> 33MHz , ±20ps typ. RMS One sigma PATTERN VIH: 0.7*VDDmin


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PDF 50ppm 33MHz smd marking mp asxp
2010 - AAT2113B

Abstract: LQM2HPNR47MG0 murata mlc 0201 GRM155R60J105KE19D AAT2113B-1 AAT2113BIXS-1 GRM188R60J475KE19D
Text: PRODUCT DATASHEET AAT2113B SwitchRegTM 3.3MHz , Fast Transient 1.5A Step-Down Converter in , . The 3.3MHz switching frequency enables the use of small external components. The ultra-small 2mm x , : 1.0V to 2.5V High Efficiency, Low Noise Architecture 3.3MHz Switching Frequency No External , ) 2113B.2010.03.1.0 www.analogictech.com 1 PRODUCT DATASHEET AAT2113B SwitchRegTM 3.3MHz , Fast , DATASHEET AAT2113B SwitchRegTM 3.3MHz , Fast Transient 1.5A Step-Down Converter in 2mm x 2mm Package


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PDF AAT2113B AAT2113B 2113B LQM2HPNR47MG0 murata mlc 0201 GRM155R60J105KE19D AAT2113B-1 AAT2113BIXS-1 GRM188R60J475KE19D
TTL 7475

Abstract: No abstract text available
Text: max. Jitter 20µA max. ± 250ps max. for F<= 33MHz , ±100ps typ. ± 100ps max. for F> 33MHz , ±50ps typ. Peak to peak ± 250ps max. for F<= 33MHz , ±100ps typ. ± 125ps max. for F> 33MHz , ±75ps typ. ± 50ps max. for F<= 33MHz , ±30ps typ. ± 30ps max. for F> 33MHz , ±20ps typ. ± 50ps max. for F<= 33MHz , ±30ps typ. ± 30ps max. for F> 33MHz , ±20ps typ. RMS One sigma PATTERN VIH: 0.7*VDDmin


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PDF Vol01 50ppm TTL 7475
t523

Abstract: t536 Elite Microelectronics T524 t518 T505 t610 t314 T-535 T308
Text: 33MHZ SYMBOL MIN MAX MIN MAX UNIT 411CLK period T101 40 30 ns 411CLK high at 3.7V T102 5 4 ns , . preliminary This Material Copyrighted By Its Respective Manufacturer 75 4.4.2 Reset Timing 25MHZ 33MHZ , Respective Manufacturer 4.4.3 AT Bus Cycle Timing SYMBOL 25MHZ MIN MAX 33MHZ MIN MAX UNIT BALE active , Copyrighted By Its Respective Manufacturer AT Bus Cycle Timing (Cont.) 25MHZ 33MHZ SYMBOL MIN MAX MIN MAX , Manufacturer 4.4.3 AT Bus Cycle Timing SYMBOL 25MHZ MIN MAX 33MHZ MIN MAX UNIT HOLD valid from 411CLK


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PDF e88C411 e88C411 25MHZ 33MHZ 411CLK 33MHZ 411CLK t523 t536 Elite Microelectronics T524 t518 T505 t610 t314 T-535 T308
1997 - intel 7883

Abstract: 80960SA 80960KB 80960KA 80960JF 80960JD 80960JA 80960HD 80960HA 80960CF
Text: 10.51 10 6.89 6.86 5 0 SA/SB 20Mhz Benchmark Report KA/KB 25Mhz CA 33Mhz CF 33Mhz CF 40Mhz 7 i960® Microprocessor GHOSTSCRIPT Postscript Interpreter (cont , PERFORMANCE 8 7.81 7 6 5 4.05 4 3.55 3.1 3 2 1 0 JA 33Mhz 8 JF 33Mhz JD 25 , Benchmark Report KA/KB 25Mhz CA 33Mhz CF 33Mhz CF 40Mhz 9 i960® Microprocessor NET , 33Mhz 10 JF 33Mhz JD 25/50Mhz HA 40Mhz Benchmark Report i960® Microprocessor


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PDF 20Mhz 25Mhz 33Mhz 40Mhz 25/50Mhz 20/60Mhz intel 7883 80960SA 80960KB 80960KA 80960JF 80960JD 80960JA 80960HD 80960HA 80960CF
Not Available

Abstract: No abstract text available
Text: copies of 66/100/133MHz CPU Clocks (2.5V) 7 copies of PCI Clock ( 33MHz ) (3.3V) 7 copies of DRAM Clocks (1 Free Running DCLK) (100/133MHz, 3.3V) 2 copies of APIC Clock @ 33MHz , (2.5V) 1 copy of 48MHz USB , PCI Hi- Z TCLK/6 33MHz 33MHz 33MHz 33MHz 48M Hz Hi- Z TCLK/2 48MHz 48MHz 48MHz 48MHz REF Hi- Z TCLK 14.318MHz 14.318MHz 14.318MHz 14.318MHz APIC Hi- Z TCLK/6 33MHz 33MHz 33MHz 33MHz Note s 1 2,3 4,5,6 4,5,6 4 , 10ns 20ns 30ns 40ns Cycle Repeat CPU 66MHz SDRAM 100MHz 3.3V 66MHz PCI 33MHz APIC 33MHz REF


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PDF PI6C115M 66/100/133MHz 33MHz) 100/133MHz, 33MHz, 48MHz 56-Pin PI6C115-
2007 - CRYSTAL 14.318MHZ

Abstract: Silego Technology
Text: Geode based systems · 3 - selectable 66MHz or 33MHz PCI clock outputs · Three selectable 66MHz or 33MHz PCI clock outputs · 2 - 33MHz LPC clock outputs · Two 33MHz clock outputs for LPC interface , S0 6 LCLK1_33M O, SE 33MHz LCLK output. 7 VSS GND Ground for outputs. 8 VDD PWR 3.3V power supply for outputs. 9 LCLK2_33M O, SE 33MHz LCLK output. 10 , 33MHz or 66MHz PCI clock output. 19 VDD PWR 3.3V power supply for outputs. 20 PCICLK1


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PDF SLG62102 66MHz 33MHz 24MHz 318MHz CRYSTAL 14.318MHZ Silego Technology
1997 - STP2003QFP

Abstract: Sun Ultra 5 EDO FLASH DIMMs 72 pin CONNECTOR HEADER 20 PIN MAIL "ISP" server SIMM 72 simm72 Sun Ultra AX M48T59 DB25S
Text: 32 bit 5V 33MHz 512K E-Cache PCI Open Boot PROM UltraSPARC Data Buffer Ultra PORT Architecture (UPA) core 64 bit EPCI 5V / 3.3V 33MHz / 66MHz PCI to EIDE Controller (ATA , Configurations 32bit 64bit Frequency Performance SEUAX 2 2 33MHz (32bit) 132MB/sec , ORDERING INFORMATION Part Number CPU PCI Bus Description SEUAX-1167-0 167MHz 33MHz SEUAX-12501-0 250MHz 33MHz SEUAXE-12501-0 250MHz 33/66MHz SEKIT-AX167-SIS10-M


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PDF SEUAX-1167-0 167MHz 33MHz SEUAX-12501-0 250MHz SEUAXE-12501-0 33/66MHz SEKIT-AX167-SIS10-M STP2003QFP Sun Ultra 5 EDO FLASH DIMMs 72 pin CONNECTOR HEADER 20 PIN MAIL "ISP" server SIMM 72 simm72 Sun Ultra AX M48T59 DB25S
Not Available

Abstract: No abstract text available
Text: Output, 33MHz LVCMOS The PI6C557-10 is an integrated 100MHz differential and 33MHz LVCMOS clock , provided for analog core, 100MHz differential output, and 33MHz LVCMOS output to adhere to lowest risk , VDD33 Power Output Power Ground for 33MHz output. 33.3MHz LVCMOS output. Power for 33MHz , 100MHz and 33MHz outputs when HIGH. Internal pull-down is 30Kohm. 1 Description Analog Ground , PCIE Gen 1 (pk-pk) Phase Jitter 33MHz LVCMOS DC Characteristics (VDD = 3.3V ± 5%, TA = -40°C to


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PDF PI6C557-10 100MHz 33MHz PI6C557-10 33MHz 25MHz 100MHz
t523

Abstract: T536 t802 T311 .T536 S M T209 t519 XA0-XA16 t609 T319
Text: MIN MAX 33MHZ MIN MAX SYMBOL UNIT 411CLK period 411CLK high at 3.7V 411CLK low at 0.8V 411CLK , .4 .2 Reset Timing 25MHZ MIN MAX 33MHZ MIN MAX SYMBOL UNIT RESET1- setup time to 411CLK , PRELIMINARY Elite Microelectronics, Inc. 4.4 .3 AT Bus Cycle Timing 25MHZ MIN MAX 33MHZ MIN MAX , . preliminary 77 AT Bus Cycle Timing (Cont.) 25MHZ MIN MAX 33MHZ MIN MAX SYMBOL UNIT IOCHRDY , PRELIMINARY Elite Microelectronics, Inc. 4 .4 .4 DMA Cycle Timing 25MHZ MIN MAX 33MHZ MIN MAX


OCR Scan
PDF e88C411 25MHZ 33MHZ 411CLK t523 T536 t802 T311 .T536 S M T209 t519 XA0-XA16 t609 T319
2008 - SRX7278

Abstract: No abstract text available
Text: PI6C557-10 Network Clock Generator Product Features · 100MHz Differential Output, 33MHz LVCMOS · , pins are provided for analog core, 100MHz differential output, and 33MHz LVCMOS output to adhere to , integrated 100MHz differential and 33MHz LVCMOS clock generator. It uses a 25MHz quartz crystal to provide an , . Crystal output. Crystal power ground. Ground. Power. Ground for 33MHz output. 33.3MHz LVCMOS output. Power for 33MHz output Power. Complimentary 100MHz differential output. 100MHz differential output. Ground


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PDF PI6C557-10 100MHz 33MHz 25MHz 100MHz --16-pin, PI6C557-10 SRX7278
STP2003QFP

Abstract: Sun Ultra AX Sun Ultra 5 CONNECTOR HEADER 20 PIN MAIL pci connector 124 pin "ISP" server SEUAX-1167-0 462 motherboard
Text: 5V/3.3V 33MHz /66MHz 144 512K E-Cache 32 bit /I PCI 5V 33MHz / UltraSPARC Data Buffer , 64bit 2 1 ECache 512Kb 1MB Frequency 33MHz 66MHz Performance (32bit) 132MB/sec (32bit) 132MB/sce (64 , -12501-0 SEKIT-AX167-SIS10-M SEKIT-AX167-UIS10-M SEKIT-AX167-SEC10-M 167MHz 250MHz 250MHz 167MHz 167MHz 167MHz 33MHz 33MHz 33/66MHZ 33MHz 33MHz 33MHz SPARCengine Uftra AX PCI Bus Board SPARCenglne Ultra AX PCI Bus Board


OCR Scan
PDF SEUAX-1167-0 SEUAX-12501-0 SEUAXE-12501-0 SEKIT-AX167-SIS10-M SEKIT-AX167-UIS10-M SEKIT-AX167-SEC10-M 167MHz 250MHz STP2003QFP Sun Ultra AX Sun Ultra 5 CONNECTOR HEADER 20 PIN MAIL pci connector 124 pin "ISP" server 462 motherboard
2009 - 100mhz crystal decoupling

Abstract: SRX7278 PI6C557-10 clock generator differential output GND33 tdc marking code
Text: Output, 33MHz LVCMOS The PI6C557-10 is an integrated 100MHz differential and 33MHz LVCMOS clock , provided for analog core, 100MHz differential output, and 33MHz LVCMOS output to adhere to lowest risk , VDD33 Power Output Power Ground for 33MHz output. 33.3MHz LVCMOS output. Power for 33MHz , 100MHz and 33MHz outputs when HIGH. Internal pull-down is 30Kohm. 1 Description Analog Ground , 33MHz LVCMOS DC Characteristics (VDD = 3.3V ± 5%, TA = -40°C to +85°C) t 3.465V unless otherwise stated


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PDF PI6C557-10 100MHz 33MHz PI6C557-10 33MHz 25MHz 100MHz 100mhz crystal decoupling SRX7278 clock generator differential output GND33 tdc marking code
intel 775 motherboard diagram

Abstract: pin diagram of intel p4 processor ICS9LP505-2 lga775 96MP2DD-24FA-4M7T prescott 800 dual core cpu Socket 775 PIN diagram 96D2-1G667NN-TR Intel Pentium 4 Socket 775 PIN diagram W83627DHG-a
Text: + Source code 4.0 GB/s per direction, 1 slot 1 GB/s per direction, 1 slot 32-bit/ 33MHz , 1 slots Dual , 33MHz 14.318 MHz ADDR ADDR DATA CNTL CNTL HOST BUS DATA Main Clock ICS9LP505-2 INTEGRATED VGA , SATA BUS AZALIA LINK 24MHz INTEL ICH8 5 PCIEX1 Port 32.768KHz 48MHz 33MHz 14.318MHz INTEL , II -5 PCIEx by 1 interface 31 X 31 mm 652 mBGA PCI IDE ITE8212F PCI SLOT 1 33MHz 33MHz 33MHz 33MHz 33MHz 33MHz PCIEx1 port1-4 SST BUS 100MHz 14.318MHz 33MHz 32.768KHz PCI BUS REQ1


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PDF DVMB-764 RS-485 2000/XP 2002/95/EC DVMB-764 DDR2-667 96D2-2G667FB-TR 96D2-1G667NN-TR intel 775 motherboard diagram pin diagram of intel p4 processor ICS9LP505-2 lga775 96MP2DD-24FA-4M7T prescott 800 dual core cpu Socket 775 PIN diagram Intel Pentium 4 Socket 775 PIN diagram W83627DHG-a
2001 - Not Available

Abstract: No abstract text available
Text: low skew to handle data transfers in excess of 133 MHz. • 7 copies of PCI Clock ( 33MHz ) (3.3V) • 7 copies of DRAM Clocks (1 Free Running DCLK) (100/133MHz, 3.3V) • 2 copies of APIC Clock @ 33MHz , TCLK/2 TCLK TCLK/6 2,3 1 0 0 66MHz 100MHz 66MHz 33MHz 48MHz 14.318MHz 33MHz 4,5,6 1 0 1 100MHz 100MHz 66MHz 33MHz 48MHz 14.318MHz 33MHz 4,5,6 1 1 0 133MHz 133MHz 66MHz 33MHz 48MHz 14.318MHz 33MHz 4


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PDF PI6C115M 66/100/133MHz PI6C115M 56-Pin PI6C115-
2005 - PM25LV040

Abstract: PM25LV020 SO8w footprint MX25L8005M2C-15G MX25L8005M2C MLP8 FOOTPRINT ICE25P05 SST25VF016-33-4C-QA M25PE10-VMP6TG Y25f05
Text: compatible at 33MHz , different read ID, bottom sector optionally split into four 1KB-sectors Footprint compatible but care to central pad, download and update compatible at 33MHz , different read ID, bottom , 33MHz , different read ID, bottom sector optionally split into four 1KB-sectors Footprint compatible but care to central pad, download and update compatible at 33MHz , different read ID, bottom sector optionally split into four 1KB-sectors Footprint compatible, download and update compatible at 33MHz


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PDF CRSERFLASH0705 PM25LV040 PM25LV020 SO8w footprint MX25L8005M2C-15G MX25L8005M2C MLP8 FOOTPRINT ICE25P05 SST25VF016-33-4C-QA M25PE10-VMP6TG Y25f05
ARM10TDMI block diagram

Abstract: KS32C50100 ARM7 set associative fast sram 200mhz 8k KS* I2C UART buffer ic ARM920T 1997 196QFP 64k FIFO DRAM 196-QFP
Text: speed USB · E/S : 2Q. 99 · Little/Big Endian · E/S: Jan. 1999 KS32C5000 ( 33MHz ) · S-ARM7T · , /Big Endian support -> UART Buffer improve -> HDLC/MAC Bug Fix · E/S : Jan. 99 KS32C5000A ( 33MHz , ( 33MHz ) Network Team MAC (10/100M) 2-ch HDLC (with DMA) I&D Cache 2-ch UART SRAM 2 , Ethernet Backbone Network Team TransTransformer former RIC RIC CPU Bus S-ARM7T ( 33MHz , Diagram(Ethernet Switch) KS32C5000A CPU Bus S-ARM7T ( 33MHz ) MAC (10/100M) Switched


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PDF KS32C5000A 32-bit 200MHz S-ARM920T S-ARM1020T 300MHz ARM10TDMI 40MHz ARM10TDMI block diagram KS32C50100 ARM7 set associative fast sram 200mhz 8k KS* I2C UART buffer ic ARM920T 1997 196QFP 64k FIFO DRAM 196-QFP
2003 - Not Available

Abstract: No abstract text available
Text: Vtt_Pwrgd# assertion = CPU Input / Output 8 33MHz clock output / CPU2 select when HIGH PCIF[1:2 , # / PWRDWN 33MHz clocks outputs (free running) 33MHz clocks outputs 48MHz clock output 96MHz , SRC PCIF / PCI REF DOT_96 USB_48 Note 1 0 1 100MHz 100MHz 33MHz 14.318MHz 96MHz 48MHz 1 0 0 1 133MHz 100MHz 33MHz 14.318MHz 96MHz 48MHz 1 0 1 1 166MHz 100MHz 33MHz 14.318MHz 96MHz 48MHz 1 0 1 0


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PDF PI6C410M PI6C410M 400MHz 350ps 48MHz 250ps PI6C410MA 56-Pin, 240mil
1997 - PPC401GF

Abstract: V962PBC-33 V962PBC V961PBC-40 V961PBC-33 V961PBC V960PBC-33 V960PBC V292PBC V962PBC-40
Text: · 2 channel DMA controller · 33MHz and 40MHz local bus versions available with independent PCI operation up to 33MHz · Both target and master (primary or secondary) modes supported on the PCI and local , -33 REV B2 i960Cx/Hx 32-bit demultiplexed 160-pin EIAJ PQFP 33MHz V962PBC-40 REV B2 i960Cx , 32-bit multiplexed 160-pin EIAJ PQFP 33MHz V961PBC-40 REV B2 i960JA/JD/JF PPC401GF 32 , -pin EIAJ PQFP 33MHz V292PBC-33 REV B2 Am29030/35/40 32-bit demultiplexed 160-pin EIAJ PQFP 33MHz


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PDF 576-byte 33MHz 40MHz 33MHz V960PBC V961PBC 2348G PPC401GF V962PBC-33 V962PBC V961PBC-40 V961PBC-33 V960PBC-33 V292PBC V962PBC-40
2010 - MX25L6406E

Abstract: MX25L6445E MX25L6445 mxic mx25l6406e MX25L6405D data mx25L6406E MX25L6406 MX25L6445* input id mxic mx25l6445e MX25L644
Text: ~86MHz Read 10KHz~ 33MHz 50MHz DC~ 33MHz - - DC~80MHz 2 READ(x2 I/O) 10KHz , tCH 86MHz: 5.5ns 33MHz : 13ns 104MHz: 4.5ns 50MHz: 9ns 86MHz: 5.5ns 33MHz : 13ns tCL 86MHz: 5.5ns 33MHz : 13ns 104MHz: 4.5ns 50MHz: 9ns 86MHz: 5.5ns 33MHz : 13ns Byte 9us(typ , .) 20uA(max.) ICC1 25mA(max.) @86MHz 20mA(max.) @66MHz 10mA(max.) @ 33MHz 19mA(max.) @104MHz 15mA(max.) @66MHz 10mA(max.) @ 33MHz 25mA(max.) @86MHz 20mA(max.) @66MHz 10mA(max.) @ 33MHz ICC2


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PDF MX25L6406E MX25L6405D MX25L6445E AN-069 MX25L6406E MX25L6405D MX25L6445E. MX25L6445E MX25L6445 mxic mx25l6406e data mx25L6406E MX25L6406 MX25L6445* input id mxic mx25l6445e MX25L644
2003 - fsb -016

Abstract: No abstract text available
Text: output ITP_EN = 0 @ Vtt_Pwrgd# assertion = SRC ITP_EN = 1 @ Vtt_Pwrgd# assertion = CPU 33MHz clock output / CPU2 select when HIGH 33MHz clocks outputs (free running) 33MHz clocks outputs 48MHz clock output 96MHz , 33MHz 33MHz 33MHz 33MHz 33MHz 33MHz 33MHz 33MHz REF 14.318MHz 14.318MHz 14.318MHz 14.318MHz 14.318MHz , Float CPU# Normal Float SRC Normal Iref × 2 or Float SRC# Normal Float PCIF / PCI 33MHz Low REF , , 33MHz Figure 1, Power down sequence 8 PS8734 05/19/04 PI6C410 Clock Generator for Intel


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PDF PI6C410 400MHz -56-Pin PI6C410 350ps 48MHz 500ps 125ps PS8734 fsb -016
Supplyframe Tracking Pixel