The Datasheet Archive

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Part Manufacturer Description Datasheet Download Buy Part
PR212 Texas Instruments Power Management Solution for Spartan(TM)-IIE (Design 3)
PR208 Texas Instruments Power Management Solution for Spartan(TM)-IIE (Design 1)
PR210 Texas Instruments Power Management Solution for Spartan(TM)-IIE (Design 2)

UltraSPARC IIe Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
UltraSPARC IIIi

Abstract: UltraSPARC iie ultrasparc AF5A
Text: ) External ` Cache RAM Memory Interface Unit (MIU) UltraSPARC - I Bu £ Figure 1. F unctional Block , this bus. (3.3V, UPA)"1 Bidirectional radial UltraSPARC -1 Bus signal betw een UltraSPARC -1 and the system. Driven by UltraSPARC -1 to initiate SYSADR transactions to the system. Driven by the sys tem to initiate Coherency, Interrupt or Slave transactions to UltraSPARC -1. Synchronous to the system clock. (3.3 V, UPA) UltraSPARC -1 system address bus arbitration request from up to 3 other UltraSPARC -1 bus


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PDF 64-bit STP1030A P1030A STP1030A UltraSPARC IIIi UltraSPARC iie ultrasparc AF5A
UltraSparc T1

Abstract: No abstract text available
Text: STP1030A S un M ic r o e l e c t r o n ic s July 1997 UltraSPARC "-! DATA SHEET , , UltraSPARC -1, is a high-perform ance, highly-integrated superscalar processor implementing the SPARC V9 64 , - Operates at 3.3V - 521 Pin Plastic Ball Grid Array (BGA) • Power Management 1 UltraSPARC , . Functional Block Diagram S un M icroelectronics July 1997 UltraSPARC "! First Generation SPARC v9 , , UltraSPARC -1 integrates the follow ing com ponents (see Figure 1): • Prefetch, branch prediction and


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PDF STP1030A 64-Bit STP1030A, STP1030A 256-Pin STP1030ABGA-167 UltraSparc T1
STP1030

Abstract: UltraSPARC ii AF5A Sun UltraSparc T1 Sun UltraSparc T2
Text: ^ Business SPA R C Technology M ay 1995 UltraSPARC -1 DATA SHEET In t r o d u c t io n , o n e n t O v e r v i e w In a single chip implementation, the UltraSPARC -1 processor integrates , units in the FPU allows UltraSPARC -1 to issue and execute two float ing-point instructions per cycle , latency operations. Graphics Unit (GRU) UltraSPARC -1 introduces a comprehensive set of graphics , Reference - System Interface Symbol SYSADR[35:0] Type Nam e and Function B idirectional UltraSPARC -1 B us


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PDF STP1030, 64-bit STP1030 UltraSPARC ii AF5A Sun UltraSparc T1 Sun UltraSparc T2
polaris

Abstract: No abstract text available
Text: : • SPARC Æ options: UltraSPARC ™ IIe , IIi • PowerPC Æ options: MCP750, MCP765 • Intel options


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Z2 150 1AK

Abstract: Sun UltraSparc T2 UltraSPARC ii AJ17A
Text: Introduction High-Performance 64 Bit RISC Processor The STP1030, UltraSPARC -!, is a high-performance , ) UltraSPARC -! Bus F ig u r e 1. F u n c tio n a l B lo ck D iagram U l t r a S P A R C -I C o m p o n e n t O v e r v i e w In a single chip implementation, the UltraSPARC -! processor integrates the , 64-entry dTLB for data, both fully asso ciative. UltraSPARC -! provides hardware support for a , o f the execution units in the FPU allows UltraSPARC -! to issue and execute two float ing-point


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PDF STP1030, 64-bit STP1030 Z2 150 1AK Sun UltraSparc T2 UltraSPARC ii AJ17A
1998 - 6803 microprocessor

Abstract: Sun UltraSparc ultrasparc 3 SUN MICROELECTRONICS register file UltraSPARC ii memory bandwidth
Text: UltraSPARC II Microprocessor TM High-Performance, Highly-Scalable, Multiprocessing, 64-bit SPARCTM V9 RISC Microprocessor Placeholder for illustration or photo The UltraSPARC II processor , special-purpose media processor. And the UltraSPARC II delivers superior raw compute performance by using the , UltraSPARC II processor not only helps the system designer by implementing industry-standard testing and , reliability. With high performance, high scalability, and high reliability, the UltraSPARC II is the


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PDF 64-bit 64-way PBN-0140-01 6803 microprocessor Sun UltraSparc ultrasparc 3 SUN MICROELECTRONICS register file UltraSPARC ii memory bandwidth
Not Available

Abstract: No abstract text available
Text: STP5110A S un M ic r o e l e c t r o n ic s J u ly 1997 UltraSPARC ™ CPU Module -! , interfaces to the UltraSPARC Port Architecture (UPA) interconnect bus. The m ain com ponents on the m odule are: one UltraSPARC -1 CPU, two UltraSPARC-I UDB data buffer chips, one 32kx36 tag SRAM , four 32kx36 , interface at a 2:1 frequency ratio. The m odule w ill be available w ith the UltraSPARC -1 running at 167 , €¢ High perform ance UltraSPARC -1 CPU module • Delivers approxim ately 7.7 SPEC int95, 11.4 SPEC


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PDF STP5110A 32kx36 32kx36 MC100LVE111 5110AUPA-167 STP1030A)
STP1080

Abstract: ultrasparc 3
Text: device used in UltraSPARC -1 system s to connect the CPU and its external SRAM cache bus to the system bus , the STP1080. Companion Device for 167/200 MHz UltraSPARC -1 Systems Features · Isolates the , 191 UltraSPARC '"-! Data Buffer (UDB-I) Companion Device for 167/200 MHz UltraSPARC -1 Systems , delivery rates of the E-Cache and Interconnect. UltraSPARC -1 has a second-level cache of at least 512KB , Buffer (UDB-I) Companion Device for 167/200 MHz UltraSPARC -1 Systems T e c h n ic a l O v e r v ie w


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PDF STP1080BGA STP1080. STP1080ABGA-83 STP1080ABGA-100 STP1080 ultrasparc 3
Not Available

Abstract: No abstract text available
Text: STP5111A S un M ic r o e l e c t r o n ic s J u ly 1997 UltraSPARC ™ CPU Module -! DATA SHEET 200 MHz UltraSPARC -1 + 1 MB E-Cache + UDBs D e s c r ip t io n The UltraSPARC-I m , interfaces to the UltraSPARC Port Architecture (UPA) interconnect bus. The m ain com ponents on the m odule are: one UltraSPARC -1 CPU, two UltraSPARC-I UDB data buffer chips, one 32kx36 tag SRAM , eight 64 k x , interface at a 2:1 frequency ratio. The m odule w ill be available w ith the UltraSPARC -1 running at 200


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PDF STP5111A 32kx36 MC10ELV111 PA-200 STP1030A)
SRAM

Abstract: ultrasparc
Text: S un M icro electro nics July 1997 UltraSPARC "-! CPU Module DATA SHEET D e s c r ip t io n The UltraSPARC -1 module is a high performance, SPARC V9 compliant, small form factor processor module, which interfaces to the UltraSPARC Port Architecture (UPA) interconnect bus. The main components on the module are: one UltraSPARC -1 CPU, two UltraSPARC -1 UDB data buffer chips, one 32kx36 tag SRAM , . The interface to the module is through a high-speed edge connector. 167 MHz UltraSPARC -1 + 0.5 MB


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PDF 32kx36 32kx36 MC100LVE111 STP5110AUPA-167 STP1030A) STP5110A SRAM ultrasparc
GIGABYTE G31

Abstract: SPARC v9 architecture BLOCK DIAGRAM gigabyte p31 187U UltraSPARC ii TP1030A
Text: , UltraSPARC -1, is a high-performance, highly-integrated superscalar processor implementing the SPARC V9 64 , Power Management 157 UltraSPARC "-1 First Generation SPARC v9 64-Bit Microprocessor With VIS , Figure 1. Functional Block Diagram 158 S un M icroelectronics ]u ly l9 9 7 UltraSPARC , chip implementation, UltraSPARC -1 integrates the following components (see Figure 1): · Prefetch , for instructions and a 64-entry dTLB for data, both fully associative. UltraSPARC -1 provides hardw are


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PDF 64-Bit STP1030A, STP1030A 256-Pin STP1030ABGA-167 STP1030ABGA-200 GIGABYTE G31 SPARC v9 architecture BLOCK DIAGRAM gigabyte p31 187U UltraSPARC ii TP1030A
STP5111

Abstract: No abstract text available
Text: e s c r ip t io n The UltraSPARC -1 module is a high performance, SPARC V9 compliant, small form factor processor module, which interfaces to the UltraSPARC Port Architecture (UPA) interconnect bus. The , with the system interface at a 2:1 frequency ratio. The module will be available with the UltraSPARC , UltraSPARC -1 + 1 MB E-Cache + UDBs Features · High performance UltraSPARC -1 CPU module · Programmable bus , scalable systems to be built · UltraSPARC 's pipelined E-Cache interface delivers high performance · Allows


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PDF 32kx36 64kxl8 MC10ELV111 5111AUPA-200 STP1030A) STP5111
UltraSPARC ii

Abstract: No abstract text available
Text: STP5110A S un M ic r o e le c t r o n ic s July 1997 UltraSPARC TM -l CPU Module , , small form factor processor m odule, which interfaces to the UltraSPARC Port Architecture (UPA) interconnect bus. The m ain com ponents on the m odule are: one UltraSPARC-I CPU, two UltraSPARC -1 UDB data , available with the UltraSPARC -1 running at 167 MHz. The interface to the m odule is through a high-speed edge connector. 167 MHz UltraSPARC -1 + 0.5 MB E-Cache + UDBs Features High performance


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PDF STP5110A 32kx36 32kx36 MC100LVE111 STP511 STP51 OAUPA-167 STP1030A) UltraSPARC ii
Sun UltraSparc T1

Abstract: UltraSPARC ii STP1031 ultrasparc g31 m7 te
Text: in the same group. UltraSPARC-II is part of a second generation of UltraSPARC pipeline-based products , developers. At the same time, it provides software compatibility with existing UltraSPARC -1 based systems , (BGA) · Power Managem ent · Multiple Clocking Modes - UltraSPARC ! C om patible · Multiple Outstanding , single chip implementation, UltraSPARC - II integrates the following components (see Figure D , -entry iTLB for instructions and a 64-entry dTLB for data, both fully associative. UltraSPARC - II provides


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PDF 64-Bit STP1031 STP1031, STP1031 Sun UltraSparc T1 UltraSPARC ii ultrasparc g31 m7 te
2008 - Sun UltraSparc t2

Abstract: Sun UltraSparc ultrasparc 3 UltraSPARC T2 Processor with Wind River wind river sunwin Sun UltraSparc T2 plus snort
Text: UltraSPARC ® T2 Processor with Wind River Platform for Network Equipment, Linux Edition The future , latency · Wind River Platform for Network Equipment, Linux Edition, running on the UltraSPARC ® T2 , UltraSPARC T2 processor is a true "system on a chip" > Today's network infrastructure must deliver far , networking processors (NPUs), for networking functions. Now, with the UltraSPARC T2 CMT processor, plus Wind , Development Suite on the UltraSPARC T2 processor means systems designers can continue to use the same


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PDF 1-800-555-9SUN Sun UltraSparc t2 Sun UltraSparc ultrasparc 3 UltraSPARC T2 Processor with Wind River wind river sunwin Sun UltraSparc T2 plus snort
STP51

Abstract: No abstract text available
Text: S T P 5111A S un M ic r o e le c t r o n ic s July 1997 UltraSPARC TM -l CPU Module , , small form factor processor m odule, which interfaces to the UltraSPARC Port Architecture (UPA) interconnect bus. The m ain com ponents on the m odule are: one UltraSPARC-I CPU, two UltraSPARC -1 UDB data , available with the UltraSPARC -1 running at 200 MHz. The interface to the m odule is through a high-speed edge connector. 200 MHz UltraSPARC -1 + 1 MB E-Cache + UDBs Features High performance UltraSPARC


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PDF 32kx36 MC10ELV111 STP5111AU PA-200 STP1030A) STP51
1997 - STP2003QFP

Abstract: Sun Ultra 5 EDO FLASH DIMMs 72 pin CONNECTOR HEADER 20 PIN MAIL "ISP" server SIMM 72 simm72 Sun Ultra AX M48T59 DB25S
Text: DESCRIPTION The Ultra AX Net Engine combines the Sun UltraSPARC microprocessor, network software and PC , AX Net Engine is an UltraSPARC powered PCI motherboard that can be installed in a PC standard ATX , UltraSPARC I and II microprocessor modules. - Optional modules support a broad range of networked options , July 1997 SPARCengineTMUltraTMAX Ultra AX Net Engine SEUAX SEUAXE BLOCK DIAGRAM UltraSPARC PCIbus 2.1 Processor Module 167MHz or 250MHz UltraSPARC 144 Standard I/O Expansion 36


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PDF SEUAX-1167-0 167MHz 33MHz SEUAX-12501-0 250MHz SEUAXE-12501-0 33/66MHz SEKIT-AX167-SIS10-M STP2003QFP Sun Ultra 5 EDO FLASH DIMMs 72 pin CONNECTOR HEADER 20 PIN MAIL "ISP" server SIMM 72 simm72 Sun Ultra AX M48T59 DB25S
Sun UltraSparc T2

Abstract: Sun UltraSparc T1 STP1080 sparc v8 spitfire Sun UltraSparc II
Text: Prel i m i na r y SPA RC T echrdogy Business STP1080 May 1995 UltraSPARC -1 Data Buffer (U DB) DATA SHEET Introduction The UltraSPARC ^ Data Buffer(UDB) consists of two chips that connect UltraSPARC -! and its E-eache to a 144bit data bus. Data Buffer chips move data between the E-eache and , · · · · · Isolates the processor from the system bus Interface to the UltraSPARC -1 Bus Operates at , Interconnect. UltraSPARC -! has a second-level cache of at least 512KB. The second-level cache is physically


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PDF STP1080 144bit 16paritybils. STP1080 44ayer Sun UltraSparc T2 Sun UltraSparc T1 sparc v8 spitfire Sun UltraSparc II
1998 - Sun UltraSparc T1

Abstract: ULTRASPARC-III UPA64 ultrasparc 3 ULTRASPARC Sun UltraSparc UltraSparc IIi
Text: Solution The UltraSPARC i-Series family consists of processors at 270, 300, and 333MHz and modules at , system performance and features the award-winning UltraSPARC processor in a single-chip system solution. The UltraSPARC IIi processor incorporates a CPU, PCI bus interface, and memory controller to deliver , communication systems and advanced imaging technology. Optimizing Overall System Performance The UltraSPARC , the UltraSPARC IIi, while using PC-class, PCI-based mother boards and components. In addition, Sun


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PDF 64-bit 333MHz 270MHz/256Kb, 300MHz/512Kb, 333MHz/2MB. PBN-0014-03 Sun UltraSparc T1 ULTRASPARC-III UPA64 ultrasparc 3 ULTRASPARC Sun UltraSparc UltraSparc IIi
ultrasparc

Abstract: No abstract text available
Text: UltraSPARC " -!! Data Buffer (UDB-II) DATA SHEET D e s c r ip t io n The UltraSPARC-II Data , . UDB-II Block Diagram July 1997 S un M icroelectronics 253 UltraSPARC "-11 Data Buffer , from the UltraSPARC-II to the UPA, while the other holds data going from the UPA to the UltraSPARC , UltraSPARC "-!! Data Buffer (UDB-II) Companion Device for 250/300 MHz UltraSPARC -!! Systems Error , UltraSPARC'-IJ Data Buffer (UDB-JI) Companion Device for 250/300 MHz UltraSPARC -11 Systems TABLE 1: ECC Status


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PDF 1V11V UltraSPARC-11 STP1081ABGA-125 STP1081ABGA-150 ultrasparc
STP2003QFP

Abstract: Sun Ultra AX Sun Ultra 5 CONNECTOR HEADER 20 PIN MAIL pci connector 124 pin "ISP" server SEUAX-1167-0 462 motherboard
Text: The Ultra AX Net Engine combines the Sun UltraSPARC microprocessor, network software and PC hardware , is an UltraSPARC powered PCI motherboard that can be installed in a PC standard ATX chassis and , Benefits · UltraSPARC I and II microprocessor modules. - Optional modules support a broad range of , nics july 1997 SPARCengineTMUltraTMAX Ultra AX Net Engine B l o c k D ia g r a m UltraSPARC Processor Module 167MHz or 250MHz PCIbus 2.1 Standard I/O Expansion UltraSPARC 36 64 bit EPCI


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PDF SEUAX-1167-0 SEUAX-12501-0 SEUAXE-12501-0 SEKIT-AX167-SIS10-M SEKIT-AX167-UIS10-M SEKIT-AX167-SEC10-M 167MHz 250MHz STP2003QFP Sun Ultra AX Sun Ultra 5 CONNECTOR HEADER 20 PIN MAIL pci connector 124 pin "ISP" server 462 motherboard
1999 - ULTRASPARC-III

Abstract: Sun UltraSparc itanium merced "rainbow technologies" 21264 PowerPC 7400 ultrasparc 3 rainbow technologies 1999 MPC7400
Text: UltraSPARC III processor. examples of security technologies that RSA Decryption Kernel Measurements , Processor Sun UltraSPARC * III Clock Frequency 660 MHz 600 MHz RSA Decryptions Per Second 1,000 , data for the Sun UltraSPARC * III processor. Figure 2. Relative component costs for SSL transactions , , number Processor Intel® ItaniumTM Processor Sun UltraSPARC * III Clock Frequency 660 MHz 600 , instruction execution in the Itanium processor. The processors (Ref. 7) · Sun UltraSPARC * III processor


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2000 - Contivity Extranet Switch 4500

Abstract: AH3214015-1 "L2TP" "PPTP"
Text: None Intel/Pentium 300 MHz and greater Solaris 2.7 (Solaris 7) None SPARC/ UltraSPARC Solaris 2.5.1, 2.6, 2.7 (Solaris 7) None SPARC/ UltraSPARC Solaris 2.5.1, 2.6, 2.7 (Solaris 7) HP OpenView 4.1.x, 5.0.x, 6.x SPARC/ UltraSPARC Solaris 2.5.1, 2.6, 2.7 (Solaris 7) Sun , 5.2* None SPARC/ UltraSPARC Red Hat Linux 5.2* None *Not officially supported


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PSA B20 0110

Abstract: Sun UltraSparc T1 UltraSPARC ii ultrasparc
Text: . Clocks, Reset, etc. Observability. JTAG, etc. Figure 3. Main UltraSPARC -41 Interfaces Cache Coherence , 219 UltraSPARC " -Il Second Generation SPARC v9 64-Bit Microprocessor With VIS · Shared Clean (S , Store hit, atomic hit to Shared Clean line i) A Shared Clean line is victimized by UltraSPARC . I-Cache , other interrupters. July 1997 S un M icroelectronics 223 UltraSPARC ""-11 Second , d eliver a 64 byte interrupt packet to the destination (see A S I Registers definition in UltraSPARC


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PDF 64-Bit STP1031, STP1031 STP1031LGA PSA B20 0110 Sun UltraSparc T1 UltraSPARC ii ultrasparc
805-0086-02

Abstract: J0801 UltraSPARC ii Sun UltraSparc II
Text: SME5421MCZ-300 microsystems Ju ly 1998 UltraSPARC TM-ll/CPU Module DATA SHEET D e s c r ip , CPU m odule. It interfaces to the UltraSPARC P ort A rchitecture 64S (UPA64S) interconnect bus, m ain , ] o UPA_ADR_VLD SYS-DAT[63:0] o I/O 10 Sun M icrosystem s, Inc July 1998 UltraSPARC , Distribution 12 Sun M icrosystem s, Inc July 1998 UltraSPARC TM-IIi CPU Module 300 M H z CPU, 0.5 , V ss to V D D 1. To be announced 14 Sun M icrosystem s, Inc July 1998 UltraSPARC


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PDF SME5421MCZ-300 UPA64S) UPA64S E5421M Z-300 UPA64s, 805-0086-02 J0801 UltraSPARC ii Sun UltraSparc II
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