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ULTRASPARC-II datasheet (2)

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UltraSPARC-II Sun Microelectronics UltraSPARC-II CPU Module Original PDF
UltraSPARC-IIi Sun Microelectronics UltraSPARC-IIi CPU Module Original PDF

ULTRASPARC-II Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
Not Available

Abstract: No abstract text available
Text: DATA SHEET Complete 296 MHz CPU, 2.0 MB E-Cache, UDB-II D e s c r ip t io n The UltraSPARC-II m , the UltraSPARC Port Architecture (UPA) interconnect bus. The m odule consists of one UltraSPARC-II microprocessor, two UltraSPARC-II Data Buffer chips, one 32 K x 36 tag SRAM , four 128k K x 36 data SRAM s, and , frequency.The m odule is available w ith the UltraSPARC-II run­ ning at 296M Hz. The interface to the m odule , The STP5211, UltraSPARC-II CPU M odule consists of the follow ing components: • UltraSPARC-II


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PDF STP5212 MC100LVE210 STP5212UPA-300 100MHz STP1031) STP1081)
ultrasparc

Abstract: No abstract text available
Text: UltraSPARC " -!! Data Buffer (UDB-II) DATA SHEET D e s c r ip t io n The UltraSPARC-II Data Buffer (UDB-II) consists of two identical ASICs connecting the UltraSPARC-II micro processor and its , . Companion Device for 250/300 MHz UltraSPARC-II Systems Features · Isolates the processor from the system , /300 MHz UltraSPARC-II Systems UDB-II Interface UDB-II Interlace Figure 1. UDB-II Module Block , delivery rates of the E-Cache and that of the interconnect. UltraSPARC-II has a second-level cache of at


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PDF 1V11V UltraSPARC-11 STP1081ABGA-125 STP1081ABGA-150 ultrasparc
1997 - MCE-100

Abstract: STP1081 STP5211UPA-250 MC100LVE111 MC100LVE210
Text: E-Cache, UDB-II DESCRIPTION The UltraSPARC-II module is a high performance, SPARC V9 compliant, small , . The module consists of one UltraSPARC-II microprocessor, one UltraSPARC-II Data Buffer (consisting of , available with the UltraSPARC-II running at 248 MHz. The interface to the module is through a high-speed standard edge connector. Features Benefits · High performance UltraSPARC-II CPU Module · , multiprocessing · Range of scalable systems can be built · 1.0 Megabyte E-Cache · UltraSPARC-II pipelined


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PDF STP5211 MC100LVE210 STP5211UPA-250 STP1031) STP1081) MCE-100 STP1081 STP5211UPA-250 MC100LVE111
1997 - SPARC v9 architecture BLOCK DIAGRAM

Abstract: UltraSPARC ii sparc sparc v7 STP1031LGA Sinak h30
Text: UltraSPARC-II. Bit 4 of the UltraSPARC-II bus S_REPLY is not used by UltraSPARC-II. Synchronous to system clock , , instructions before and after a conditional branch) can be issued in the same group. UltraSPARC-II is part of , technology, the UltraSPARC-II provides a higher clock frequency, multiple SRAM modes and System-to-Processor , software compatibility with existing UltraSPARC-I based systems. UltraSPARC-II also implements the , clocked at half the UltraSPARC-II frequency. (See Timing Considerations Section on page 21 for more


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PDF STP1031 64-Bit STP1031, STP1031 STP1031LGA SPARC v9 architecture BLOCK DIAGRAM UltraSPARC ii sparc sparc v7 STP1031LGA Sinak h30
1997 - MCE-100

Abstract: ULTRASPARC-II stp1081 BGA 328 Motherboard socket 754 SPARC v9 architecture BLOCK DIAGRAM STP5212UPA-300 MC100LVE210 MC100LVE111 Sun UltraSparc
Text: E-Cache, UDB-II DESCRIPTION The UltraSPARC-II module is a high performance, SPARC V9 compliant, small , . The module consists of one UltraSPARC-II microprocessor, two UltraSPARC-II Data Buffer chips, one 32 K , which yields a 3:1 ratio to the UPA frequency.The module is available with the UltraSPARC-II running at , Benefits · High performance UltraSPARC-II CPU Module · Deliver 12.1 SPECint95 (est.), 15.5 SPECfp95 , · 2.0 Megabyte E-Cache · UltraSPARC-II Pipelined E-Cache Interface delivering high performance


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PDF STP5212 MC100LVE210 STP5212UPA-300 296MHz 100MHz STP1031) STP1081) MCE-100 ULTRASPARC-II stp1081 BGA 328 Motherboard socket 754 SPARC v9 architecture BLOCK DIAGRAM STP5212UPA-300 MC100LVE111 Sun UltraSparc
instruction set Sun SPARC T3

Abstract: Sun UltraSparc T2 "64-Bit Microprocessor" instruction set Sun SPARC T5 UltraSPARC ii SUN MICROELECTRONICS Sun UltraSparc SPARC v9 architecture BLOCK DIAGRAM Sun UltraSparc T1 ULTRASPARC-II integer execution unit
Text: UltraSPARC-II. TABLE 3: UPA Port Interface UPA Port Interface UltraSPARC-II Interface UPA_DataBus[144] <â , UltraSPARC-II. • S_CPB_REQ (Copyback): Copyback request from the system controller to UltraSPARC-II following , UltraSPARC-II. • S_CPD_REQ (Copyback To Discard): Sent at the UltraSPARC-II bus interface to UltraSPARC-II in , Read): The only slave read transaction that should be sent to UltraSPARC-II. UltraSPARC-II responds to , system data bus from UltraSPARC-II. It allows data transfers between UltraSPARC-II and the memory system


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PDF STP1031 64-Bit STP1031, STP1031 787-Pin instruction set Sun SPARC T3 Sun UltraSparc T2 "64-Bit Microprocessor" instruction set Sun SPARC T5 UltraSPARC ii SUN MICROELECTRONICS Sun UltraSparc SPARC v9 architecture BLOCK DIAGRAM Sun UltraSparc T1 ULTRASPARC-II integer execution unit
2001 - SPARC v9 architecture BLOCK DIAGRAM

Abstract: UltraSPARC ii
Text: UltraSPARC-II. Bit 4 of the UltraSPARC-II bus S_REPLY is not used by UltraSPARC-II. Synchronous to system clock , . UltraSPARC-II is part of a second generation of UltraSPARC pipeline-based products. In addition to using a new process technology, the UltraSPARC-II provides a higher clock frequency, multiple SRAM modes and , provides software compatibility with existing UltraSPARC-I based systems. UltraSPARC-II also implements the , UltraSPARC-II frequency. (See Timing Considerations Section on page 233 for more detail.) 216 July 1997


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PDF STP1031 STP1031, 64-bit STP1031 STP1031LGA SPARC v9 architecture BLOCK DIAGRAM UltraSPARC ii
Not Available

Abstract: No abstract text available
Text: DATA SHEET Complete 248 MHz CPU, 1.0 MB E-Cache, UDB-II D e s c r ip t io n The UltraSPARC-II m , the UltraSPARC Port Architecture (UPA) interconnect bus. The m odule consists of one UltraSPARC-II microprocessor, one UltraSPARC-II Data Buffer (consisting of two UDB-II m icrochips), one 32 K x 36 tag SRAM , ratio to the UPA frequency.The m odule is available w ith the UltraSPARC-II run­ ning at 248 MHz. The , ultiprocessing • Range of scalable system s can be built • 1.0 M egabyte E-Cache • UltraSPARC-II


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PDF STP5211 MC100LVE210 5211UPA-250 STP1031) STP1081)
1997 - STP1081

Abstract: 75193 Sun UltraSparc T2 40N20
Text: /300 MHz UltraSPARC-II Systems DESCRIPTION The UltraSPARC-II Data Buffer (UDB-II) consists of two identical ASICs connecting the UltraSPARC-II microprocessor and its E-Cache to the system data bus (i.e , UltraSPARCTM-II Data Buffer (UDB-II) Companion Device for 250/300 MHz UltraSPARC-II Systems STP1081 SRAM , the interconnect. UltraSPARC-II has a second-level cache of at minimum 512 Kilobytes. This , 1997 UltraSPARCTM-II Data Buffer (UDB-II) Companion Device for 250/300 MHz UltraSPARC-II Systems


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PDF STP1081 256-Pin STP1081ABGA-125 STP1081ABGA-150 STP1081 75193 Sun UltraSparc T2 40N20
Not Available

Abstract: No abstract text available
Text: High-Capacity, Two-Speed Data Transfer D e s c r ip t io n The UltraSPARC-II Data Buffer (UDB-II) consists of two identical integrated circuit microchips connecting the UltraSPARC-II microprocessor and its , of the E-Cache and that of the interconnect. UltraSPARC-II has a second-level cache of at m inim um , Transfer F u n c t io n a l O v e r v ie w Data Buffering UltraSPARC-II supports m ultiple outstanding , data com es from the store buffer of the UltraSPARC-II. The processor m akes successive stores to the


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PDF ASAM/CCR-232 1081ABG
in138

Abstract: SPARC v9 architecture BLOCK DIAGRAM cpu lga UltraSPARC ii
Text: io n The UltraSPARC-II module is a high performance, SPARC V9 compliant, small form factor processor , one UltraSPARC-II microprocessor, two UltraSPARC-II Data Buffer chips, one 32 K x 36 tag SRAM, four , to the UPA frequency.The module is available with the UltraSPARC-II run ning at 296MHz. The interface , E-Cache, UDB-II Features · High performance UltraSPARC-II CPU Module · Programmable UPA bus speed · , Gigabytes/sec · Range of scalable systems can be built · UltraSPARC-II Pipelined E-Cache Interface


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PDF MC100LVE210 STP5212UPA-300 296MHz 100MHz STP1031) STP1081) in138 SPARC v9 architecture BLOCK DIAGRAM cpu lga UltraSPARC ii
1999 - Sun Enterprise 250

Abstract: MC100LVE210 RT0201 SME5222AUPA-400
Text: UltraSPARC-II. Synchronous to UPA_CLK. Active high. UPA_REQ_IN[2:0] I UltraSPARC-II system address bus , DESCRIPTION UltraSPARC-II CPU The UltraSPARCTM-II CPU is the second generation in the UltraSPARCTM s-series , E-Cache SME5222AUPA-400 DATA BUFFER DESCRIPTION UltraSPARC-II Data Buffer (UDB-II) The UltraSPARCTM-II module has two UltraSPARC-II data buffers (UDB-II) - each a 256 pin BGA device - for a system bus , clocked with the same clock delivered to UltraSPARC-II (1/2 of the CPU pipeline frequency). EXTERNAL


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PDF SME5222AUPA-400 SME5222AUPA-400) Sun Enterprise 250 MC100LVE210 RT0201 SME5222AUPA-400
1999 - Not Available

Abstract: No abstract text available
Text: -400 UltraSPARCTM-II CPU Module 400 MHz CPU, 4.0 MB E-Cache CPU DESCRIPTION UltraSPARC-II CPU The UltraSPARCTM-II , UltraSPARC-II Data Buffer (UDB-II) The UltraSPARCTM-II module has two UltraSPARC-II data buffers (UDB-II) - each , system side. The CPU side of the UDB-II is clocked with the same clock delivered to UltraSPARC-II (1/2 of , components: · · · · · · UltraSPARCTM-II CPU at 400 MHz UltraSPARC-II Data Buffer (UDB-II) 4.0 Megabyte , Tag SRAM DATA [24:0] UltraSPARC-II CPU UPA ADDR [35:0] + Control SRAM ADDR [19:0] + Control Tag


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PDF SME5224AUPA-400 SME5224AUPA-400)
1999 - Sun Enterprise 250

Abstract: MC100LVE210 RT0201 SME5224AUPA-450 STP2202ABGA BGA 48 "8 x 8" memory micron
Text: CPU Module 450 MHz CPU, 4.0 MByte E-Cache CPU DESCRIPTION UltraSPARC-II CPU The UltraSPARCTM-II , DESCRIPTION UltraSPARC-II Data Buffer (UDB-II) The UltraSPARCTM-II, 450MHz CPU module has two UltraSPARC-II , the same clock delivered to UltraSPARC-II (1/2 of the CPU pipeline frequency). EXTERNAL CACHE , components: · · · · · · UltraSPARCTM-II, 450MHz CPU UltraSPARC-II Data Buffer (UDB-II) 4.0 , ADDR [17:0] + Control Tag SRAM DATA [24:0] UltraSPARC-II CPU UPA ADDR [35:0] + Control SRAM


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PDF SME5224AUPA-450 450MHz SME5224AUPA-450) Sun Enterprise 250 MC100LVE210 RT0201 SME5224AUPA-450 STP2202ABGA BGA 48 "8 x 8" memory micron
2000 - Not Available

Abstract: No abstract text available
Text: UltraSPARC-II. Synchronous to UPA_CLK. Active high. UPA_REQ_IN[2:0] I UltraSPARC-II system address bus , E-Cache CPU DESCRIPTION UltraSPARC-II CPU The UltraSPARC™-II, 480 MHz CPU is the second generation , €¢ UltraSPARC™-II, 480 MHz CPU UltraSPARC-II Data Buffer (UDB-II) Eight Megabyte E-cache, made up of eight (512K Î , is illustrated in Figure 1. Tag SRAM ADDR [17:0] + Control Tag SRAM DATA [24:0] UltraSPARC-II , UltraSPARC-II Data Buffer (UDB-II) The UltraSPARC™-II, 480 MHz CPU module has two UltraSPARC-II data buffers


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PDF SME5224BUPA-480 SME5224BUPA-480)
2001 - MCE-100

Abstract: MCE100
Text: STP5212 July 1997 UltraSPARCTM-II CPU Module DATA SHEET DESCRIPTION The UltraSPARC-II module , UltraSPARC Port Architecture (UPA) interconnect bus. The module consists of one UltraSPARC-II microprocessor, two UltraSPARC-II Data Buffer chips, one 32 K x 36 tag SRAM, four 128k K x 36 data SRAMs, and an , available with the UltraSPARC-II running at 296MHz. The interface to the module is through a high-speed , UltraSPARC-II CPU Module · Programmable UPA bus speed · SPARC V9 Compliant · Implements Visual Instruction Set


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PDF STP5212 MC100LVE210 STP5212UPA-300 296MHz 100MHz STP1031) STP1081) MCE-100 MCE100
1999 - Sun Enterprise 250

Abstract: MC100LVE210 RT0201 SME5224AUPA-360 STP2202ABGA
Text: DESCRIPTION UltraSPARC-II CPU The UltraSPARCTM-II CPU is the second generation in the UltraSPARCTM s-series , DESCRIPTION UltraSPARC-II Data Buffer (UDB-II) The UltraSPARCTM-II module has two UltraSPARC-II data buffers , UltraSPARC-II (1/2 of the CPU pipeline frequency). EXTERNAL CACHE DESCRIPTION The external cache (E-cache , UltraSPARC-II CPU at 360 MHz UltraSPARC-II Data Buffer (UDB-II) 4.0 Megabyte E-cache, made up of eight (256K X , DATA [24:0] UltraSPARC-II CPU UPA ADDR [35:0] + Control SRAM ADDR [19:0] + Control SRAM


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PDF SME5224AUPA-360 SME5224AUPA-360) Sun Enterprise 250 MC100LVE210 RT0201 SME5224AUPA-360 STP2202ABGA
Not Available

Abstract: No abstract text available
Text: UltraSPARC-II in response to a Read To Own (P_RDO_REQ) request for a block from another UltraSPARC-II. â , should be sent to UltraSPARC-II. UltraSPARC-II responds to this request by sending the value of its bus , is forwarded by the system controller to UltraSPARC-II. UltraSPARC-II replies through a P_RAS; then , UltraSPARC-II. Synchronous to the system clock. (3.3V, UPA) N ODE_RQ[2:0] I UltraSPARC-II system , clock. (3.3V, UPA) S_REPLY[3:0] I UltraSPARC-II system reply packet, driven to UltraSPARC-II.


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PDF STP1031 64-Bit STP1031, STP1031 787-Pin
Not Available

Abstract: No abstract text available
Text: ) The UltraSPARC™ -II m odule has two UltraSPARC-II data buffers (UDB-II) - each a 256 pin BGA device , system side. The CPU side of the UD B-II is clocked w ith the same clock delivered to UltraSPARC-II (1 , €¢ UltraSPARC™ -II CPU at 400 M H z • UltraSPARC-II Data Buffer (UDB-II) • 4.0 M egabyte E-cache, made up , UltraSPARC-II pins. The 4-bit M CAP value for this m odule is 0111b. M odule Pow er Two types of pow er are , board as long as the m odule clock timing is satisfied. The UltraSPARC-II CPU and UD B-II data buffers


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PDF E5224UPA-400)
UltraSPARC ii

Abstract: No abstract text available
Text: ( UltraSPARC-II Data Bujjer (UDB-II) Data Sh eet O c t o b e r 1 996 STP1081 S un M ic r o e , , Two-Speed Data Transfer D esc r ip tio n The UltraSPARC-II Data Buffer (UDB-II) consists of two identical integrated circuit microchips connecting the UltraSPARC-II m icroprocessor and its E-Cache to the slower , systembus Interlace to the UltraSPARC-II bus B e n e fits · High performance: ease of design * Fully , delivery rates of the E-Cache and that of the interconnect. UltraSPARC-II has a second-level cache of at m


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PDF STP1081 UltraSPARC ii
1999 - STP2202ABGA

Abstract: RT0201 Sun Enterprise 250 Sun UltraSparc ULTRASPARC MC100LVE210 SME5224AUPA-400
Text: -400 UltraSPARCTM-II CPU Module 400 MHz CPU, 4.0 MB E-Cache CPU DESCRIPTION UltraSPARC-II CPU The UltraSPARCTM-II , -400 DATA BUFFER DESCRIPTION UltraSPARC-II Data Buffer (UDB-II) The UltraSPARCTM-II module has two UltraSPARC-II data buffers (UDB-II) - each a 256 pin BGA device - for a UPA Interconnect system bus width of , the same clock delivered to UltraSPARC-II (1/2 of the CPU pipeline frequency). EXTERNAL CACHE , · UltraSPARCTM-II CPU at 400 MHz UltraSPARC-II Data Buffer (UDB-II) 4.0 Megabyte E-cache, made


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PDF SME5224AUPA-400 SME5224AUPA-400) STP2202ABGA RT0201 Sun Enterprise 250 Sun UltraSparc ULTRASPARC MC100LVE210 SME5224AUPA-400
Not Available

Abstract: No abstract text available
Text: m odule has two UltraSPARC-II data buffers (UDB-II) - each a 256 pin BGA device - for a system bus , the UD B-II is clocked w ith the same clock delivered to UltraSPARC-II (1 /2 of the CPU pipe­ line , o m p o n e n t O v e r v ie w The UltraSPARC-II CPU Module, (SM E5222UPA-400), (see Figure 1), consists of the follow ing components: • UltraSPARC™ -II CPU at 400 M H z • UltraSPARC-II Data , system ASICs. These bits are hardw ired on the m odule and are know n at M CAP[3:0] at the UltraSPARC-II


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PDF SME5222UPA-400 E5222UPA-400)
Not Available

Abstract: No abstract text available
Text: m odule has two UltraSPARC-II data buffers (UDB-II) - each a 256 pin BGA device - for a system bus , the UD B-II is clocked w ith the same clock delivered to UltraSPARC-II (1 /2 of the CPU pipe­ line , C o m p o n e n t O v e r v ie w The UltraSPARC-II CPU Module, (SM E5222AUPA-400), (see Figure 1), consists of the follow ing components: • UltraSPARC™ -II CPU at 400 M H z • UltraSPARC-II Data , UltraSPARC-II pins. The 4-bit M CAP value for this m odule is 0111b. M odule Pow er Two types of pow er are


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PDF SME5222AUPA-400 E5222AUPA-400)
2000 - sun sparc pinout

Abstract: Sun Enterprise 250 MC100LVE210 RT0201 SME5228BUPA-480 STP2202ABGA SPARC v9 architecture BLOCK DIAGRAM velocity of propagation of FR4
Text: -480 UltraSPARCTM-II CPU Module 480 MHz CPU, 8.0 Mbyte E-Cache CPU DESCRIPTION UltraSPARC-II CPU The , , 480 MHz CPU UltraSPARC-II Data Buffer (UDB-II) Eight Megabyte E-cache, made up of eight (512K 18 , is illustrated in Figure 1. Tag SRAM ADDR [17:0] + Control Tag SRAM DATA [24:0] UltraSPARC-II , UltraSPARC-II Data Buffer (UDB-II) The UltraSPARCTM-II, 480 MHz CPU module has two UltraSPARC-II data buffers , UltraSPARC-II (1/2 of the CPU pipeline frequency). EXTERNAL CACHE DESCRIPTION The external cache is


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PDF SME5228BUPA-480 SME5228BUPA-480) sun sparc pinout Sun Enterprise 250 MC100LVE210 RT0201 SME5228BUPA-480 STP2202ABGA SPARC v9 architecture BLOCK DIAGRAM velocity of propagation of FR4
UltraSPARC ii

Abstract: No abstract text available
Text: ( WËÊIÊÈËÎIËKÊËÊË UltraSPARC-II D ata Buffer (UDB-II) Data Sheet October 1996 STP1081 S un M , ip t io n The UltraSPARC-II D ata Buffer (UDB-II) consists of tw o identical in teg rated circuit m icrochips connecting th e UltraSPARC-II m icroprocessor and its E-Cache to the slow er system d ata bus , of the E-Cache and that of the interconnect. UltraSPARC-II has a second-level cache of at m in im u m , io n a l O v e r v ie w Data Buffering UltraSPARC-II supp o rts m ultiple outstan d in g requests to


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PDF STP1081 UltraSPARC ii
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