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Part Manufacturer Description Datasheet Download Buy Part
LT1010CT#TRPBF Linear Technology IC BUFFER AMPLIFIER, PZFM5, LEAD FREE, PLASTIC, TO-220, 5 PIN, Buffer Amplifier
LT1010CN8#TR Linear Technology IC BUFFER AMPLIFIER, PDIP8, 0.300 INCH, PLASTIC, DIP-8, Buffer Amplifier
LT1010CN8#TRPBF Linear Technology IC BUFFER AMPLIFIER, PDIP8, 0.300 INCH, LEAD FREE, PLASTIC, DIP-8, Buffer Amplifier
LT1010CH Linear Technology IC BUFFER AMPLIFIER, MBCY3, METAL CAN, TO-39, 4 PIN, Buffer Amplifier
LT1010CK Linear Technology IC BUFFER AMPLIFIER, MBFM4, METAL CAN, TO-3, 4 PIN, Buffer Amplifier
LT1010MH883 Linear Technology IC BUFFER AMPLIFIER, MBCY3, METAL CAN, TO-39, 4 PIN, Buffer Amplifier

UART TTL buffer Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
2006 - FT232R

Abstract: FT232RQ ft232r MAX232 TTL232R-3V3 serial port to ttl using max232 UART TTL buffer TTL-232R-3V3 TTL-232R TTL232R AN232B05
Text: TM Future Technology Devices International Ltd. TTL -232R USB to TTL Serial Converter Cable The TTL -232R is a USB to TTL serial converter cable incorporating FTDI's FT232RQ USB - Serial UART interface IC device, the latest device to be added to FTDI's range of USB UART interface Integrated Circuit Devices. It is designed to allow for a fast, simple way to connect devices with a TTL level serial , Peripherals to USB Interface Microcontroller UART or I/O to USB Interface FPGA / PLD to USB TTL -232R USB


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PDF TTL-232R TTL-232R FT232RQ FT232R ft232r MAX232 TTL232R-3V3 serial port to ttl using max232 UART TTL buffer TTL-232R-3V3 TTL232R AN232B05
2006 - max232 rts cts

Abstract: TTL-232R-3V3 cmos 3v3 TTL232R-3V3 FT232RQ FT232R USB UART ttl drive MAX232 for level converter USB CABLE notes on serial communication MAX232
Text: Peripherals to USB Interface Microcontroller UART or I/O to USB Interface FPGA / PLD to USB TTL , UART interface I/O pins on the TTL -232R-3V3 (RXD, TXD, RTS#, and CTS#) are configured to use the , specifications. The TTL -232R-3V3 has passed FCC and CE testing. Programmable Receive Buffer Timeout - The , TM Future Technology Devices International Ltd. TTL -232R-3V3 USB to TTL Serial Converter Cable The TTL -232R-3V3 is a USB to TTL serial converter cable incorporating FTDI's FT232RQ USB - Serial


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PDF TTL-232R-3V3 TTL-232R-3V3 FT232RQ FT232R max232 rts cts cmos 3v3 TTL232R-3V3 FT232R USB UART ttl drive MAX232 for level converter USB CABLE notes on serial communication MAX232
2009 - cc2530fx

Abstract: SmartRF04EB 1.9 smartrf04eb CC111xFx SmartRF04EB CC2530 CC2430 RS232 CC2431 software uart UART CC2530
Text: de-asserted ( TTL high). DMA/CPU Allocated source buffer (typically received on RF) UxUCR UART Port , SmartRF® SoC RF RTS RX RS232 TTL TX UART UART protocol USART Evaluation Board Central , (assuming TTL voltage level) which supports the UART protocol, meaning half/full-duplex asynchronous serial , will initiate a single byte DMA transfer from the allocated UART TX source buffer to the UxDBUF , register to the allocated UART RX destination buffer . SWRA222B Page 4 of 28 Design Note DN112


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PDF DN112 CC111xFx, CC243xFx, CC251xFx CC253xFx CC1110Fx CC1111Fx CC2430Fx CC2431Fx CC2510Fx cc2530fx SmartRF04EB 1.9 smartrf04eb CC111xFx SmartRF04EB CC2530 CC2430 RS232 CC2431 software uart UART CC2530
SC11091CV

Abstract: 8096 instruction set SC11054 mc9346n intel 8096 instruction set SC11091 SC11091CQ
Text: 67 57 33 Address lines for UART register select, input, TTL . Chip select, active low, input, TTL . 8-bit data port, input-output, TTL . Data in strobe (PC reads from UART registers), active low, input, TTL . Data out strobe (PC writes into UART registers), active low, input, TTL . Interrupt, output, CMOS , Internal ROM Power Down m ode indicator on PD pin Built-in UART with 80ns data access time in parallel , ( UART DATA BUS) BAUD RATE GENERATOR TRANS MITTER UART INTERRUPT CONTROL RECEIVER C = > IO 0 - K >3


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PDF SC11091/SC11095 68-PIN 42bis SC11091) 16x16 SCU011, SC11024, SC11044, SC11054 SC11091CV 8096 instruction set mc9346n intel 8096 instruction set SC11091 SC11091CQ
2000 - IMP16C550

Abstract: IMP16C450 80284 IMP16C550CJ44 imp16c550-cj44 48-PIN 44-PIN 16-BYTE sim 300 modem datasheet imp16c550cp
Text: (except the Register Buffer , Transmitter Holding and Divisor Latches), and the control logic of the UART , IMP16C550 Data Communications Universal Asynchronous Receiver/Transmitter ( UART )with 16 , Tri-State® TTL drive capabilities for bidirectional data bus and control bus Easily interfaces to most , , DTR, RI,and DCD) The IMP16C550 Universal Asynchronous Receiver Transmitter ( UART ) is a CMOS-VLSI communication device in a single package. The UART performs serial to parallel conversion on data characters


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PDF IMP16C550 16-BYTE IMP16C550 IMP16C550-CJ44 IMP16C550-A48 IMP16C450 80284 IMP16C550CJ44 imp16c550-cj44 48-PIN 44-PIN sim 300 modem datasheet imp16c550cp
2002 - 16-BYTE

Abstract: 44-PIN 48-PIN IMP16C450 IMP16C550 imp dms the av IMP16C5
Text: IMP16C550 Data Communications Universal Asynchronous Receiver/Transmitter ( UART )with 16 , Tri-State® TTL drive capabilities for bidirectional data bus and control bus Easily interfaces to most , , DTR, RI,and DCD) The IMP16C550 Universal Asynchronous Receiver Transmitter ( UART ) is a CMOS-VLSI communication device in a single package. The UART performs serial to parallel conversion on data characters , received from the CPU. The CPU can read the complete status of the UART at any time during the functional


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PDF IMP16C550 16-BYTE IMP16C550 Univer50-CP40 IMP16C550-CJ44 IMP16C550-A48 44-PIN 48-PIN IMP16C450 imp dms the av IMP16C5
T-CON BOARD samsung

Abstract: E804H T-CON BOARD samsung pin 5808H B004H 8004H samsung Timing controller T-con E80CH bufer open drain T-CON BOARD for samsung
Text: Trigger Level Input Buffer TTL Level Input Buffer TTL Schmitt Trigger Level Input Buffer with Pull-up , Buffer TTL Schmitt Trigger Level Input with Pull-up Resistor and Tri-State Output with Medium SlewRate , TTL schimitt trigger z > o o > Input bufer Input bufer Input buffer with pull up o1 ,o2,o3,io1 ,io2 , two-channel UART , twochannel DMA, system manager (chip select logic, DRAM controller), three-channel timer , Two-Channel UART - Three-Channel Timer - Interrupt Controller - Tone Generator - I/O ports - Watch


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PDF KS32C6200 32-Bit KS32C6200 16/32-bit T-CON BOARD samsung E804H T-CON BOARD samsung pin 5808H B004H 8004H samsung Timing controller T-con E80CH bufer open drain T-CON BOARD for samsung
intel 8096

Abstract: STR 11006 SC11011CV intel 8096 instruction set 8096 instruction set A5 MCR 100-6 SC11061 temperature control of 8096 Savoy Electronics mcr 100-6 A26
Text: lines for UART register select, input, TTL . S6-S0 Interrupt, output, CMOS/ TTL . Tristate" 8-bit data port , out strobe (PC writes into UART regis ters), active low, input, TTL . Data in strobe (PC reads from UART registers), active low, input, TTL . Ouput, ready signal for high speed PC-AT interface. RÎ OH , interface to SC11006/024 Pow erful enough to handle M N P5 as w ell as H ayes commands & DSP Built-in UART , bit which switches the UART to bring out the parallel or the serial side of the UART . The MAC receives


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PDF SC11061 68-PIN SC11011CV SC11061CV SC11006/024 J5P312A8-29 SRX3860 intel 8096 STR 11006 SC11011CV intel 8096 instruction set 8096 instruction set A5 MCR 100-6 temperature control of 8096 Savoy Electronics mcr 100-6 A26
Ei16C550-CP40

Abstract: Ei16C550-CJ44 DS1488
Text: reporting capabilities Tri-State® TTL drive for the data bus and control bus Line break generation and , enhanced version of the Ei16C450 Universal Asynchronous Receiver/ Transmitter ( UART ). The improved , transfers. The UART performs serial-to-parallel conversion on data characters received from a peripheral , CPU can read the complete status of the UART at any time during the functional operation. Status information reported includes the type and condition of the transfer operations being performed by the UART


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PDF Ei16C550 Ei16C550-A48 Ei16C550-CP40 Ei16C550-CJ44 Ei16C550-CP40 Ei16C550-CJ44 DS1488
2002 - LM393NE

Abstract: de9s-frs dj005b MCP2155 MCP2150 K D S 11.0592 MHZ HC tfds4500 diode ir 4570 UA7800KTE MAX3238
Text: UART Control, Status and Data Signal Traces ( TTL levels) RX CD Jumper UART Control and Data , Communication Equipment (DCE) applications. This requires some of the UART 's non-data circuits to operate , . This Technical Brief focuses on the Host UART signals from the U2 socket (MCP2150/ MCP2155) to the , Technology Inc. Preliminary DS91059B-page 1 TB059 MCP2150 DEVELOPER'S BOARD UART SIGNALS USING , Figure 2 and Figure 3). Table 1 shows the direction of the MCP2150 and MCP2155 UART signals and the


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PDF TB059 MCP2150 MCP2155 MCP2155 MCP2150 D-85737 LM393NE de9s-frs dj005b K D S 11.0592 MHZ HC tfds4500 diode ir 4570 UA7800KTE MAX3238
2002 - MCP2155

Abstract: MCP2150 DSR 505 200B MAX3238 UART TTL buffer
Text: ) MAX3238 (U1) CTS TX RTS DSR DTR UART Control, Status, and Data Signal Traces ( TTL levels , the NDM state. TX 7 7 8 I TTL Asynchronous receive; from Host Controller UART , Communication Equipment (DCE) applications. This requires some of the UART 's non-data circuits to operate , Figure 1. This Technical Brief focuses on the Host UART signals from the U2 socket (MCP2150/ MCP2155 , Microchip Technology Inc. Preliminary DS91059A-page 1 TB059 MCP2150 DEVELOPER'S BOARD UART


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PDF TB059 MCP2150 MCP2155 MCP2155 MCP2150 D-81739 DSR 505 200B MAX3238 UART TTL buffer
2004 - 74hc273

Abstract: SMD CODE list mosfet 6pin k 2129 MOSFET TRANSISTOR SMD CODE PACKAGE SOT363 TRIAC dimmer control I2C LPC2129 ARM7TDMI-S programming TEA1620P SOT363 flash TEA1623P TEA1620P/N1
Text: Schmitt-Trigger 5 V Dual Bus Buffer /Line Driver; TTL Enabled (3-State) 5 V Triple Inverter; TTL Enabled 5 V , 2-Input NOR Gate; TTL Enabled 5 V Dual 2-Input AND Gate; TTL Enabled 5 V Dual Buffer /Line Driver with Active LOW Output Enable; TTL Enabled (3-State) 5 V Dual Buffer /Line Driver with Active HIGH , Package 74HCT3G07 74HCT3G14 74HCT3G34 5 V Triple Open Drian Buffer ; TTL Enabled 5 V Triple Inverting Schmitt Trigger; TTL Enabled 5 V Triple Buffer Gate; TTL Enabled DC DC DC Interface


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PDF PCA9510, PCA9511, PCA9512, PCA9513, PCA9514 74ALVCxxx BGA2715, BGA2716 LPC2119, LPC2129 74hc273 SMD CODE list mosfet 6pin k 2129 MOSFET TRANSISTOR SMD CODE PACKAGE SOT363 TRIAC dimmer control I2C LPC2129 ARM7TDMI-S programming TEA1620P SOT363 flash TEA1623P TEA1620P/N1
SC11091

Abstract: SC11064 sw 2604 ic schematic SC11011 sc11061 mc9346n SC11091CQ SC11091C SC11091CV mc9346
Text: ,33 65 59 67 61 Address lines for UART register select, input, TTL . Chip select, active low, input, TTL . 8-bit data port, input-output, TTL . D0-D 7 DIS DÖS Data in strobe (PC reads from UART registers), active low, input, TTL . Data out strobe (PC writes into UART registers), active low, input, TTL , ROM Pow er D ow n m ode indicator on PD pin Built-in UART w ith 80ns data access time in parallel m , patible UART w hich can be configured to provide a serial o r parallel DTE interface. In th e RDY m o d e


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PDF SC11091/SC11095 68-PIN 42bis SC11091/SC11095) 16x16 SC11011 SC11024, SC11026, SC11044, SC11091 SC11064 sw 2604 ic schematic sc11061 mc9346n SC11091CQ SC11091C SC11091CV mc9346
str w 6554 a

Abstract: str w 6554 ic str 6554 a SC11040 intel 8096 ic str 6554 SC11043 str f 6554 SC11031 8 PIN RELAY 6V dc pla circuit diagram
Text: for UART register select. INPUT, TTL . Chip select, active low. INPUT-OUTPUT, TTL . 8 -bit data port. > CS D0 -D 7 DÎS DOS INTO RDY > INPUT, TTL . Data in strobe (PC reads from UART registers), active low. INPUT, TTL . Data out strobe (PC writes into UART registers), active low. OUTPUT, CMOS/ TTL , internal RAM Power Down mode indicator on PD pin CMOS technology 16C450 compatible UART APPLICATIONS V , UART INTERRUPT CONTROL RECEIVER Figure 1. Rev 1.0 1-271 SC11031/SC11040/SC11041/SC11042


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PDF 42bis, 128Kx8 25Kx8 16x16 SC11011, SC11031/SC11040 str w 6554 a str w 6554 ic str 6554 a SC11040 intel 8096 ic str 6554 SC11043 str f 6554 SC11031 8 PIN RELAY 6V dc pla circuit diagram
OXPCI958

Abstract: PU5103 AT96C46 at96c AD-29B C80-004 63 marking PMDS 88h-8Fh OX16PCI958 16C550
Text: Programming Line control (bit 7) SCC UART Data Mnem. Receiver buffer RBR Transmitter , OX16PCI958 DATA SHEET Octal UART with PCI Interface FEATURES · · · · · · · · · · , Driver-facilitated DSR/DTR & Xon/Xoff handshaking 5-,6-,7- & 8-bit data framing 1, 1.5 or 2 stop bits UART , eight-byte programming interface to each UART . The UARTs are fully software-compatible with 16C550 devices , the receive FIFO. The state of the UART can be found at any time by reading status registers, and


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PDF OX16PCI958 32-bit, 16C550type 16C550/450 32-byte DS-0022 OX16PCI958-PQAG OXPCI958 PU5103 AT96C46 at96c AD-29B C80-004 63 marking PMDS 88h-8Fh 16C550
2013 - Not Available

Abstract: No abstract text available
Text: Transceiver UART Controller Tx Buffer RTS DTR DSR Tx_LED Rx Buffer GND Rx_LED VCFG , -232 Converter . 9 USB to UART cable with TTL level UART signals . , IC is used on the serial UART interface of the CY7C74225 to convert the TTL levels of the CY7C64225 , TTL level UART signals This example illustrates a USB to UART cable design with TTL Level UART , with TTL level UART signals VDD VDD VDD VDD VBUS VBUS D+ 1k GND Rx_LED 560 D


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PDF CY7C64225
2013 - imo plc cable rs232

Abstract: RS232 TTL self powered transceiver rs232 driver receiver rx1 tx1 android CY7C64225
Text: -232 Converter . 9 USB to UART cable with TTL level UART signals . , IC is used on the serial UART interface of the CY7C74225 to convert the TTL levels of the CY7C64225 , Document Number: 001-76294 Rev. *B Page 9 of 19 CY7C64225 USB to UART cable with TTL level UART signals This example illustrates a USB to UART cable design with TTL Level UART Signals using CY7C64225. This design is based on bus powered configuration. Figure 7. USB to UART cable with TTL level UART


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PDF CY7C64225 28-pin imo plc cable rs232 RS232 TTL self powered transceiver rs232 driver receiver rx1 tx1 android CY7C64225
2000 - TDA50

Abstract: TDA5056 quad video processor
Text: Semiconductors SYMBOL CS_RGN CLK UART 0 interface (4 pins) RXD0 TXD0 RTSN0 CTSN0 141 142 143 144 I O O I TTL input 2 mA output drive 2 mA output drive TTL input 5V 3.3 V 3.3 V 5V UART 0 receive data line or , UART 1 and SSI interfaces (5 pins) RXD1/V34_RXD TXD1/V34_TXD RTSN1/V34_FS 137 138 139 I O I/O TTL input , interface to IEEE 1394 devices (such as Philips PDI 1394 chip-set) · Two UART (RS232) data ports with Direct , front-end · An elementary UART with DMA capabilities, dedicated to front panel devices for instance · Two


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PDF SAA7219 753504/02/pp20 TDA50 TDA5056 quad video processor
1999 - ms-029fa1

Abstract: ejtag dvb SQFP208 MIPS16 ssi 202 smart card tda8004 SAA7219HS S-108 quad video processor IEEE 1284 Peripheral Interface Controller
Text: 141 I TTL input 5V UART 0 receive data line or receive serial data TXD0 142 O , interface CTSN0 144 I TTL input 5V UART 0 clear to send or serial I/O interface clock of the SSI interface UART 0 interface (4 pins) UART 1 and SSI interfaces (4 pins) 137 I TTL , 140 I TTL input 5V UART 1 clear to send or serial input interface clock of the SSI , interface (36.684 MHz) RXD2 135 I TTL input 5V UART 2 receive data line TXD2 136


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PDF SAA7219 SAA7219 545004/01/pp20 ms-029fa1 ejtag dvb SQFP208 MIPS16 ssi 202 smart card tda8004 SAA7219HS S-108 quad video processor IEEE 1284 Peripheral Interface Controller
1999 - STDM85

Abstract: KS32C5000AA hdlc KS32C5000A KS32C500
Text: channel 0 receive buffer register Undefined URXBUF1 0xE010 W UART channel 1 receive buffer , Important peripheral functions include two HDLCs, two UART channels, 2-channel GDMA, two 32-bit timers, and , controller · HDLC · GDMA · UART · Timers · Programmable I/O ports · , HDLCs System Manager · · · Four-word depth write buffer · Cost-effective , Programmable I/O UARTs · 18 programmable I/O ports · Two UART (serial I/O) blocks with DMA-based


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PDF 2-5000A KS32C5000A KS32C5000AA 16/32-bit 60BSC STDM85 hdlc KS32C500
2001 - SQFP208

Abstract: yc 645 smd pin diagram jtag dvb china CBC 184 transistor PDI 1284 saa7215 SQFP-208 quad video processor
Text: UART 0 request to send CTSN0 144 I TTL input 5V UART 0 clear to send UART 0 interface (4 pins) UART 1 and SSI interfaces (5 pins) 137 I TTL input 5V UART 1 receive data , MHz) RXD2 135 I TTL input 5V UART 2 receive data line TXD2 136 O 2 mA , OFFN0 133 I TTL input 5V ISO UART 0 card presence SC_I/O0 134 I/O , output drive 3.3 V ISO UART 1 reset of the card OFFN1 125 I TTL input 5V ISO UART


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PDF SAA7219 SAA7219 753504/03/pp20 SQFP208 yc 645 smd pin diagram jtag dvb china CBC 184 transistor PDI 1284 saa7215 SQFP-208 quad video processor
str w 6554 a

Abstract: str w 6554 intel 8096 str 6554 SC11031 kxo-110 196608 mhz SC11042CV marking g2l SC11031CV 8096 block diagram
Text: . Parallel System s Interface (to P C bus) 57,55,53 INPUT, TTL . Address lines for UART register select. 64 , INPUT, TTL . Data in strobe (PC reads from UART registers), active low. 59 INPUT, TTL . Data out strobe (PC writes into UART registers), active low. 67 OUTPUT, CMOS/ TTL . TristateTM. Interrupt. 61 OUTPUT , compatible UART APPLICATIONS V.22bis m odem w ith V.42bis compression (11043) MNP2-5 modems Class 1 , . These devices contain a 16C450 compatible UART which can be configured to provide a serial or parallel


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PDF SC11031/SC11040/SC11041/SC11042/SC11043 68-PIN 242G10 SCU031/SC11040/SC11041/SC11042/SC11043 42bis, 128Kx8 25Kx8 16x16 str w 6554 a str w 6554 intel 8096 str 6554 SC11031 kxo-110 196608 mhz SC11042CV marking g2l SC11031CV 8096 block diagram
2014 - Not Available

Abstract: No abstract text available
Text: Transceiver UART Controller Tx Buffer RTS DTR DSR Tx_LED Rx Buffer GND Rx_LED VCFG , -232 Converter . 9 USB to UART cable with TTL level UART signals . , IC is used on the serial UART interface of the CY7C74225 to convert the TTL levels of the CY7C64225 , TTL level UART signals This example illustrates a USB to UART cable design with TTL Level UART , with TTL level UART signals VDD VDD VDD VDD VBUS VBUS D+ 1k GND Rx_LED 560 D


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PDF CY7C64225
2007 - ph5n

Abstract: "ph4n" ph6n UART TTL buffer ph0n DDRDATA11 kss3k
Text: input buffer , 3.3 V tolerant, PU TTL output buffer , 3.3V capable,4 mA TTL Schmitt trigger input buffer , _0 TEST_1 TEST_2 TEST_3 TEST_4 TEST_5 nTRST TTL input buffer , 3.3 V tolerant, PD DEBUG TDO E17 , Clock Test Data Input Test Mode Select TTL BIDIR buffer , Programmable Logic I/O 3.3V capable, 4mA , G5 F5 I/O TTL BIDIR buffer , Programmable Logic I/O 3.3V capable, 4mA 3.3V tolerant, PU Direction , E7 D7 I/O TTL BIDIR buffer , Programmable Logic I/O 3.3V capable, 4mA 3.3V tolerant, PU Direction


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PDF SPEAR-09-H122 Head600 ARM926EJ-S 333MHz. 600KByte 128KByte 166MHz 32KByte 8/16bit 200MHz) ph5n "ph4n" ph6n UART TTL buffer ph0n DDRDATA11 kss3k
2007 - ph6n

Abstract: transistor PH6n SPEAR-09-P022 TA 8268 analog UART TTL buffer transistor ph0n ta 8268 p022 ph4n upd programmable timer
Text: TTL Output Buffer 3.3V capable, 4mA Input UART UART2_RXD AB20 Input FIRDA_TXD AA18 , channel Analog buffer 2.5V tolerant Input Test Reset Input TTL Schmitt trigger input buffer , 3.3 V tolerant, PU E17 Output Test Data Output TTL output buffer , 3.3V capable,4 mA E16 Input Test Clock TTL Schmitt trigger input buffer , 3.3 V tolerant, PU D16 Input Test Data Input TMS 10/37 Input TDI PL TTL input buffer , 3.3 V tolerant, PD TCK


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PDF SPEAR-09-P022 Plus600 ARM926EJ-S 333MHz. 600KByte 128KByte 166MHz 32KByte 8/16bit 200MHz) ph6n transistor PH6n SPEAR-09-P022 TA 8268 analog UART TTL buffer transistor ph0n ta 8268 p022 ph4n upd programmable timer
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