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Part Manufacturer Description Datasheet Download Buy Part
TURBO-DECO-X2-UT3 Lattice Semiconductor Corporation SITE LICENSE TURBO DECODER XP2
TURBO-DECO-X2-U3 Lattice Semiconductor Corporation IP CORE TURBO DECODER XP2
TURBO-DECO-XP-N1 Lattice Semiconductor Corporation IP CORE TURBO DECODER XPGA
TURBO-DECO-P2-U3 Lattice Semiconductor Corporation IP CORE TURBO DECODER ECP2
TURBO-DECO-PM-UT3 Lattice Semiconductor Corporation SITE LICENSE TURBO DECODER ECP2M
TURBO-DECO-XM-UT3 Lattice Semiconductor Corporation SITE LICENSE TURBO DECODER XP

Turbo decoder Xilinx Datasheets Context Search

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2002 - Turbo decoder Xilinx

Abstract:
Text: Package 3GPP Compliant Turbo Convolutional Decoder 3GPP Compliant Turbo Convolutional Encoder 3GPP Turbo Decoder Xilinx Xilinx Xilinx SysOnChip LogiCORE LogiCORE LogiCORE AllianceCORE Viterbi Decoder , Turbo , Encoder TURBO_DEC Turbo Decoder Viterbi Decoder SysOnChip TILAB TILAB Xilinx AllianceCORE , Support (Continued) Function 8b/10b Decoder Vendor Name Xilinx IP Type LogiCORE Key Features Industry std , Error correction, wireless, DVB, Satellite data link DVB-RCS Turbo Decoder iCODING AllianceCORE


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PDF UG012 Turbo decoder Xilinx verilog code for floating point adder 80C31 instruction set dvb-RCS chip AX1610 verilog code for FFT 32 point 65-bit G.727 matlab vhdl code of 32bit floating point adder vhdl code direct digital synthesizer
2008 - Turbo decoder Xilinx

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Text: from Xilinx . For more information, visit the Turbo Decoder product page. Contact your local Xilinx , 3GPP LTE Turbo Decoder v2.0 XMP020 June 24, 2009 Product Brief Introduction General Description The Turbo Convolution Code (TCC) decoder core is used in conjunction with a TCC encoder to , data reliably over noisy data channels. The turbo decoder operates very well under low signal-tonoise , 3GPP LTE Turbo Decoder v2.0 Performance The performance of the core varies with FPGA family and


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PDF XMP020 Turbo decoder Xilinx Turbo Decoder lte turbo encoder LTE Turbo decoder xilinx lte TURBO decoder turbo encoder design using xilinx design of lte turbo encoder XILINX,ISE xilinx TURBO decoder
2008 - Turbo decoder Xilinx

Abstract:
Text: LTE UL Channel Decoder v2.0 XMP024 June 24, 2009 Product Brief Introduction The Xilinx ® LTE UL Channel Decoder core provides designers with an LTE Uplink Channel Decoding block for the 3GPP , Identifier to ensure block synchronization. · Scalable performance of Turbo Decoder and Block Decoder , full license must be obtained from Xilinx . For more information, visit the LTE UL Channel Decoder , ) size according to the configuration parameters. · Decoding - Turbo decoding applied to UL-SCH


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PDF XMP024 Turbo decoder Xilinx CRC lte xilinx lte TURBO decoder LTE uplink TB lte automatic repeat request redundancy version turbo decoder
2003 - turbo encoder circuit, VHDL code

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Text: IEEE 802.16-Compatible Turbo Product Code Decoder v1.1 DS212 June 30, 2008 Product , Synthesis None Support Provided by Xilinx , Inc. Applications The TPC decoder core operates in , IEEE 802.16-Compatible Turbo Product Code Decoder v1.1 Pinout Figure 1 shows the top level , 30, 2008 Product Specification IEEE 802.16-Compatible Turbo Product Code Decoder v1.1 Table 1 , 802.16-Compatible Turbo Product Code Decoder v1.1 Table 2 lists the Hamming code generator polynomials


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PDF 16-Compatible DS212 turbo encoder circuit, VHDL code turbo codes matlab simulation program turbo codes matlab code 5 to 32 decoder using 38 decoder vhdl code hamming decoder vhdl code vhdl code hamming Comtech Aha 4501 4 bit SISO block diagram code hamming vhdl code for 4-bit counter
2007 - spartan ucf file 6

Abstract:
Text: Xilinx . For more information, visit the IEEE 802.16e CTC Decoder Product Page. Contact your local Xilinx , IEEE 802.16e CTC Decoder v4.0 XMP004 December 2, 2009 Product Brief Introduction 88 Mbps , 802.16e CTC decoder core performs iterative decoding of channel data that has been encoded as described , decoder core is capable of achieving high throughput. The decoded data rate reaches up to 220 Mbps with , Xilinx Implementation Tools ISE 11.2 Verification ModelSim PE 6.2c Simulation ModelSim


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PDF XMP004 16e-2005 16Rev2/D0b spartan ucf file 6 vhdl code for spartan 6 vhdl spartan 3a turbo codes using vhdl Spartan 3E VHDL code Puncturing vhdl virtex ucf file 6 vhdl code for turbo decoder interleaver by vhdl
2001 - software defined radio

Abstract:
Text: of the Turbo Decoder 7.4% of XC2V6000 2811 slices 4 Block RAMs tools. The Filter silicon. This , /dsp/. and a Turbo Codec. reduces power consumption. Turbo Decoder Turbo Decoder Viterbi Dec. Turbo Decoder Turbo Decoder Viterbi Dec. Viterbi Dec. Viterbi Dec. Fall/Winter 2001 Xcell Journal 83 , parallel architecture within Turbo Encoder the device. Flexibility One of the key aspects of an SDR , . Xilinx also offers a complete solution for general DSP development and has made significant advances to


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2006 - turbo encoder model simulink

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Text: Xilinx 3GPP Turbo Encoder and Decoder cores is incorporated into a System Generator design to provide , , logic gates, etc.) and custom blocks, such as the Xilinx Turbo encoder and decoder . Figure 2 shows that , Xilinx Turbo encoder or decoder data sheets for more details (provided within the ZIP file associated , Xilinx Turbo Encoder or Decoder is required, the design must be re-synthesized. This section describes , . Create the Xilinx Turbo encoder and decoder hardware design files. The encoder and decoder are brought


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PDF XAPP948 xc2v3000' turbo encoder model simulink xilinx TURBO decoder FER performance of the Turbo code matlab code turbo encoder design using xilinx Turbo decoder Xilinx timing metric for AWGN channel matlab code system generator matlab ise turbo encoder simulink vhdl code for siso shift register XAPP948
2008 - verilog code for 2-d discrete wavelet transform

Abstract:
Text: Interleaver / De-interleaver Reed-Solomon Decoder Reed-Solomon Encoder Turbo Convolutional Code Decoder , CDMA2000/3GPP2 Turbo Convolutional Code Encoder, CDMA2000/3GPP2 UMTS/3GPP Turbo Convolutional Decoder UMTS/3GPP Turbo Convolutional Encoder IEEE 802.16 TPC , Solomon Decoder (MC-XIL-RSDEC) Avnet Reed Solomon Encoder (MC-XIL-RSENC) Avnet Turbo Decoder , 3GPP SysOnChip, Inc. Turbo Decoder , 3GPP (S3000) iCoding Technology, Inc


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2008 - vhdl code for DES algorithm

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Text: Reed-Solomon Decoder 4 Reed-Solomon Encoder 4 Turbo Convolutional Code Decoder , CDMA2000/3GPP2 4 Turbo Convolutional Code Encoder, CDMA2000/3GPP2 4 UMTS/3GPP Turbo Convolutional Decoder , Design Tool and comes with an extensive library of Xilinx LogiCORE IP. Reed Solomon Decoder (MC-XIL-RSDEC) 4 Avnet Reed Solomon Encoder (MC-XIL-RSENC) 4 Avnet Turbo Decoder , 3GPP 4 SysOnChip, Inc. Turbo Decoder , 3GPP (S3000) 4 iCoding Technology, Inc. Turbo Decoder , DVB-RCS


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2005 - xilinx TURBO decoder

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Text: The data into the DIN port of the Turbo Decoder core must be generated using the Xilinx TCC Encoder , 0 3GPP2 Turbo Decoder v1.0 DS275 April 28, 2005 0 Product Specification 0 Features , data storage · To be used with Xilinx CORE GeneratorTM system v7.1i The TCC decoder is used in , data channels. The turbo decoder core operates very well under low-signal to noise conditions and , Log MAP Turbo Decoder , describes this approach in greater detail. www.xilinx.com DS275 April 28


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PDF DS275 CDMA2000/3GPP2 xilinx TURBO decoder Turbo Code LogiCORE IP License Terms RSC11 Turbo decoder Xilinx XC2V500 XC2VP20
2001 - 80C31 instruction set

Abstract:
Text: Multiplexer Slice 3G FEC Package 3GPP Compliant Turbo Convolutional Decoder 3GPP Compliant Turbo Convolutional Encoder 3GPP Turbo Decoder 8b/10b Decoder 8b/10b Encoder ADPCM 1024 Channel ADPCM 16 Channel ADPCM 256 , Turbo Decoder Fast Ethernet (10/100 Mbps) MAC Evaluation Board Fast Ethernet (10/100 Mbps) Media Access , Encoder Reed-Solomon Decoder Vendor Name Xilinx Xilinx Xilinx Xilinx sysonchip Xilinx Xilinx Amphion , XF-HDLC Controller SPEEDROUTER Network Processor T1 Deframer T1/E1 Framer Turbo Decoder - 3GPP Turbo


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PDF 8b/10b DO-DI-ADPCM32) DO-DI-ADPCM64) CC-201) CC-200) CRC10 CC-130) CRC32 CC-131) 80C31 instruction set xc2s200 pq208 xilinx code for 8-bit serial adder dvb-RCS transmitter XC2S50 driver PIC Microcontroller GSM Modem POS-PHY ATM format dvb-RCS modulator uart 16450 128-bit key generation matlab code for image enc
2002 - 80C31 instruction set

Abstract:
Text: Communication & Networking 3G FEC Package 3GPP Compliant Turbo Convolutional Decoder 3GPP Compliant Turbo Convolutional Encoder 3GPP Turbo Decoder 8b/10b Decoder 8b/10b Encoder ADPCM 1024 Channel ADPCM 16 Channel ADPCM , Modulator Core DVB-RCS Turbo Decoder Fast Ethernet (10/100 Mbps) MAC Evaluation Board Fast Ethernet (10/100 , XC2V1000-4 XC4005XL-1 XC4010XL-9 XCV50-6 XC2V40 XCS30-4 Key Features Viterbi Decoder , Turbo Codec , Framer Turbo Decoder - 3GPP Turbo Encoder TURBO_DEC Turbo Decoder UTOPIA Level-2 PHY Side RX Interface


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PDF 8b/10b DO-DI-ADPCM32) DO-DI-ADPCM64) CC-201) CC-200) CRC10 CC-130) CRC32 CC-131) 80C31 instruction set XC2S200 pq208 xilinx fifo generator 6.2 design BCD adder pal application of 8259 microcontroller MC68000 opcodes AX1610 adder xilinx dvb-RCS modem hitachi pbx
2001 - xilinx vhdl code for floating point square root

Abstract:
Text: deep Communication & Networking 3G FEC Package 3GPP Compliant Turbo Convolutional Decoder 3GPP Compliant Turbo Convolutional Encoder Xilinx LogiCORE Viterbi Decoder , Turbo Codec, Convolutional Enc 80% 40 , correction, wireless Xilinx LogiCORE Xilinx LogiCORE 65% 60 XC2V250 3GPP Turbo , switches DVB-RCS Turbo Decoder Flexbus 4 Interface Core, 16-Channel (DO-DI-FLX4C16) Flexbus 4 Interface , Reed-Solomon Decoder Xilinx LogiCORE 40% 98 XC2V250 Std or custom coding, 312 bit symbol


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PDF XC2V1000-4 UG002 xilinx vhdl code for floating point square root multiplier accumulator MAC code verilog multi channel UART controller using VHDL 80C31 instruction set vhdl code of 32bit floating point adder verilog code for floating point adder xilinx logicore fifo generator 6.2 vhdl code for 3-8 decoder using multiplexer vhdl code 32bit LFSR xilinx vhdl code for floating point square root o
2007 - lte turbo encoder

Abstract:
Text: Downlink Chip Rate" · "3GPP LTE Turbo Decoder " · "3GPP LTE Turbo Encoder" · "3GPP RACH Preamble Detector" · "3GPP Searcher" · "3GPP Turbo Convolutional Code Decoder " · "3GPP Turbo Convolutional Code Encoder" · "3GPP2 Turbo Convolutional Code Decoder " · "3GPP2 Turbo Convolutional Code Encoder" · "802.16E Convolutional Turbo Code (CTC) Decoder " · "802.16E Convolutional Turbo Code (CTC) Encoder" · , " · "Reed-Solomon Decoder " · "Reed-Solomon Encoder" · " Turbo Product Code (TPC) Decoder " · "Viterbi


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PDF XTP025 L3/24/08 lte turbo encoder its 31567 data sheet xilinx lte TURBO decoder LDPC encoder decoder ip core XTP025 LDPC decoder ip core LTE DL Channel Encoder 24604 25160 dvb-s encoder design with fpga
2007 - LDPC decoder ip core

Abstract:
Text: Downlink Chip Rate" · "3GPP LTE MIMO Decoder " · "3GPP LTE MIMO Encoder" · "3GPP LTE Turbo Decoder " · , Convolutional Code Decoder " · "3GPP Turbo Convolutional Code Encoder" · "3GPP2 Turbo Convolutional Code Decoder " · "3GPP2 Turbo Convolutional Code Encoder" · "802.16E Convolutional Turbo Code (CTC) Decoder , Factor Reduction" · "Reed-Solomon Decoder " · "Reed-Solomon Encoder" · " Turbo Product Code (TPC , Release Date v2.0 33266 11.3 September 16, 2009 3GPP LTE Turbo Decoder Product Page


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PDF XTP025 LDPC decoder ip core 33258 24604 LDPC decoder timing lte turbo encoder 223-28 XTP025 3GPP LTE MIMO Decoder LDPC encoder defective pixel correction
1994 - DO-DI-AWGN

Abstract:
Text: Xilinx Additive White Gaussian Noise Core | Silicon Solutions | Design Resources | Services | Documentation | Home : Products & Services : Intellectual Property : Xilinx Turbo Product Code Xilinx , such as Reed-Solomon, Viterbi Decoder , Turbo Convolutional code or Turbo Product code are generated , customers Download the AWGN Xilinx Additive White Gaussian Noise Core q q q q q q q q q , synthesizable with Synplify Pro Incorporate Xilinx Smart-IP Technology for maximum and predictable performance


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2005 - RTL 8186

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Text: utilization estimate of the IEEE 802.16e CTC decoder core. These estimates are given by the Xilinx ISE , CTC decoder core using the Xilinx ISE 8.1.03i software (PRODUCTION 1.58 2006-02-24, STEPPING level 1). Table 11: IEEE 802.16 CTC Decoder Core Static Timing Results Xilinx FPGA Clock Speed (MHz , addition to the decoder core, the hardware test bench contains an LFSR-based data generator, the Xilinx , 0 IEEE 802.16e CTC Decoder Core DS137 (v2.3) July 11, 2006 0 Product Specification 0


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PDF DS137 16-2004/Cor1/D5 RTL 8186 vhdl code for block interleaver turbo encoder circuit, VHDL code RTL 8190 Turbo Code LogiCORE IP License Terms 32 bit adder vhdl code matlab code for half adder xilinx TURBO decoder Turbo decoder Xilinx 8085 vhdl
2005 - matlab codes for wcdma rake receiver

Abstract:
Text: efforts as a baseline to eventually merge the development efforts into © 2005 Xilinx , Inc. All rights reserved. XILINX , the Xilinx logo, and other designated brands included herein are trademarks of Xilinx , for voice users encompasses the Viterbi decoder , deinterleaver, and rate matching. Symbol-rate processing for data additionally includes turbo encoding and decoding. Chip-rate processing involves the , requires significant parallel processing and, therefore, is ideally suited for Xilinx FPGA implementation


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PDF XAPP726 pp1064-1070. matlab codes for wcdma rake receiver 3G HSDPA circuits diagram HSDPA matlab wcdma simulink turbo encoder circuit, VHDL code mimo model simulink hsdpa matlab codes 3g hsdpa signal antenna Diagram umts turbo encoder circuit 3G HSDPA cell capacity planning
2004 - vhdl codes for Return to Zero encoder in fpga

Abstract:
Text: Template The 3GPP2 Turbo Encoder core can be used in conjunction with the Xilinx 3GPP2 Turbo Decoder (available from the Xilinx CORE GeneratorTM system) to provide an extremely effective way of transmitting , Support General Description Provided by Xilinx , Inc @ www.xilinx.com The 3GPP2 Turbo Encoder core , 0 3GPP2 Turbo Encoder v2.0 DS604 April 2, 2007 0 Product Specification 0 Features , -3, Spartan-3E, Spartan-3A/3AN/3A DSP FPGAs Core Specifics · Implements the 3GPP2/CDMA-2000 Turbo


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PDF DS604 3GPP2/CDMA-2000 vhdl codes for Return to Zero encoder in fpga turbo encoder design using xilinx Turbo Decoder rsc Encoder turbo-code vhdl code for CDMA turbo codes using vhdl MULT18X18S convolution encoder with interleaver
2003 - Bosch radar

Abstract:
Text: the early research and development of object detection and automotive network technologies. Xilinx , are in the early stages of development. Xilinx FPGA performance ensures superior performance today , byte-enable support. Xilinx IQ Solutions for Automotive Intelligence · Xilinx offers a range of , available from CAST, Bosch, and Xylon · Xilinx FPGAs provide unrivaled DSP performance­faster than any , Core Xilinx Virtex-II Pro Platform 8x8 Multiplier Accumulate (MAC) 4.8 Billion MAC/s fclk =


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2008 - turbo encoder design using xilinx

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Text: LTE DL Channel Encoder v2.0 XMP023 April 24, 2009 Product Brief Introduction The Xilinx , speed and area · Fully synchronous design using a single clock · For use with the Xilinx , , PCH, and MCH transport blocks · · CRC · Overview Encoding Turbo code , . Code block segmentation applied to DL-SCH, PCH, and MCH transport blocks (i.e., data that are turbo , by the core: © 2008-2009 Xilinx , Inc., XILINX , the Xilinx logo, Virtex, Spartan, ISE and other


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PDF XMP023 16-bit turbo encoder design using xilinx CRC24 lte turbo encoder LTE DL Channel Encoder lte xilinx turbo convolution encoder CRC lte CRC-24 ds699 design of lte turbo encoder
2008 - lte turbo encoder

Abstract:
Text: . Date Version 09/19/08 1.0 Revision Initial Xilinx release. 3GPP LTE Turbo Encoder , information about the Xilinx ® LogiCORETM IP 3GPP LTE Turbo Encoder v2.0 bit accurate C model for 32-bit and , the Xilinx LogiCORETM IP 3GPP LTE Turbo Encoder v2.0 bit accurate C model for 32-bit and 64-bit Linux , /support. Xilinx provides technical support for use of this product as described in 3GPP LTE Turbo , 3GPP LTE Turbo Encoder Bit-Accurate C Model UG506 (v1.0) September 19, 2008 Xilinx


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PDF UG506 32-bit 64-bit lte turbo encoder AMD64 DS701 LTE turbo lte xilinx turbo xilinx lte xilinx TURBO
2008 - bch verilog code

Abstract:
Text: Xilinx ® LogiCORETM IP LTE DL Channel Encoder core provides designers with an LTE Downlink Channel , For use with the Xilinx CORE GeneratorTM software v13.4 Documentation Design Files Example Design , Xilinx , Inc. 1. 2. 3. 4. For a complete listing of supported devices, see the release notes for this , version of the tools, see the ISE Design Suite 13: Release Notes Guide © Copyright 2008­2012 Xilinx , Inc. Xilinx , the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Zynq, and other designated brands


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PDF XMP023 ZynqTM-7000, bch verilog code vhdl code lte vhdl code CRC for lte vhdl convolution coding vhdl code for lte channel coding redundancy version LTE DL Channel Encoder ds699 CRC24 xilinx virtex 5 mac 1.3
2004 - 56B3

Abstract:
Text: of the Xilinx Turbo Code LogiCORE IP License Terms. The module is shipped as part of the Vivado , Updated for re-designed 3GPP Turbo Encoder (v2.0) Updated to version 3.0 standards and Xilinx tools 8.2i , LogiCORE IP 3GPP Turbo Encoder v4.1 DS319 July 25, 2012 Product Specification Introduction This version of the Turbo Convolution Code (TCC) encoder is designed to meet the 3GPP mobile , Available through the Xilinx VivadoTM Design Suite Provided with Core Documentation Design Files Example


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PDF DS319 56B3 5.6B3 FFG1157 block interleaver in modelsim Turbo Code LogiCORE IP License Terms umts turbo encoder vhdl convolution coding
2002 - block diagram code hamming using vhdl

Abstract:
Text: -Compatible Turbo Product Code Encoder v1.0 Performance Characteristics Using the Xilinx static timing analysis , IEEE 802.16-Compatible Turbo Product Code Encoder v1.0 DS211 June 30, 2008 Product , Requirements Xilinx ® Implementation Tools ISE® 4.2.03i or later Verification Mentor Graphics , . Provided by Xilinx , Inc. The TPC Encoder core is especially useful for those communication links that , forward error correction capability. Turbo Product Codes offer a higher performance alternative to


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PDF 16-Compatible DS211 block diagram code hamming using vhdl hamming test bench vhdl code hamming window vhdl code hamming hamming code FPGA vhdl code for 8 bit parity generator block diagram code hamming hamming code in vhdl vhdl code for 4 bit even parity generator TPC encoder design using xilinx
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