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LTC3444EDD#PBF Linear Technology LTC3444 - Micropower Synchronous Buck-Boost DC/DC Converter for WCDMA Applications; Package: DFN; Pins: 8; Temperature Range: -40°C to 85°C
LTC3444EDD#TRPBF Linear Technology LTC3444 - Micropower Synchronous Buck-Boost DC/DC Converter for WCDMA Applications; Package: DFN; Pins: 8; Temperature Range: -40°C to 85°C
LTC3444EDD Linear Technology LTC3444 - Micropower Synchronous Buck-Boost DC/DC Converter for WCDMA Applications; Package: DFN; Pins: 8; Temperature Range: -40°C to 85°C
LTC3444EDD#TR Linear Technology LTC3444 - Micropower Synchronous Buck-Boost DC/DC Converter for WCDMA Applications; Package: DFN; Pins: 8; Temperature Range: -40°C to 85°C

Turbo Decoder wcdma sova Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
2002 - 3GPP turbo decoder log-map

Abstract: sova Iterative Decoding for turbo codes turbo decoder Turbo Decoder wcdma sova Turbo Decoder satellite CS3630 convolutional encoder interleaving convolutional interleave CS3630TK
Text: efficient and high-performance solution for the turbo decoder specifications supplied by the W-CDMA and , CS3630 TM Turbo Decoder Virtual Components for the Converging World The CS3630 Turbo , Input De-puncture De-interleaver Interleaver Decoder 2 Decoder 1 Figure 1: A Turbo Decoder Overview Diagram FEATURES Supports full range of W-CDMA and CDMA2000 data block lengths , CS3630 Turbo Decoder TURBO CODES FOR ERROR CORRECTION generally operate over blocks of data, with


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PDF CS3630 CS3630 CDMA2000 DS3630v1 3GPP turbo decoder log-map sova Iterative Decoding for turbo codes turbo decoder Turbo Decoder wcdma sova Turbo Decoder satellite convolutional encoder interleaving convolutional interleave CS3630TK
2000 - FIR filter design using cordic algorithm

Abstract: EPF20K Scrambling code rAised cosine FILTER QPSK qam trans Modulator block diagram CORDIC QAM modulation rake complex qpsk Modulator umts turbo encoder circuit MPEG4 schematic
Text: function, which meets the WCDMA standard. See Figure 2 for a block diagram. The turbo encoder uses 3,000 , Deinterleaver Viterbi Decoder Data Turbo Decoder ADC Channelizer Error Indication CRC I , Viterbi decoder is used to decode signals encoded using convolutional encoders; the turbo decoder is used with the turbo encoder. Viterbi Decoder The Viterbi algorithm is the optimal algorithm to decode , length. W-CDMA requires a decoder with a constraint length of 9, which poses an implementation challenge


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PDF IMT-2000, FIR filter design using cordic algorithm EPF20K Scrambling code rAised cosine FILTER QPSK qam trans Modulator block diagram CORDIC QAM modulation rake complex qpsk Modulator umts turbo encoder circuit MPEG4 schematic
2002 - turbo codes matlab simulation program

Abstract: turbo codes using vhdl 5 to 32 decoder using 3 to 8 decoder vhdl code turbo codes matlab code 3 to 8 line decoder vhdl IEEE format vhdl coding for error correction and detection vhdl codes for Return to Zero encoder vhdl coding for turbo code VHDL code for interleaver block in turbo code Puncturing vhdl
Text: . However, SOVA is sub-optimum and is currently not supported by the Altera Turbo Encoder/ Decoder MegaCore , Turbo Encoder/ Decoder MegaCore Function User Guide 101 Innovation Drive San Jose, CA 95134 , 1.1.2 rev 1 July 2002 Copyright Turbo Encoder/ Decoder MegaCore Function User Guide SUPPLY OF , ® Turbo Encoder/ Decoder MegaCore® function. f Go to the following sources for more information , this release. Refer to the Turbo Encoder/ Decoder MegaCore function readme file for late-breaking


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PDF EP20K400 EP20K200 EP20K300E turbo codes matlab simulation program turbo codes using vhdl 5 to 32 decoder using 3 to 8 decoder vhdl code turbo codes matlab code 3 to 8 line decoder vhdl IEEE format vhdl coding for error correction and detection vhdl codes for Return to Zero encoder vhdl coding for turbo code VHDL code for interleaver block in turbo code Puncturing vhdl
2000 - turbo codes matlab simulation program

Abstract: Turbo code Decoder posteriori TURBO Encoder/Decoder source coding turbo encoder circuit sova 5 to 32 decoder using 3 to 8 decoder vhdl code turbo decoder turbo codes matlab code vhdl code for bit interleaver Interleaver-De-interleaver
Text: Turbo Encoder/ Decoder MegaCore Function User Guide Version 1.1 August 2000 Turbo Encoder , provides comprehensive information about the Altera® turbo encoder/ decoder MegaCoreTM function. How , encoder/ decoder is shown in Figure 1. Figure 1. Turbo Encoder/ Decoder Block Diagram Turbo Encoder Turbo Decoder Information bits Transmitted information bits Interleaver Encoder 1 Encoder 2 , Decoder 2 9 Specifications- Encoder User Guide Specifications-Encoder Turbo Encoder


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PDF -UG-TURBO-01 turbo codes matlab simulation program Turbo code Decoder posteriori TURBO Encoder/Decoder source coding turbo encoder circuit sova 5 to 32 decoder using 3 to 8 decoder vhdl code turbo decoder turbo codes matlab code vhdl code for bit interleaver Interleaver-De-interleaver
2000 - sim 300 processor gsm modem datasheet

Abstract: sim 300 processor datasheet for gsm modem sim 300 processor gsm modem sim 300 processor for gsm modem sim 300 gsm PCI5110 umts turbo encoder circuit vocoder gsm amr UMTS baseband serial port gsm modem
Text: Interface WCDMA RAKE Receiver Diagnostic Monitor WCDMA Searcher WCDMA Channel Decoder GSM , Keypad Interface GSM DSP Control AMR Voice Decoder Channel Decoder Co-Processor WCDMA Channel , CDMA GSM TDMA UMTS CDMA GSM TDMA UMTS CDMA GSM TDMA UMTS PCI5110 UMTS ( WCDMA )/ GSM/GPRS PCI5110 UMTS( WCDMA )/GSM/GPRS Digital Baseband Processor PCI5110 GENERAL FEATURES Supports 3GPP/UMTS ( WCDMA ) Frequency Division Duplex (FDD) operating mode Supports Circuit Switched Voice, Packet-Switched


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PDF PCI5110 PCI5110 280-ball sim 300 processor gsm modem datasheet sim 300 processor datasheet for gsm modem sim 300 processor gsm modem sim 300 processor for gsm modem sim 300 gsm umts turbo encoder circuit vocoder gsm amr UMTS baseband serial port gsm modem
2005 - ST140

Abstract: lms ARM ARM926 V510AT Basic ARM 7500 block diagram Convolutional decoder UART Program Examples ARM
Text: /s - 29000 Mops - 7500 Mips Convolutional Decoder Engine: ­ 256 x 12.2 kpbs AMR voice users ­ Programmable Code Parameters to support multi-standards ( W-CDMA , TD-SCDMA, CDMA2000 and EDGE) Turbo Decoder , Periph COPRO DMA Periph 1 x UARTs Turbo Decoder Engine 2 x Ethernet MAC Convolutional , specific IP blocks such as a Turbo Decoder Engine, Convolution Decoder Engine, UTOPIA Interface , Peripherals including Multi-Channel Serial Ports, UTOPIA interface, Turbo Decoder Engine and Convolutional


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PDF V510AT ST140 600MHz ARM926 300MHz 40-bit) CDMA2000 CDMA2000) lms ARM ARM926 V510AT Basic ARM 7500 block diagram Convolutional decoder UART Program Examples ARM
2005 - ARM926

Abstract: STW51000 CDMA 1xEV-DO Rev. A ST140 STW51000AT turbo decoder convolutional convolution interleaver lms ARM
Text: MMacs/s - 29000 Mops - 7500 Mips Convolutional Decoder Engine: ­ 256 x 12.2 kpbs AMR voice users ­ Programmable Code Parameters to support multi-standards ( W-CDMA , TD-SCDMA, CDMA2000 and EDGE) Turbo Decoder , Periph COPRO DMA Periph 1 x UARTs Turbo Decoder Engine 2 x Ethernet MAC Convolutional , specific IP blocks such as a Turbo Decoder Engine, Convolution Decoder Engine, UTOPIA Interface , Peripherals including Multi-Channel Serial Ports, UTOPIA interface, Turbo Decoder Engine and Convolutional


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PDF STW51000 ST140 600MHz ARM926 300MHz 40-bit) CDMA2000 CDMA2000) STW51000 CDMA 1xEV-DO Rev. A STW51000AT turbo decoder convolutional convolution interleaver lms ARM
2005 - Not Available

Abstract: No abstract text available
Text: 7500 Mips Convolutional Decoder Engine: – 256 x 12.2 kpbs AMR voice users – Programmable Code Parameters to support multi-standards ( W-CDMA , TD-SCDMA, CDMA2000 and EDGE) Turbo Decoder Engine: – 28 x 384 kbps (8 iterations) – Programmable Code Parameters to support multi-standards ( W-CDMA , Cross Bar ² Core Periph COPRO DMA Periph 1 x UARTs Turbo Decoder Engine 2 x , as well as application specific IP blocks such as a Turbo Decoder Engine, Convolution Decoder Engine


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PDF STW51000AT ST140 600MHz ARM926 300MHz 40-bit) CDMA2000 CDMA2000)
2002 - Convolutional Encoder

Abstract: CS3530 Convolutional Block Interleaver time interleaver "Single-Port RAM" turbo encoder circuit
Text: of products 1 CS3530 Turbo Encoder TURBO CODES FOR ERROR CORRECTION encoder or decoder , overall turbo encoding rate is fixed at 1/3. An exception occurs when the W-CDMA turbo encoder produces , W-CDMA . Since 3G turbo coding forces a block structure on the convolutional code, a series of three , = W-CDMA 7 CS3530 Turbo Encoder Table 3: CS3530 Configuration Register Map Address , CS3530 TM Turbo Encoder Virtual Components for the Converging World The CS3530 Turbo


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PDF CS3530 CS3530 CDMA2000 DS3530 Convolutional Encoder Convolutional Block Interleaver time interleaver "Single-Port RAM" turbo encoder circuit
2003 - turbo decoder

Abstract: 3GPP turbo decoder log-map 5 to 32 decoder circuit 5 to 32 decoder block diagram of 2 to 4 decoder LFX1200B-04FE680C turbo encoder circuit Block Interleaver time interleaver DECODER MEANS
Text: Turbo Decoder July 2003 IP Data Sheet Features General Description Compliant with , Buffering Bit Error Rate of 10-6 (at 1.5 dB Eb/No SNR) Lattice provides a Turbo Decoder IP core that is , correction solution. Functional Block Diagram Figure 1. Turbo Decoder Conceptual Functional Block Diagram , ip1020_02 Lattice Semiconductor Turbo Decoder Block Diagram Figure 2. Turbo Decoder I/O Block , Turbo Decoder interleaver_init block_size iterations clk rate Note: Additional I/O signals


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PDF 30MHz, LFX1200B-04FE680C turbo decoder 3GPP turbo decoder log-map 5 to 32 decoder circuit 5 to 32 decoder block diagram of 2 to 4 decoder turbo encoder circuit Block Interleaver time interleaver DECODER MEANS
2005 - matlab codes for wcdma rake receiver

Abstract: 3G HSDPA circuits diagram HSDPA matlab wcdma simulink turbo encoder circuit, VHDL code mimo model simulink 3g hsdpa signal antenna Diagram hsdpa matlab codes umts turbo encoder circuit 3G HSDPA cell capacity planning
Text: Error-Correcting Coding and Decoding Turbo Codes," IEEE Proc 1993 Int Conf. Comm., pp1064-1070. 3. WCDMA , W-CDMA base station, along with the associated implementation challenges faced by W-CDMA equipment , of an optimal solution to meet the extensive processing requirements of the W-CDMA specifications while retaining flexibility and minimizing the overall cost. Introduction The W-CDMA system is one , W-CDMA system is the 3G base station, shown in Figure 1. Antenna Baseband Processing Network


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PDF XAPP726 pp1064-1070. matlab codes for wcdma rake receiver 3G HSDPA circuits diagram HSDPA matlab wcdma simulink turbo encoder circuit, VHDL code mimo model simulink 3g hsdpa signal antenna Diagram hsdpa matlab codes umts turbo encoder circuit 3G HSDPA cell capacity planning
2001 - SPRA680

Abstract: umts turbo encoder MULTICHANNEL receiver probability ovsf mip 8360 rake complex umts turbo encoder circuit Scrambling code
Text: turbo decoder data Output turbo decoder errors Communication through these buffers is controlled via , data from data channel HPI_TurboErrors: Number of errors that the turbo decoder has corrected. 3.8 , Application Report SPRA680 - July 2000 Implementation of a WCDMA Rake Receiver on a TMS320C62x , paths in a wideband code division multiple access ( WCDMA ) digital signal processor (DSP) radio. Overall , . . . . . . . 24 9 Turbo Decoding Error Correction . . . . . . . . . . . . . . . . . . . . . . . .


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PDF SPRA680 TMS320C62x 100-MHz umts turbo encoder MULTICHANNEL receiver probability ovsf mip 8360 rake complex umts turbo encoder circuit Scrambling code
2000 - SPRA680

Abstract: TMS320C62x umts turbo encoder wcdma rake receiver Scrambling code MIP 0255 turbo decoder cdma receiver probability MS2871 UMTS receiver
Text: 020145e0/TurboErrors C0/192 8/8 Output array of turbo decoder data Output turbo decoder errors , data from data channel HPI_TurboErrors: Number of errors that the turbo decoder has corrected. 3.8 , Application Report SPRA680 - July 2000 Implementation of a WCDMA Rake Receiver on a , the paths in a wideband code division multiple access ( WCDMA ) digital signal processor (DSP) radio , . . . . . . . . . . . . . . . . . . . 24 9 Turbo Decoding Error Correction . . . . . . . . . . . .


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PDF SPRA680 TMS320C62xTM 100-MHz TMS320C62x umts turbo encoder wcdma rake receiver Scrambling code MIP 0255 turbo decoder cdma receiver probability MS2871 UMTS receiver
2004 - rsc Encoder

Abstract: convolutional encoder interleaving Turbo Encoder interleaver Block Interleaver convolutional ccsds LFX500B-04F516C LFEC20E-5F672C pin diagram encoder
Text: 's Turbo Encoder core is created in conjunction with the Turbo Decoder core to provide users with a state , the encoded stream. At the decoder , knowledge of this pattern enables de-puncturing. The Turbo , Turbo Encoder September 2004 IP Data Sheet Features General Description Fully Compatible with the Following Standards Turbo coding is an advanced error correction technique widely used in the communications industry. Turbo encoders and decoders are key elements in today


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PDF S0002-A LFEC20E-5F672C rsc Encoder convolutional encoder interleaving Turbo Encoder interleaver Block Interleaver convolutional ccsds LFX500B-04F516C pin diagram encoder
vhdl code for turbo

Abstract: Turbo Decoder 3GPP turbo decoder log-map turbo encoder circuit vhdl code for interleaver 5 to 32 decoder using 3 to 8 decoder verilog ccsds
Text: ispLever CORE TM Turbo Decoder User's Guide July 2003 ipug14_02 Lattice Semiconductor Turbo Decoder User's Guide Introduction Lattice's Turbo Decoder core provides an ideal , application rather than the Turbo Decoder , resulting in a faster time to market. Turbo coding is an advanced error correction technique widely used in the communications industry. The Turbo Decoder IP Core from Lattice is compliant with two different standards: 3GPP and CCSDS. Lattice's Turbo Decoder core was


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PDF ipug14 1-800-LATTICE vhdl code for turbo Turbo Decoder 3GPP turbo decoder log-map turbo encoder circuit vhdl code for interleaver 5 to 32 decoder using 3 to 8 decoder verilog ccsds
2000 - altera CORDIC ip

Abstract: rAised cosine rAised cosine FILTER CORDIC altera square root rake cyclic redundancy code IMT-2000 ovsf turbo 1998 code for cordic
Text: Devices & IP Functions Turbo Turbo W-CDMA s s s (PCCC Parallel Concatenated Convolutional Code) : 40 5,114 : =1/ 3 =1/ 2 W-CDMA Turbo MegaCore Turbo APEX 20K 3,000 , W-CDMA System with Altera Devices & IP Functions Viterbi Turbo Viterbi Turbo Turbo , : Implementing a W-CDMA System with Altera Devices & IP Functions Turbo Turbo Turbo Turbo MegaCore , IP W-CDMA 2000 9 ver. 1.0 Application Note 129


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PDF IMT-2000 -AN-129-01/J 03-3340-9480FAX. altera CORDIC ip rAised cosine rAised cosine FILTER CORDIC altera square root rake cyclic redundancy code IMT-2000 ovsf turbo 1998 code for cordic
2010 - MSC8157

Abstract: MSC8158 FFT Application note freescale UMTS baseband SC3850 CPRI umts uplink LTE baseband chip scrambling code uplink
Text: , mainstream adoption of next-generation hardware acceleration for Turbo and Viterbi for high-speed , Second-generation multi-accelerator platform engine for baseband (MAPLE-B2) Highly flexible, programmable Turbo and Viterbi decoder supports configurable decoding parameters. It can perform up to 260 Mbps of Turbo decoding in UMTS and Viterbi decoding and up to 200 Mbps for K = 7 tail biting FFT/iFFT , . Whether the application targets a WCDMA or TD-SCDMA or system, the development environment gives


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PDF MSC8158/MSC8158E MSC8158/MSC8158E MSC8158E SC3850 MSC8157 MSC8158FS MSC8157 MSC8158 FFT Application note freescale UMTS baseband CPRI umts uplink LTE baseband chip scrambling code uplink
2003 - 1/3 Convolutional encoder

Abstract: rsc Encoder pin diagram encoder turbo encoder circuit circuit diagram of encoder Turbo Decoder LFX500B-04F516C ip1018 convolutional encoder interleaving encoder source code
Text: 's Turbo Encoder core is created in conjunction with the Turbo Decoder core to provide users with a state , encoded stream. At the decoder , knowledge of this pattern enables de-puncturing. The Turbo Encoder IP , Turbo Encoder July 2003 IP Data Sheet Features General Description Fully Compatible with the Following Standards Turbo coding is an advanced error correction technique widely used in the communications industry. Turbo encoders and decoders are key elements in today's communication


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PDF S0002-A 61MHz 64MHz 93MHz LFX500B-04F516C 1/3 Convolutional encoder rsc Encoder pin diagram encoder turbo encoder circuit circuit diagram of encoder Turbo Decoder ip1018 convolutional encoder interleaving encoder source code
Not Available

Abstract: No abstract text available
Text: ispLever CORE TM Turbo Decoder User’s Guide November 2008 ipug14_04.4 Lattice Semiconductor Turbo Decoder User’s Guide Introduction Lattice’s Turbo Decoder core provides an ideal , application rather than the Turbo Decoder , resulting in a faster time to market. Turbo coding is an advanced error correction technique widely used in the communications industry. The Turbo Decoder IP Core from Lattice is compliant with three different standards: 3GPP, 3GPP2 and CCSDS. Lattice’s Turbo Decoder


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PDF ipug14
2006 - AE 2576

Abstract: TMS320TCI648x 3GPP turbo decoder log-map C6416 0x00050005
Text: . ABSTRACT Turbo decoder lies at the heart of all of the third-generation (3G) wireless standards. The turbo coprocessors (TCP2) are programmable peripherals used to decode turbo codes. It is , implementations of Turbo decoder , which can be selected on a frame-by-frame basis. The max*-log-MAP should get a , Time . 17 List of Tables 1 2 3 Typical Channel Density for WCDMA , transmitted. Turbo coding techniques are used in all third-generation (3G) wireless standards. The turbo


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PDF TMS320TCI648x AE 2576 3GPP turbo decoder log-map C6416 0x00050005
2010 - lte RF Transceiver

Abstract: lte RF Transceiver MIMO 2x2 design ideas lte turbo encoder Turbo Decoder LTE base station lte WiMAX transceivers Turbo Decoder JESD204A "Zadoff-Chu sequence"
Text: Symbol mapper/demapper LTE channel card · 3GPP Turbo encoder · 3GPP Turbo decoder · Discrete , , Long-Term Evolution (LTE), and W-CDMA . They are also highly optimized for Altera® silicon. With these , · Viterbi · Turbo cores · Low-density parity check (LDPC) cores · Scalable orthogonal frequency


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PDF SS-01062-4 lte RF Transceiver lte RF Transceiver MIMO 2x2 design ideas lte turbo encoder Turbo Decoder LTE base station lte WiMAX transceivers Turbo Decoder JESD204A "Zadoff-Chu sequence"
2010 - MSC8157

Abstract: LTE baseband chip CPRI lte baseband mbps channel equalization MIMO SC3850 3GPP LTE MIMO Decoder MSC8157E channel equalization MIMO despreading Turbo Decoder wcdma viterbi
Text: ) Highly flexible, programmable Turbo and Viterbi decoder supports configurable decoding parameters. It can perform up to 440 Mbps of Turbo decoding for 3GLTE. Viterbi decoding at up to 200 Mbps. Turbo , Turbo and Viterbi channel decoding, Turbo encoding and rate matching, MIMO MMSE, IRC and ML , systems. Whether the application targets a 3G-LTE, WCDMA , or WiMAX system, the development environment


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PDF MSC8157/MSC8157E MSC8157/MSC8157E SC3850 MSC8157/ MSC8157E MSC8157FS MSC8157 LTE baseband chip CPRI lte baseband mbps channel equalization MIMO 3GPP LTE MIMO Decoder channel equalization MIMO despreading Turbo Decoder wcdma viterbi
2012 - PSC9132

Abstract: JESD207/ADI BSC9130/31 BSC9132
Text: ) deploying Turbo and Viterbi decoding algorithms in LTE/LTE-A and WCDMA standards. Other functions such as , encoding processing: Used for FEC deploying turbo encoding algorithms in LTE/ LTE-A and WCDMA standards , latency • MAPLE-B baseband acceleration platform • Turbo /Viterbi decoder supporting LTE , CRC Attach PHY Layer Downlink Data Path Processing Functions Turbo Encoding Rate Matching , RateDematching, Transport CRC HARQ Block Check Combining, CRC Turbo Decoding freescale.com QorIQ


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2009 - TMS320TCI6485

Abstract: gsm mobile sniffer Turbo Decoder wcdma viterbi 2G base station antenna product cognitive radio TMS320TCI6489 TCI6489 3G HSDPA circuits diagram TMS320C64 msc in gsm
Text: coprocessor (RAC) Optimized for wireless baseband applications with turbo and Viterbi decoder , coprocessors: · Viterbi decoder coprocessor 2 (VCP2) · Turbo decoder coprocessor 2 (TCP2) · Receiver , , supporting eight users on a single WCDMA carrier. It is also capable of running both PHY and higher layer software functions on each of the two cores, and includes software for WCDMA that supports all Layer 1, 2 , single WCDMA carrier. With a broad selection of available analog RF components, the TCI6489 enterprise


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PDF TMS320TCI6485 TMS320TCI6489 TMS320TCI6489 TCI6485 TCI6489 TCI6485 gsm mobile sniffer Turbo Decoder wcdma viterbi 2G base station antenna product cognitive radio 3G HSDPA circuits diagram TMS320C64 msc in gsm
vhdl code for turbo

Abstract: rsc Encoder turbo encoder circuit vhdl code for interleaver interleaver convolutional encoder interleaving MOUSE ENCODER output block interleaver in modelsim vhdl code for block interleaver ispLEVER project Navigator
Text: 's Turbo Encoder core is created in conjunction with the Turbo Decoder core to provide users with a state , decoder state initialization. Figures 3, 4 and 5 illustrate the timing specifications of the Turbo , ispLever CORE TM Turbo Encoder User's Guide July 2003 ipug08_02 Lattice Semiconductor Turbo Encoder User's Guide Introduction This document contains technical information about the Lattice Turbo Encoder IP core. Turbo coding is an advanced error correction technique widely used


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PDF ipug08 S0002-A 1-800-LATTICE vhdl code for turbo rsc Encoder turbo encoder circuit vhdl code for interleaver interleaver convolutional encoder interleaving MOUSE ENCODER output block interleaver in modelsim vhdl code for block interleaver ispLEVER project Navigator
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