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2000 - transistor 5-2736

Abstract: 5-2736 pin diagram of ic 7495 pin diagram of ic 7495 A pin diagram of ic 7495 generator data sheet ic 7495 EN10 LU3X54FTL MR30 MR31
Text: controlled by autonegotiation. The signals RX_CLK10, RXD_10, TX_CLK10 , and TXD_10 (all from ports A, B, C , Mbits/s serial interface) signals are still routed to port B (RX_CLK10, RXD_10, TX_CLK10 , and TXD_10). , ) Block Diagrams Smart Bused MII Mode RX_CLK10 RX_CLK10 RXD_10 RXD_10 TX_CLK10 TXD_10 TX_CLK10 TXD_10 CRS_10/100 4 RX_EN10/100 TX_EN10/100 4 COL_10/100 SECURITY10/100 10/100 , Bused MII Mode RX_CLK10 RX_CLK10 RXD_10 RXD_10 TX_CLK10 TXD_10 10 Mbits/s REPEATER


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PDF LU3X54FTL 10Base-T/100Base-TX/FX LU3X54FTL 10Base-T, 100Base-TX, 100Base-FX 100Base-FX. transistor 5-2736 5-2736 pin diagram of ic 7495 pin diagram of ic 7495 A pin diagram of ic 7495 generator data sheet ic 7495 EN10 MR30 MR31
1999 - Not Available

Abstract: No abstract text available
Text: RX_CLK10, RXD_10, TX_CLK10 , and TXD_10 (all from ports A, B, C, and D) are internally bused together and , (RX_CLK10, RXD_10, TX_CLK10 , and TXD_10). The 100 Mbits/s signals are still routed to port A (TX_CLK25, TXD , _10 TX_CLK10 TXD_10 CRS_10/100 RX_EN10/100 TX_EN10/100 COL_10/100 SECURITY10/100 10/100 Mbits/s SMART REPEATER , _10 TX_CLK10 TXD_10 CRS_100 RX_EN100 TX_EN100 COL_100 TX_EN10/SECURITY TX_CLK25 TXD_100[3:0] TX_ER RX_CLK25 RXD , ) Separate Bused MII Mode 10 Mbits/s REPEATER RX_CLK10 RXD_10 TX_CLK10 TXD_10 COL_10 CRS_10 RX_EN10


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PDF LU3X54FT 10Base-T/100Base-TX/FX 10Base-T, 100Base-TX, 100Base-FX 100Base-FX. DS99-246LAN
2000 - 5-2736

Abstract: data sheet ic 7495 EN10 LU3X54FT MR30 MR31
Text: ), TX_EN10 (4), and TX_EN100(4). The signals RX_CLK10, RXD_10, TX_CLK10 , and TXD_10 (all from ports A, B , -pin 10 Mbits/s serial interface) signals are still routed to port B (RX_CLK10, RXD_10, TX_CLK10 , and TXD , Smart Bused MII Mode RX_CLK10 RX_CLK10 RXD_10 RXD_10 TX_CLK10 TXD_10 TX_CLK10 TXD , ) Separate Bused MII Mode RX_CLK10 RXD_10 TX_CLK10 TXD_10 COL_10 CRS_10 RX_EN10 TX_EN10 10 Mbits , MDIO RX_CLK10 RXD_10 TX_CLK10 TXD_10 COL_10 CRS_10 RX_EN10 TX_EN10 CRS_100 TX_EN100


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PDF LU3X54FT 10Base-T/100Base-TX/FX LU3X54FT 10Base-T, 100Base-TX, 100Base-FX 100Base-FX. DS99-246LAN 5-2736 data sheet ic 7495 EN10 MR30 MR31
EF802

Abstract: pf30n Nec mr31
Text: ), and TX_EN 100(4). The signals RX_CLK10, RXD_10, TX_CLK10 , and TXD_10 (all from ports A, B, C, and D , , RXD_10, TX_CLK10 , and TXD_10). The 100 Mbits/s signals are still routed to port A (TX_CLK25, TXD_100[3 , _10 TX_CLK10 TXD_10 CRS_10/100 RX_EN10/100 TX_EN10/100 COL_10/100 SECURITY10/100 10/100 Mbits/s SMART REPEATER , _10 TX_CLK10 TXD_10 CRS_100 RX_EN100 TX_EN100 TX_EN10/SECURITY -rv r i i/oc TXD_100[3:0] TX_ER RX_CLK25 RXD , ) Separate Bused Mil Mode RX_CLK10 RXD_10 TX_CLK10 10 Mbits/s REPEATER TXD_10 COL 10 CRS_10 RX_EN10


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PDF LU3X54FT 10Base-T/100Base-TX/FX 10Base-T /EEE802 100Base-FX DS98-132LAN DS98-038LAN) EF802 pf30n Nec mr31
mr31 nec

Abstract: NEC MR31 CQL10
Text: ), RX_EN10(4), RX_EN100(4), TX_EN10 (4), and TX_EN 100(4). The signals RX_CLK10, RXD_10, TX_CLK10 , and TXD , to port B (RX_CLK10, RXD_10, TX_CLK10 , and TXD_10). The 100 Mbits/s signals are still routed to port , Mil Mode RX_CLK10 RXD_10 TX_CLK10 TXD 10 CRS_10/100 RX_EN10/100 TX_EN10/100 CQL_10/100 SECURITY10/100 10/100 Mbits/s SM ART REPEATER Í/ 4/ C RX_CLK10 RXD_10 TX_CLK10 TXD_10 CRS_100 RX_EN100 , _10 TX_CLK10 TXD_10 COL_10 CRS_10 RX_EN10 TX_EN10 : CRS 100 TX EN100 TX CLK25 TXD_100[3:0] TX ER 100


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PDF LU3X54FT 10Base-T/100Base-TX/FX 10Base-T, 100Base-TX, 100Base-FX 100Base-FX. 10Base-T mr31 nec NEC MR31 CQL10
Not Available

Abstract: No abstract text available
Text: RX_CLK10, RXD_10, TX_CLK10 , and TXD_10 (all from ports A, B, C, and D) are internally bused together and , still routed to port B (RX_CLK10, RXD_10, TX_CLK10 , and TXD_10). The 100 Mbits/s signals are still , -TX Description (continued) Smart Bused Mode Block Diagram RX_CLK10 RXD 10 TX_CLK10 TXD 10 CRS_10/100 , MDC MDIO t Í/ / * 4/ 4, 'k/ RX CLK10 RXD_10 TX_CLK10 TXD. 10 CRS_100 RX_EN100 TX_EN100 COL_100 1A , _10 TX_CLK10 TXD_10 COL_10 CRS_10 RX_EN10 TX_EN10 4/ r 'a, / " 100 Mbits/s REPEATER CRS_100 TX


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PDF LU3X54 10Base-T/1 10Base-T LU3M38 EE802 DS98-038LAN DS97-241LAN)
2003 - Not Available

Abstract: No abstract text available
Text: ] XCK10 LDIN10[0:9] TXCLK10 CV00, COMDET00, WDSYNC00 RBC00[0:1] LDOUT00[0:9] XCK00 LDIN00[0:9] TXCLK00


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PDF SDP3G06 C--70 PB03-047SRDS
2003 - XCK12

Abstract: SDP3G08 XCK11
Text: , WDSYNC10 2 HDINP10 RBC10[0:1] 10 2 LDOUT10[0:9] XCK10 LDIN10[0:9] TXCLK10 HDINN10


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PDF SDP3G08 8b/10b X3T11; or12-4106) PB03-051SRDS XCK12 XCK11
74hc04

Abstract: tms 374 74HC04 NOT GATE datasheet ddr5 74HC04 datasheet DMO10 TX3036 dmo2 IDC18 DMO11
Text: _10 E4 C3 TXCLK_10 TPOS_10 TXOUT9 SMB F4 TTIP_10 TCLK_10 TNEG_10 TX3036 15


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PDF 74HC04 TX3036 XRT75R12 100uF TANT01 XRT75R12 74hc04 tms 374 74HC04 NOT GATE datasheet ddr5 74HC04 datasheet DMO10 TX3036 dmo2 IDC18 DMO11
Not Available

Abstract: No abstract text available
Text: RESET TEN10 LINKST ACTLED VDD LINKOK TLS0 TLS1 TLS2/TDATA GND TXCLK10 RLS0 RLS1 RLS2 RLS3 RXCLK100 GND , ]/ TDATA TXCLK10 BA[14:0] BDO o PHY I PHY SRAM SRAM BootROM EEPROM SRAM BootROM EEPROM SRAM , continuous. Clock 11.25. This is an 11.25 Mhz clock iCLK1/4). This clock is used as an input to TXCLK10 when , . Clock Osc. TXCLK10 o RESET TESTOE TESTSEL VGSEL I I I General General General General o , (continued) Transceiver Interfaces (continued) ATT2MD01 ÄTT2X01 TLS[2:0] RXCLK TLS[2:0) RXCLK100 TXCLK100


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PDF ATT2MD01 100VG-AnyLAN 10Base-T ATT2X01 DS94-032LA
T7213

Abstract: No abstract text available
Text: TLS2/TDATA GND TXCLK10 193 194 195 196 BD1 BD2 BD3 BD4 41 42 43 44 45 46 47 48 , . TXCLK10 I PHY Transm it C lock 10 Mbit. This is the transmit clock from the 10 Mbits/s , clock (±100 ppm), 45— 55% duty cycle. It must be continuous. CLK1125 0 TXCLK10 Clock 11.25. This is an 11.25 MHz clock (CLK1/4). This clock is used as an input to TXCLK10 when in 100 Mbits


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PDF ATT2MD01 100VG/1 100VGAnyLAN 10Base-T ATT2X01 100VG-AnyLAN 1995AT DS94-032LAN 005002ki T7213
Not Available

Abstract: No abstract text available
Text: O L _ 1 0 0 [B ]/C O L _ 1 0 /1 00 [B ] I C R S _ 1 0 0 [B ]/C R S _ 1 0 /1 0 0 [B ] i TX_CLK10 I , 10 MHz clock output in 10 Mbits/s serial mode. TX_CLK10 provides timing reference for the transfer of the TX_EN10 and TXD_10 signals that are sampled on the rising edge of TX_CLK10 . When operating , synchronous with TX_CLK10 . 120 119 117 116 TXD 100[3:0] I Shared Transmit Data. 4-bit parallel


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PDF LU3X54FT 10Base-T/100Base-TX/FX 100Base-FX 10Base-T 208-Pin
Not Available

Abstract: No abstract text available
Text: LK10 RX_CLK10 R XC LK25 RXD_10 RXD_100 RXDV RXER TXD _10 TXD _100 TX_ER TXCLK25 TX_CLK10 RX_CLK10 R , Transmit Clock (10 MHz). 10 MHz clock output in 10 Mbits/s serial mode. TX_CLK10 provides timing reference for the transfer of the TX_EN10 and TXD_10 signals that are sampled on the rising edge of TX_CLK10 , Data. Serial data output that is synchronous to the falling edge of RX_CLK10. 148 TX_CLK10 O , input synchronous with TX_CLK10 . Shared Transmit Data. 4-bit parallel input synchronous with TX_CLK25


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PDF LU3X54FTL 10Base-T/100Base-TX/FX 3X54FTL 10Base-T, 100Base-TX, 100Base-FX 100Base-FX.
t7213

Abstract: 2MD12 bd8202 ATT2MD12 ATT2MD01 ATT2MD11 ATT2X01 paging Transceiver 1994
Text: GND 144 TXCLK10 145 RLS0 146 RLS1 147 RLS2 148 RLS3 149 RXCLK100 150 GND 151 RDO/COl 152 RD1 , transceiver. TXCLK10 I PHY Transmit Clock 10 Mbit. This is the transmit clock from the 10 Mbit transceiver , . This is a 30 MHz clock (±100 ppm), 45—55% duty cycle. It must be continuous. CLK1125 0 TXCLK10 Clock 11.25. This is an 11.25 MHz clock (CLK1/4). This clock is used as an input to TXCLK10 when in 100


OCR Scan
PDF ATT2MD11 10OVG-AnyLAN 100VG-AnyLAN 10Base-T ATT2X01 5-2196C1 ATT2MD11 208-Pin t7213 2MD12 bd8202 ATT2MD12 ATT2MD01 paging Transceiver 1994
Not Available

Abstract: No abstract text available
Text: /GPI1 TLS2/TDATA GND TXCLK10 RLS0 RLS1 RLS2 RLS3 RXCLK100 GND RDO/COL RD1/RXC RD2/RXD RD3 , . When VGSEL# is deasserted, this pin provides transmit data to a 10 Mbit transceiver. TXCLK10 I , continuous. CLK1125 0 TXCLK10 Clock 11.25. This is an 11.25 MHz clock (CLK1/4). This clock is used as an input to TXCLK10 when in 100 Mbits/s only mode to keep the 10 Mbit MAC run­ ning. RST


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PDF ATT2MD11 10OVG-AnyLAN 100VGAnyLAN ATT2X01 brT2MD11 100VG-AnyLAN 208-Pin S-2196C1 DDS002ti
2005 - Not Available

Abstract: No abstract text available
Text: _4 TxClk_5 TxClk_6 TxClk_7 TxClk_8 TxClk-9 TxClk_10 TxClk_11 TxClk_12 TxClk_13 TxClk_14 TxClk_15 TxClk


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PDF XRT59L921 XRT59L921 63-channel
2007 - XRT59L921

Abstract: schematic diagram pulse shaping TG26-1205 PE-65835 TU12 XRT59L921IB
Text: _0 TxClk_1 TxClk_2 TxClk_3 TxClk_4 TxClk_5 TxClk_6 TxClk_7 TxClk_8 TxClk-9 TxClk_10 TxClk


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PDF XRT59L921 XRT59L921 63-channel schematic diagram pulse shaping TG26-1205 PE-65835 TU12 XRT59L921IB
2007 - Not Available

Abstract: No abstract text available
Text: _5 TxClk_6 TxClk_7 TxClk_8 TxClk-9 TxClk_10 TxClk_11 TxClk_12 TxClk_13 TxClk_14 TxClk_15 TxClk_16 TxClk


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PDF XRT59L921 XRT59L921 63-channel
DD221

Abstract: IS002 att2md01 BD 535H T7213 EC T7213
Text: L1NKOK TLSO/GPOl TLS1/GPI1 TLS2/TDATA GND TXCLK10 RLS0 RLS1 RLS2 RLS3 RXCLK100 GND RDO/COL RD1/RXC RD2 , 0 PHY 4.2 Section TLS[1]/GPI1 O(I) PHY TLS[2]/TDATA 0 PHY TXCLK10 BA , .This is a 30 MHz clock (+100 ppm), 45%- 55% duty cycle. It must be continuous. TXCLK10 Clock 11.25. This


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PDF ATT2MD01 100VG/10Base-T 100VGAnyLAN 10Base-T ATT2X01 100VG-AnyLAN 0DE3111 0D50D2b DG23112 DD221 IS002 BD 535H T7213 EC T7213
1999 - KS32C50100

Abstract: hdlc 0x4024
Text: VSS TXD<2> TXD<3> TX_ERR/PCOMP_10M TX_CLK/ TXCLK_10M TX_EN/TXEN_10M MDIO LITTLE MDC VDD VSS , when a 10-Mbit/s PHY detects a collision. TX_CLK/ TXCLK_10M 46 I Transmit Clock/Transmit , , the PHY samples TXD[3:0] and TX_EN on the rising edge of TX_CLK. For data transfers, TXCLK_10M is , sampled on the rising edge of RX_CLK. To receive data, the TXCLK_10 M clock comes from the 10-Mbit/s PHY , . TXCA 1-14 I/O Type TX_CLK/ TXCLK_10M HDLC Channel A (9) Pin Counts COL/ COL


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PDF KS32C50100 16/32-bit KS32C50100, p0xE010 0xD014 0xE014 0x6000 hdlc 0x4024
1999 - STDM85

Abstract: KS32C5000AA hdlc KS32C5000A KS32C500
Text: /TxD_10M TxD1/LOOP_10M VDD VSS TxD2 TxD3 Tx_ERR/PCOMP_10M Tx_CLK/ TxCLK_10M Tx_ENT/TxEN , medium in MII mode. COL_10M is asserted when a 10-Mbit/s PHY detects a collision. TX_CLK/ TXCLK_10M , data transfers, TXCLK_10M is provided by the 10-Mbit/s PHY. TXD[3:0] TXD_10M LOOP_10M 39, 40 , receive data, the TXCLK_10 M clock comes from the 10-Mbit/s PHY. RXD[3:0]/ RXD_10M 30, 33, 34, 35 , detected/collision detected for 10M. TX_CLK/ TXCLK_10M 1 I pil Transmit data/transmit data


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PDF 2-5000A KS32C5000A KS32C5000AA 16/32-bit 60BSC STDM85 hdlc KS32C500
STDM85

Abstract: hdlc netarm 40 0x9014
Text: /COL_10M TxD1/TxD_10M TxD1/LOOP_10M VDD VSS TxD2 TxD3 Tx_ERR/PCOMP_10M Tx_CLK/ TxCLK_10M Tx_ENT , -Mbit/s PHY detects a collision. TX_CLK/ TXCLK_10M 46 I Transmit Clock/Transmit Clock for , samples TXD[3:0] and TX_EN on the rising edge of TX_CLK. For data transfers, TXCLK_10M is provided by the , sampled on the rising edge of RX_CLK. To receive data, the TXCLK_10 M clock comes from the 10-Mbit/s PHY , . 1 I pil Collision detected/collision detected for 10M. TX_CLK/ TXCLK_10M 1 I


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PDF KS32C5000 16/32-bit 60BSC 80BSC STDM85 hdlc netarm 40 0x9014
2003 - DMO11

Abstract: DMO10 0X00 GR-253 GR-499-CORE XRT73R12 XRT73R12IB em7 120 cc11r
Text: TxCLK10 TxCLK11 I E23 AB24 J22 AA23 G25 AA26 G2 AA1 J5 AA4 E4 AB3 TxPOS0 TxPOS1


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PDF XRT73R12 XRT73R12 DMO11 DMO10 0X00 GR-253 GR-499-CORE XRT73R12IB em7 120 cc11r
2003 - Not Available

Abstract: No abstract text available
Text: TxCLK10 TxCLK11 I E23 AB24 J22 AA23 G25 AA26 G2 AA1 J5 AA4 E4 AB3 TxPOS0 TxPOS1


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PDF XRT73R12 XRT73R12 XRT73Rs
2006 - DMO11

Abstract: DMO10 CR-148
Text: TxCLK9 TxCLK10 TxCLK11 TxPOS0 TxPOS1 TxPOS2 TxPOS3 TxPOS4 TxPOS5 TxPOS6 TxPOS7 TxPOS8 TxPOS9 TxPOS10


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PDF XRT73R12 XRT73R12 DMO11 DMO10 CR-148
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