The Datasheet Archive

Top Results (6)

Part Manufacturer Description Datasheet Download Buy Part
SN74LS00DBRE4 Texas Instruments LS SERIES, QUAD 2-INPUT NAND GATE, PDSO14, GREEN, PLASTIC, SSOP-14
SN74LS00NSR Texas Instruments Quad 2-input positive-NAND gates 14-SO 0 to 70
SN74LS00DR Texas Instruments Quad 2-input positive-NAND gates 14-SOIC 0 to 70
SN74LS00PSRG4 Texas Instruments Quad 2-input positive-NAND gates 8-SO 0 to 70
SN74LS00N-00 Texas Instruments LS SERIES, QUAD 2-INPUT NAND GATE, PDIP14
SN74LS00PS Texas Instruments LS SERIES, QUAD 2-INPUT NAND GATE, PDSO14, SO-8

TTL 74ls00 Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
2008 - TTL 74ls00

Abstract: AS5305 Rotary Encoder ES AS5306 72* hall IC 3 pole AS5304A AS5306A specification of 74ls00 74LS00 datasheet of ic 74ls00
Text: RL = 820 A/B/Index from AS5304/6 TTL 74LS00 CL = 20pF Figure 13: Typical digital load


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PDF AS5304/AS5306 AS5304 AS5306 TTL 74ls00 AS5305 Rotary Encoder ES AS5306 72* hall IC 3 pole AS5304A AS5306A specification of 74ls00 74LS00 datasheet of ic 74ls00
2008 - TTL 74LS00

Abstract: AS5306 magnetic strip encoder 74LS00 AS5304 JESD78 MO-153-AC 12mm Rotary Encoder switch rotary encoder 500 pulses per revolution quadrature
Text: See Figure 13 See Figure 13 Push/Pull mode VDD = 5V RL = 820 A/B/Index from AS5304/6 TTL 74LS00 CL = 20pF Figure 13: 9.5 Typical digital load CAO Analogue Output Buffer


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PDF AS5304 AS5306 AS5304/AS5306 AS5304) AS5306) TTL 74LS00 AS5306 magnetic strip encoder 74LS00 JESD78 MO-153-AC 12mm Rotary Encoder switch rotary encoder 500 pulses per revolution quadrature
2008 - TTL 74ls00

Abstract: AS5306 AS5306A AS5304A hall incremental optical encoder 5V ttl quadrature MO-153-AC AS5304 74LS00 EN Rotary optical encoder
Text: µs 39 VDD = 5V RL = 820 A/B/Index from AS5304/6 TTL 74LS00 CL = 20pF Figure 13


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PDF AS5304 AS5306 AS5304/AS5306 AS5304) AS5306) TTL 74ls00 AS5306 AS5306A AS5304A hall incremental optical encoder 5V ttl quadrature MO-153-AC 74LS00 EN Rotary optical encoder
1997 - Not Available

Abstract: No abstract text available
Text: Revision 1.9 am lc s on A te G nt st il VDD = 5V RL = 820 A/B/Index from AS5304/6 TTL 74LS00 CL =


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PDF AS5304 AS5306 32pole-pair AS5304/AS5306
1997 - Not Available

Abstract: No abstract text available
Text: /Index from AS5304/6 TTL 74LS00 C L = 20pF 6.4 CAO Analog Output Buffer Table 6. CAO Analog


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PDF AS5304/AS5306 AS5304 AS5306 AS5304/ AS5306
1996 - 74LS00

Abstract: 74LS00 TTL TTL 74ls00 3 to 8 line decoder using 8051 8051s microcontroller 8051s interfaces 74LS138 DATASHEET WR1100 74LS00 DATA HCTL1100
Text: two additional TTL chips. If your 8051 design I/O Port Interface is completely I/O based with no , AD1 AD2 AD3 AD4 AD5 AD6 AD7 1 2 OE CHIP 1\ CS CHIP 1\ 74LS00 5 4 6 Y0 Y1 Y2 , \ CS CHIP3\ OE CHIP4\ CS CHIP4\ 74LS138 10 9 8 74LS00 RESET 1 µF TO 8051 BUS 10 32 7 8 11 HCTL-1100 74LS00 74LS138 35 14 18 Vcc \ DENOTES AN ACTIVE LOW , 74LS00 13 12 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 6 74LS00 A8 A9 A10 PHA PHB PHC


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PDF HCTL-1100 M-015 HCTL-1100/8051 HCTL-1100 HCTL1100 HCTL1100. HCTL-1100s 74LS00 74LS00 TTL TTL 74ls00 3 to 8 line decoder using 8051 8051s microcontroller 8051s interfaces 74LS138 DATASHEET WR1100 74LS00 DATA
1996 - 74LS00

Abstract: 74LS00 TTL TTL 74LS00 74LS00 truth table 74LS00DC 74ls00 tphl tplh NAND 74LS00 74LS00 QUAD 2-INPUT NAND GATE motorola 74LS00 74LS00 DATA
Text: Output Current - Low 54 74 4.0 8.0 mA FAST AND LS TTL DATA 5-2 SN54/ 74LS00 DC , SN54/ 74LS00 QUAD 2-INPUT NAND GATE · ESD > 3500 Volts QUAD 2-INPUT NAND GATE LOW POWER SCHOTTKY VCC 14 13 12 11 10 9 8 J SUFFIX CERAMIC CASE 632-08 1 2 3 4 5 6 14 7 1 GND N SUFFIX PLASTIC CASE 646-06 14 1 14 1 D SUFFIX SOIC , ns tPHL Turn-On Delay, Input to Output 10 15 ns FAST AND LS TTL DATA 5-3


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PDF SN54/74LS00 51A-02 SN54LSXXJ SN74LSXXN SN74LSXXD 74LS00 74LS00 TTL TTL 74LS00 74LS00 truth table 74LS00DC 74ls00 tphl tplh NAND 74LS00 74LS00 QUAD 2-INPUT NAND GATE motorola 74LS00 74LS00 DATA
2007 - 3 to 8 line decoder using 8051

Abstract: 74LS00 74LS00 DATA TTL 74ls00 74LS00 TTL 74LS138 DATASHEET HCTL-1100 74LS138 HCTL-1100 M-015 HCTL-1100s
Text: sense to use the HCTL-1100 bus interface circuit. This approach requires only two additional TTL chips , AD2 AD3 AD4 AD5 AD6 AD7 1 2 OE CHIP 1\ CS CHIP 1\ 74LS00 5 4 6 Y0 Y1 Y2 Y3 , CHIP3\ OE CHIP4\ CS CHIP4\ 74LS138 10 9 8 74LS00 RESET 1 µF TO 8051 BUS 10 32 7 8 11 HCTL-1100 74LS00 74LS138 35 14 18 Vcc \ DENOTES AN ACTIVE LOW SIGNAL , 39 38 38 34 1 A 2 B 3 C 11 MC0 MC1 MC2 MC3 MC4 MC5 MC6 MC7 3 74LS00 13


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PDF HCTL-1100 M-015 HCTL-1100/8051 HCTL-1100 HCTL-1100. WR1100: CS1100 3 to 8 line decoder using 8051 74LS00 74LS00 DATA TTL 74ls00 74LS00 TTL 74LS138 DATASHEET 74LS138 HCTL-1100 M-015 HCTL-1100s
74LS00 TTL

Abstract: TTL 74LS00 74LS00 74ls00 NAND gate 74LS00 DATA 74LS00 QUAD 2-INPUT NAND GATE 74LS00 truth table NAND 74LS00 74LS00DC 74ls00 tphl tplh
Text: Output Current - Low 54 74 4.0 8.0 mA FAST AND LS TTL DATA 5-2 SN54/ 74LS00 DC , SN54/ 74LS00 QUAD 2-INPUT NAND GATE · ESD > 3500 Volts QUAD 2-INPUT NAND GATE LOW POWER SCHOTTKY VCC 14 13 12 11 10 9 8 J SUFFIX CERAMIC CASE 632-08 1 2 3 4 5 6 14 7 1 GND N SUFFIX PLASTIC CASE 646-06 14 1 14 1 D SUFFIX SOIC , AND LS TTL DATA 5-3 Motorola


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PDF SN54/74LS00 51A-02 SN54LSXXJ SN74LSXXN SN74LSXXD 74IOL 74LS00 TTL TTL 74LS00 74LS00 74ls00 NAND gate 74LS00 DATA 74LS00 QUAD 2-INPUT NAND GATE 74LS00 truth table NAND 74LS00 74LS00DC 74ls00 tphl tplh
74LS00 TTL

Abstract: 74LS00 truth table IC TTL 74LS00 74LS00 74LS00 QUAD 2-INPUT NAND GATE TTL 74ls00 74LS00DC motorola 74LS00 74ls00 NAND gate 74LS00 gate
Text: Output Current - High Output Current - Low mA mA FAST AND LS TTL DATA 5-2 SN54/ 74LS00 DC , MOTOROLA SN54/ 74LS00 QUAD 2-INPUT NAND GATE · ESD > 3500 Volts QUAD 2-INPUT NAND GATE fn l [ïïl fïïl [Til fïïl ITI 171 J SUFFIX CERAMIC CASE 632-08 VCC LOW POWER SCHOTTKY Lü Ll I Ll I L±l Ll I Ll I LzJ GND N SUFFIX ,r p îïï , 'S :. D SUFFIX SOIC CASE 751A-02 5 , Conditions Vcc = 5 0 V C[_= 15 pF 5 FAST AND LS TTL DATA 5-3


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PDF SN54/74LS00 51A-02 SN54LSXXJ SN74LSXXN SN74LSXXD SN54/74LS00 74LS00 TTL 74LS00 truth table IC TTL 74LS00 74LS00 74LS00 QUAD 2-INPUT NAND GATE TTL 74ls00 74LS00DC motorola 74LS00 74ls00 NAND gate 74LS00 gate
t74ls157

Abstract: 74LS00E 74LS00 fan out T74LS74 74LS00 74LS00 QUAD 2-INPUT NAND GATE 74LS00 nand gate 74ls00 series T74LS367 NAND 74LS00
Text: LOW POWER SCHOTTKY TTL -54/74 LS SERIES DESIGN CONSIDERATIONS SUPPLY VOLTAGE — +5V ± 10% T54 , , VIH 2.0V, Vol 0.5V, VOH 2.7V T74 SERIES INPUT LOADING — THE 74LS00 INPUT LOADING IS Iil 0.36mA (LOW INPUT) AND I IH 20MA (HIGH INPUT) OUTPUT DRIVE — THE 74LS00 OUTPUT DRIVE IS Iol 8.0mA (SINK) AND I oh , DEVICES WITHIN THE FAMILY AND IS NORMALIZED AROUND THE INPUT REQUIREMENTS OF THE 74LS00 .E.G. THE 74LS00 , TECHNOLOGY AND SERVICE! 52 This Material Copyrighted By Its Respective Manufacturer LOW POWER SCHOTTKY TTL


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PDF TTL-54/74 74LS00 400/u 400mA SO-14. t74ls157 74LS00E 74LS00 fan out T74LS74 74LS00 QUAD 2-INPUT NAND GATE 74LS00 nand gate 74ls00 series T74LS367 NAND 74LS00
TTL 74ls00

Abstract: 74LS00 74LS00 TTL motorola 74LS00 74LS00 truth table NAND 74LS00 74LS00 QUAD 2-INPUT NAND GATE 74LS00 DATA 74ls00 NAND gate 74LS00DC
Text: Current — Low 54 4.0 mA 74 8.0 FAST AND LS TTL DATA 5-2 SN54/ 74LS00 DC CHARACTERISTICS OVER , (g) MOTOROLA QUAD 2-INPUT NAND GATE • ESD > 3500 Volts vcc nn [ïïi ra m ra m m LlI LLI LLI LLI LiJ LLI LLI gnd SN54/ 74LS00 QUAD 2-INPUT NAND GATE LOW POWER SCHOTTKY GUARANTEED OPERATING RANGES f0 1 J SUFFIX CERAMIC CASE 632-08 Jfllffi 1 N SUFFIX PLASTIC CASE 646-06 1 D SUFFIX SOIC CASE , AND LS TTL DATA 5-3


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PDF SN54/74LS00 51A-02 SN54LSXXJ SN74LSXXN SN74LSXXD TTL 74ls00 74LS00 74LS00 TTL motorola 74LS00 74LS00 truth table NAND 74LS00 74LS00 QUAD 2-INPUT NAND GATE 74LS00 DATA 74ls00 NAND gate 74LS00DC
74LS00 fan-out

Abstract: 74LS00 TTL 74LS00 noise immunity 7400 fan-in 74LS00 gate 74LS00 Electrical and Switching characteristics TTL 7400 rise and fall time 74ls00 applications ttl 74ls00 series logic symbol 74LS00
Text: +125°C. TTL families may be mixed for optimum system design. The following table specify the worst case noise immunity in mixed systems. WORST CASE TTL DC NOISE IMMUNITY/NOISE MARGINS Electrical Characteristics Item 6 7 10 Symbol TTL HTTL LSTTL SGS-THOMSON TTL Families Standard TTL (54/74) High Speed TTL (54H/74H) Low Power Schottky TTL (54LS/74LS) Military ( - 5 5 t o +125 C) V il V ih V ol V oh , . LOW Level Noise Margins (Military) T° From TTL HTTL LSTTL From "V ol" to "V JL " LOW Level Noise


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PDF 54H/74H) 74LS00 fan-out 74LS00 TTL 74LS00 noise immunity 7400 fan-in 74LS00 gate 74LS00 Electrical and Switching characteristics TTL 7400 rise and fall time 74ls00 applications ttl 74ls00 series logic symbol 74LS00
ls 7400

Abstract: 7400 signetics TTL TTL LS 7400 7400 ls 7400 pin configuration TTL 7400 propagation delay 74LS00 signetics 74l500 74ls00 tr tf 74LS00 function table
Text: Signetìcs I 7400, LSOO, SOO Gates Logic Products Quad Two-Input NAND Gate Product Specification TYPE TYPICAL PROPAGATION DELAY TYPICAL SUPPLY CURRENT (TOTAL) 7400 9ns 8mA 74LS00 9.5ns 1.6mA , tor 74LS; VM - 1.5V tor all other TTL families input Pulse Definition FAMILY INPUT PULSE , .) PARAMETER TEST CONDITIONS1 7400 74LS00 74S00 UNIT Min Typ2 Max Min Typ2 Max Min Typ2 Max , 1,3V for 74LS; VM = 1.5V for all other TTL families. Waveform 1. Waveform For Inverting Outputs AC


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PDF 74LS00 74SOO N7400N, N74LS00N, N74S00N N74LS00D, N74S00D 10Sul 10LSul WF07570S ls 7400 7400 signetics TTL TTL LS 7400 7400 ls 7400 pin configuration TTL 7400 propagation delay 74LS00 signetics 74l500 74ls00 tr tf 74LS00 function table
74LS00 function table

Abstract: ls 7400 pin configuration logic symbol 74LS00 specification of 74ls00 74LS00 pin configuration TTL LS 7400 logic symbol 74LS00 TTL 74ls00 7400 ls pin configuration 74LS00
Text: Signelics | 7400, LS00, S00 Gates Quad Two-Input NAND Gate Product Specification Logic Products TYPE 7400 74LS00 74S00 TYPICAL PROPAGATION DELAY 9ns 9.5ns 3ns TYPICAL SUPPLY CURRENT , TEST CIRCUITS AND WAVEFORMS VM - 1.3V for 74LS; VM = 1.5V for all other TTL families. Test , 74LS00 Max Min 2.7 0.4 Typ2 3.4 0.35 0.25 -1 .5 0.5 0.4 -1 .5 Max Min 2.7 74S00 UNIT Min Typ2 3.4 0.2 , 70S Vm = 1.3V for 74LS; = 1.5V for all other TTL families. Waveform 1. Waveform For


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PDF 74LS00 74S00 N7400N, N74LS00N, N74S00N N74LS00D, N74SOOD 74LS00 function table ls 7400 pin configuration logic symbol 74LS00 specification of 74ls00 74LS00 pin configuration TTL LS 7400 logic symbol 74LS00 TTL 74ls00 7400 ls pin configuration 74LS00
7400 signetics

Abstract: 74LS00 7400 74S00 N7400N 7400 pin configuration 74LS00 function table 7400 signetics TTL 74LS00 DATA TTL 7400 TTL 7400 propagation delay 74LS00 pin configuration
Text: Signetics I 7400, LS00, SOO Gates Logic Products Quad Two-Input NAND Gate Product Specification TYPE TYPICAL PROPAGATION DELAY TYPICAL SUPPLY CURRENT (TOTAL) 7400 9ns 8mA 74LS00 9.5ns 1.6mA , 74LS; Vu - 1.5V for all other TTL families. Input Pulse Definition FAMILY INPUT PULSE REQUIREMENTS , CONDITIONS1 7400 74LS00 74S00 UNIT Min Typ2 Max Min Typ2 Max Min Typ2 Max HIGH-level OH output , other TTL families. Waveform 1. Waveform For Inverting Outputs AC ELECTRICAL CHARACTERISTICS TA = 25Â


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PDF 74LS00 74S00 N7400N, N74LS00N, N74S00N N74LS00D, N74S00D 10Sul 10LSul 7400 signetics 74LS00 7400 74S00 N7400N 7400 pin configuration 74LS00 function table 7400 signetics TTL 74LS00 DATA TTL 7400 TTL 7400 propagation delay 74LS00 pin configuration
TTL SN 54S00

Abstract: No abstract text available
Text: . J PACKAGE SN 54LS00, SN 54S00 . . . J OR W PACKAG E SN 7400 . . . N PACKAG E SN 74LS00 , SN , V IE W ) £Q < O «- t- z TTL Devices 2 FUNCTION TA B LE le a c h g a te ) o , -INPUT PQSITIVE-NAND GATES TTL Devices R e s is t o r v a lu e s s h o w n a re n o m in a l. absolute maximum , OFFICE BOX 6 5 5 0 1 2 • D ALLAS . TEXAS 7 5 2 6 5 U N IT TTL Devices PARAM ETER SN54LS00, SN74LS00 QUADRUPLE 2-INPUT POSITIVE NAND GATES recommended operating conditions SN 74LS00 SN 54LS00


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PDF SN5400, SN54LS00, SIU54S00, SN7400, SN74LS00, SN74S00 54LS00, 54S00 74LS00, 74S00 TTL SN 54S00
7404 TTL CMOS

Abstract: TTL 74h04 TTL 7400 fairchild 7404 ttl inverter CI 74LS00 TTL 7404 fairchild 9016 TTL 7404 fairchild 74H00 TTL TTL 9016 fairchild TTL 7401
Text: /7416 D2 9002, 54/7400, 54H/74H00, 54S/74S00, 54LS/ 74LS00 , 9012, 54H/74H01, 54/7403, 54S/74S03, 54LS , . a> Q. » Q c o ï 2 <= E ¡5 2 ^ S* « Q O) o .j Package(s) 1 /uA1488 Quad mA1489 TTL Volt Single Ended ±10 220 ±15 4 I49 6A,9A 2 54/7437 Quad 2-NAND Any TTL TTL Volt Single Ended 48 10 +5.0 ' ÜB 4 D2 3I, 6A,9A 3 54/7438 Quad 2-NAND 96106 TTL Volt Single Ended 48 13 +5.0 98 4 D2 3I, 6A,9A 4 54/7440 Dual 2-NAND Any TTL TTL Volt Single Ended 48 11 +5.0 52 2 D5 3I, 6A,9A 5 54H/74H40 Dual 2


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PDF 54H/74H04, 54S/74S04, 54LS/74LS04, 9S05A, 54H/74H05, 54S/74S05, 54L8/74LS05, 54LS/74LS14, 54H/74H00, 54S/74S00, 7404 TTL CMOS TTL 74h04 TTL 7400 fairchild 7404 ttl inverter CI 74LS00 TTL 7404 fairchild 9016 TTL 7404 fairchild 74H00 TTL TTL 9016 fairchild TTL 7401
IC TTL 74LS00

Abstract: 74LS00 CMOS ic 74LS00 74LS00 74ls00 tr tf TTL 74ls00 tr tf 74ls00 tphl tplh TC74HCT00AP TC74HCT00AF DIP14-P-300-2
Text: TC74HCT00AP/AF CMOS TC74HCT00AP,TC74HCT00AF Quad 2-Input NAND Gate TC74HCT00A CMOS CMOS 2 NAND CMOS LSTTL TTL TTL 3 TC74HCT00AP · : tpd = 10 ns () (VCC = 5 V) · : ICC = 1 A () (Ta = 25°C) · TTL : VIL = 0.8 V () · : LSTTL 10 · TC74HCT00AF VIH = 2.0 V () · : |IOH| = IOL = 4 mA () : tpLH tpHL - · LSTTL ( 74LS00 ) DIP14-P-300-2.54 : 0.96 g () SOP14-P-300-1.27A : 0.18 g () 1


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PDF TC74HCT00AP/AF TC74HCT00AP TC74HCT00AF TC74HCT00A TC74HCT00AP 74LS00) DIP14-P-300-2 OP14-P-300-1 IC TTL 74LS00 74LS00 CMOS ic 74LS00 74LS00 74ls00 tr tf TTL 74ls00 tr tf 74ls00 tphl tplh TC74HCT00AF
TTL LS 7400

Abstract: IC TTL 74LS00 IC TTL 74 ls 04 7400 fan-out cmos 7400 fan-out TTL 7400 catalog TTL 74ls00 of ic 74ls00 74LS00 gate TTL 7400 rise and fall time
Text: Design Considerations, Testing and Applications Assistance Form FAST AND LS TTL FAST AND LS TTL DATA 3-1 3 DESIGN CONSIDERATIONS SELECTING TTL LOGIC. TTL Families may be mixed in a , speed paths to minimize power consumption while FASTTM TTL would be used in high speed paths. The ratio of ALS to FASTTM will depend on overall system design goals. NOISE IMMUNITY. When mixing TTL , . Table 3.1 lists the guaranteed logic levels for various TTL families and can be used to calculate noise


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PDF
74LS00 truth table

Abstract: 74ls00 tphl tplh 74LS00
Text: (g ) M O TO R O LA SN54/ 74LS00 LU LU LU LU LU LU LU J Suffix - Case 632-08 (Ceramic) N Suffix - Case 646-06 {Plastic) rsPi rr^ PARAMETER Supply Voltage Output Current - High Output Current - Low PARAMETER Input HIGH Voltage 54 JE d J L5Î> Q UAD 2-IN PU T N AN D G A T E LOW POWER SCHOTTKY GUARANTEED OPC HATING RANGES SYMBOL vcc Ta 'oh 'OL MIN 54 74 54 74 5 4 ,7 4 54 74 45 4.75 -5 5 , AND LS TTL DATA 5-2


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PDF SN54/74LS00 74LS00 truth table 74ls00 tphl tplh 74LS00
TTL 74HC00

Abstract: 74LS00 TTL 5V 74HC00 logic symbol 74LS00 TTL 74ls00 74LS00 gate diagram 74LS00 function table 74ls00 74hc00 and gates 74HC00
Text: GD54/74HC00, GD54/74HCT00 QUAD 2-INPUT NAND GATES General Description These devices are identical in pinout to the 54/ 74LS00 . They contain four independent 2-input NAND gates. These devices are characterized for opération over Wide temperature ranges to meet in-dustry and military spécifications. Features • Low Power consumption characteristic of CMOS devices • Output drive capability: 10 LS TTL Loads Min. • Operating speed superior to LS TTL • Wide operating voltage range: for HC 2 to 6 volts


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PDF GD54/74HC00, GD54/74HCT00 54/74LS00. GD74HCT00 GD54HCT00 D0Q457Q TTL 74HC00 74LS00 TTL 5V 74HC00 logic symbol 74LS00 TTL 74ls00 74LS00 gate diagram 74LS00 function table 74ls00 74hc00 and gates 74HC00
74LS00 pinout

Abstract: TTL 74HC00 74hc00 and gates 5V 74HC00 74HC00 logic symbol 74LS00 pin configuration logic symbol 74LS00 GD74HC00 74LS00 gate diagram GD54HC00
Text: GD54/74HC00, GD54/74HCT00 QUAD 2-INPUT NAND GATES General Description These devices are identical in pinout to the 54/ 74LS00 . They contain four independent 2-input NAND gates. These devices are characterized for operation over wide temperature ranges to meet industry and military specifications. Features • Low Power consumption characteristic of CMOS devices • Output drive capability: 10 LS TTL Loads Min. • Operating speed superior to LS TTL • Wide operating voltage range: for HC 2 to 6


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PDF GD54/74HC00, GD54/74HCT00 54/74LS00. GD74HCT00 GD54HCT00 74LS00 pinout TTL 74HC00 74hc00 and gates 5V 74HC00 74HC00 logic symbol 74LS00 pin configuration logic symbol 74LS00 GD74HC00 74LS00 gate diagram GD54HC00
8085 microprocessor opcode sheet

Abstract: intel 8085 opcode 8085 opcode sheet free 8085 microprocessor opcode OPCODE SHEET FOR 8051 MICROCONTROLLER dynamic ram system of 8088 microprocessor intel 8085 opcode sheet intel 8051 opcode sheet intel 8085 opcode sheet free intel 8085 manual timing and control
Text: FOUR 2186 iRAMs PROVIDE 32K BYTES OF LOCAL STORAGE CLEAN a GENERATED BY ONE TTL PACKAGE ( 74LS00 ) ONE TTL PACKAGE ( 74LS00 ) DELAYS UNTIL DATA IS VALID THE iRAMs ARE IN UNIVERAL SITE SOCKETS WlTH


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PDF 2186s AP-132 AR-235 IE-3011128211OKlBAlAP 8085 microprocessor opcode sheet intel 8085 opcode 8085 opcode sheet free 8085 microprocessor opcode OPCODE SHEET FOR 8051 MICROCONTROLLER dynamic ram system of 8088 microprocessor intel 8085 opcode sheet intel 8051 opcode sheet intel 8085 opcode sheet free intel 8085 manual timing and control
2006 - Not Available

Abstract: No abstract text available
Text: for interfacing TTL or NMOS to High Speed CMOS. The inputs are compatible with TTL , NMOS and CMOS , dissipation: ICC = 1 µA (max) at Ta = 25°C • Compatible with TTL outputs: VIH = 2 V (min) VIL = 0.8 , propagation delays: tpLH ∼ tpHL − • Pin and function compatible with 74LS00 Pin Assignment


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PDF TC74HCT00AP/AF/AFN TC74HCT00AP TC74HCT00AF TC74HCT00AFN TC74HCT00A
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