The Datasheet Archive

Top Results (6)

Part ECAD Model Manufacturer Description Datasheet Download Buy Part
UF3C065030K4S UF3C065030K4S ECAD Model UnitedSiC Power Field-Effect Transistor, 85A I(D), 650V, 0.035ohm, 1-Element, N-Channel, Silicon Carbide, Junction FET, TO-247
UJ3C065080T3S UJ3C065080T3S ECAD Model UnitedSiC Power Field-Effect Transistor
UJ3N120070K3S UJ3N120070K3S ECAD Model UnitedSiC Power Field-Effect Transistor, 33.5A I(D), 1200V, 0.09ohm, 1-Element, N-Channel, Silicon Carbide, Junction FET, TO-247
UF3C065080B7S UF3C065080B7S ECAD Model UnitedSiC 650V-80mΩ SiC FET D2PAK-7L
UF3C120150K4S UF3C120150K4S ECAD Model UnitedSiC 1200V-150mΩ SiC FET TO-247-4L
UF3SC120040B7S UF3SC120040B7S ECAD Model UnitedSiC 1200V-35mΩ SiC FET D2PAK-7L

TSMC 0.18 um MOSfet Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
2009 - PCI AHB DMA

Abstract: tsmc 0.18 axi bridge
Text: Application Interface. Link Width x1 x1 X1 x4 x4 x4 Technology TSMC 0.13 µm TSMC 0.18 µm TSMC 90 nm TSMC 0.13 µm TSMC 0.18 µm TSMC 90 nm Approx. Area 45,300 gates 45,100 gates 41,000 gates , DMAs Technology TSMC 0.13 µm TSMC 0.18 µm TSMC 90 nm TSMC 0.13 µm TSMC 0.18 µm TSMC 90 nm


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PDF 250MB/s PCI AHB DMA tsmc 0.18 axi bridge
JESD22-A114F

Abstract: JESD47 JESD-47 JEDEC JESD22-B116 free download JESD22-A102C JESD22-A108B JESD22-B116A JESD22-A114-F JESD78B JESD22-A102-C
Text: Information: 0.18 µm , 3.3 V Fab Location: TSMC Fab 8 Technology Qualification Vehicle Test Summary ­ JESD47 , / Bridge Qualification Test Summary Technology Information: 0.18 µm , 3.3 V, Fab Location: TSMC Fab 8 Test , Information: 0.35 µm , 5.0 V Fab Location: TSMC Fab 3 Technology Qualification Vehicle Test Summary ­ JESD47 , Qualification Test Summary Technology Information: 0.35 µm , 5.0 V, Fab Location: TSMC Fab 3 71256TT, 256K SRAM , Result Summary Technology Information: 0.35 µm , 3.3 V Fab Location: TSMC Fab 3 Technology


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PDF JESD22-A115B, JESD78B AV265 JESD22-B116-A, EIA/JESD22-A110B, EIA/JESD22-A102C, 168hrs JESD22-A113 JESD22-A114F JESD47 JESD-47 JEDEC JESD22-B116 free download JESD22-A102C JESD22-A108B JESD22-B116A JESD22-A114-F JESD78B JESD22-A102-C
2008 - Not Available

Abstract: No abstract text available
Text: , and using a generic Application Interface. Link Width x8 x8 x8 Technology TSMC 0.13 µm TSMC 0.18 µm TSMC 0.90 µm Approx. Area 77,600 gates 83,700 gates 65,000 gates The core includes an , DMAs 2 DMAs Technology TSMC 0.13 µm TSMC 0.18 µm TSMC 0.90 µm Approx. Area 23,500 gates 22


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2009 - tsmc 0.18

Abstract: C32025TX C32025 TMS320C25 ram tsmc 0.18
Text: Device TSMC 0.18 µm TSMC 0.13 µm TSMC 0.09 µm TSMC 0.18 µm TSMC 0.13 µm TSMC 0.09 µm Area Area


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PDF 16-bit C32025TX C32025TX TMS320C25 tsmc 0.18 C32025 ram tsmc 0.18
2008 - rc5 protocol

Abstract: philips RC5 decoder RC5 encoder RC5 IR RC5 decoder philips RC5 protocol Manchester CODING DECODING FPGA RC5 IR encoder RC5 Infrared protocol philips RC5 Infrared transmitter
Text: ASIC results. Encoder TSMC 0.13 um TSMC 0.18 um Approx. Area 452 gates 477 gates Frequency > 300 MHz > 300 MHz Decoder TSMC 0.13 um TSMC 0.18 um Approx. Area 785 gates 832 gates


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2008 - NEC protocol

Abstract: Nec Infrared protocol decoder NEC IR circuit diagram for simple IR receiver IR decoder transmission NEC CIR NEC DECODER home theater IR remote control circuit diagram NEC IR protocol ir pulse decoder
Text: representative ASIC results. Encoder TSMC 0.13 um TSMC 0.18 um Approx. Area 781 gates 831 gates Frequency > 300 MHz > 300 MHz Decoder TSMC 0.13 um TSMC 0.18 um Approx. Area 1,120 gates 1,193


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2009 - 80C552

Abstract: philips tsmc
Text: address Core Modifications ASIC Technology TSMC 0.09 µm TSMC 0.13 µm TSMC 0.18 µm


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2009 - 64x18 synchronous sram

Abstract: TSMC Flash interface VHDL code for slave SPI with FPGA TSMC embedded Flash rx data path interface in vhdl verilog code for slave SPI with FPGA TSMC Flash memory 0.18
Text: and 2 FIFOs (RX/TX) of 64x18 bits. ASIC Technology TSMC 0.18 µm TSMC 0.13 µm TSMC 0.09 µm Fmax Logic Number of (MHz) Area¹ ( µm ²) eq. gates² 350 420 520 43,100 20,730 10,560 4,320


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PDF 16-bit 64x18 2x64x18 64x18 synchronous sram TSMC Flash interface VHDL code for slave SPI with FPGA TSMC embedded Flash rx data path interface in vhdl verilog code for slave SPI with FPGA TSMC Flash memory 0.18
2006 - 3248L

Abstract: No abstract text available
Text: RELIABILITY REPORT DATE: 6/8/05 QUALITY ENG : PART NUMBER MICREL KS8001L/KSZ8001L KS8001LD/KSZ8001LD PROJECT # PACKAGE TYPE : ASSEMBLY LOC LOT # FAB LOC D/C # PROCESS KS8001S 48L SSOP OSE GD64047MEA TSMC 0437A 0.18 um KS8001LD 48L QFP ASE GD64047MEK TSMC 0503A 0.18 um Description: 10BASE-T/100BASE-TX/FX Physical Layer Transceiver. KS8001L in QFP package KS8001S is equivelent to KSZ8001L in 48 LQFP Pb-Free package


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PDF KS8001L/KSZ8001L KS8001LD/KSZ8001LD KS8001S GD64047MEA KS8001LD GD64047MEK 10BASE-T/100BASE-TX/FX KS8001L KS8001S KSZ8001L 3248L
2009 - C3202

Abstract: C32025 TMS320C25 tsmc 0.18
Text: are sample results. Device TSMC 0.18 µm TSMC 0.13 µm TSMC 0.09 µm CAST, Inc. Approx. Area


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PDF 16-bit C32025 32-bit C32025 TMS320C25 C3202 tsmc 0.18
2009 - TSMC Flash memory 0.18

Abstract: tsmc 0.18 flash 80186EC 8259A c80186 intel FPGA 80C186EC 16X16 80C186EC C80187 TSMC Flash IP
Text: . ASIC Technology Area Frequency (clkout) TSMC 90 nm 66,256 gates 30 MHz TSMC 0.13 µm 68,174 gates 30 MHz TSMC 0.18 µm 62,402 gates 30 MHz Support The core as delivered is


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PDF C80186EC 80186EC-Compliant 16-bit 16-bit 80C186EC 80186EC 80c86 80c186 TSMC Flash memory 0.18 tsmc 0.18 flash 8259A c80186 intel FPGA 80C186EC 16X16 C80187 TSMC Flash IP
2009 - 80186xl

Abstract: c80186 C80186XL 16X16 80C186XL C80187 "embedded dram" tsmc i8259a TSMC embedded Flash TSMC Flash IP
Text: / Speed TSMC 90 nm 51392 / 57623 gates 50 / 204 MHz TSMC 0.13 µm 51198 / 59924 gates 50 / 166 MHz TSMC 0.18 µm 47560 / 52700 gates 50 / 121 MHz Support The core as delivered is


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PDF C80186XL 80186XL-Compliant 16-bit 16-bit 80C186XL 80186XL 80c86 80c186 c80186 C80186XL 16X16 C80187 "embedded dram" tsmc i8259a TSMC embedded Flash TSMC Flash IP
2008 - 32Gb Nand flash toshiba

Abstract: TSMC Flash pdf of 32Gb Nand flash memory by toshiba verilog code for amba ahb and ocp network interface ahb wrapper verilog code Samsung MLC bch verilog code vhdl code hamming vhdl code hamming ecc NAND FLASH Controller
Text: internal buffers or DMA. ASIC Technology TSMC 0.18 um TSMC 0.13 um TSMC 0.09 um Area Optimized


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2009 - TSMC Flash memory 0.18

Abstract: 32Gb Nand flash toshiba tsmc 0.18 flash TSMC embedded Flash ahb wrapper vhdl code ahb wrapper verilog code toshiba NAND Flash MLC TSMC Flash interface flash controller verilog code Toshiba MLC flash
Text: mechanism, 2kB page size, and without internal buffers or DMA. ASIC Technology TSMC 0.18 µm TSMC 0.13 µm TSMC 0.09 µm Area Optimized Speed Optimized Area (gates) Fmax Area (gates) Fmax


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PDF FAT12/16/32 TSMC Flash memory 0.18 32Gb Nand flash toshiba tsmc 0.18 flash TSMC embedded Flash ahb wrapper vhdl code ahb wrapper verilog code toshiba NAND Flash MLC TSMC Flash interface flash controller verilog code Toshiba MLC flash
2009 - tsmc cmos 0.13 um

Abstract: CH7301C cmos tsmc 0.18 TSMC 0.18 um CMOS RGB24 ahb slave RTL Sitronix ST7787 ST7787 Application Notes tsmc cmos ADV7120
Text: following ASIC results are optimized for area and exclude any memory. ASIC Technology TSMC 0.18 um TSMC 0.13 um TSMC 90 nm Approx. Area Frequency (hclk) Frequency (clk_pxl) 14,183 gates


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PDF 320x240) 1920x1200) 15-bit 24-bit 24-bit RGB24 ADV7120 80MHz CH7301C tsmc cmos 0.13 um CH7301C cmos tsmc 0.18 TSMC 0.18 um CMOS ahb slave RTL Sitronix ST7787 ST7787 Application Notes tsmc cmos ADV7120
TSMC 0.18 um CMOS

Abstract: 0.18-um CMOS technology characteristics tsmc 0.18 flash tsmc cmos 0.18 um AD8138 AD8351 N-7075 vhdl coding for analog to digital converter verilog code for adc verilog code of analog mixed mode
Text: silicon area, and includes necessary shielding and guardring. It is implemented in TSMC 0.18 µm CMOS , or out-of-range. Implemented in a generic 0.18 µm CMOS process, operating from a single 1.8 V , and beyond. It thus represents an ideal solution for QUICK REFERENCE DATA Hard Macro / TSMC Generic, 6 Metal 0.18 µm CMOS 0.77 mm2 / 1.180 × 0.65 mm IP Type / Technology IP Area / Dimensions , . No fill pattern is necessary to meet TSMC density rules, it meets all TSMC density rules on poly


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PDF nAD10110-18a 10-bit nAD10110-18a N-7075 TSMC 0.18 um CMOS 0.18-um CMOS technology characteristics tsmc 0.18 flash tsmc cmos 0.18 um AD8138 AD8351 vhdl coding for analog to digital converter verilog code for adc verilog code of analog mixed mode
TSMC 0.18 um CMOS

Abstract: vhdl coding for analog to digital converter adc vhdl cmos tsmc 0.18 0.18-um CMOS technology characteristics TSMC 0.18 um CMOS silicon AD8138 AD8351 N-7075 vlsi design physical verification
Text: Hard Macro / TSMC Generic, 6 Metal 0.18 µm CMOS 2 0.86 mm / 1.310 × 0.65 mm IP Type / Technology , over-range, under-range or out-of-range. Implemented in a generic 0.18 µm CMOS process, operating from a , 0.86 mm of silicon area, and includes necessary shielding and guardring. It is implemented in TSMC 0.18 µm CMOS process, using no extra mixed signal options. All the 6 available metal layers are utilized by the core. No fill pattern is necessary to meet TSMC density rules, it meets all TSMC density


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PDF nAD12110-18a 12-bit nAD12110-18a N-7075 TSMC 0.18 um CMOS vhdl coding for analog to digital converter adc vhdl cmos tsmc 0.18 0.18-um CMOS technology characteristics TSMC 0.18 um CMOS silicon AD8138 AD8351 vlsi design physical verification
TSMC 0.18 um CMOS

Abstract: TSMC rf cmos 0.18 um IFSR15 N-7075 cmos tsmc 0.18 1/TSMC rf cmos 0.18 um
Text: REFERENCE DATA Hard Macro / TSMC Generic, 6 Metal 0.18 µm CMOS 0.8 mm2 / 0.8 × 1.0 mm IP Type , shielding and guardring. It is implemented in TSMC 0.18 µm CMOS process, using no extra mixed signal , . Implemented in a generic 0.18 µm CMOS process, operating from a single 1.8 V supply and employing a fully , TSMC density rules, it meets all TSMC density rules on ploy and metal. It is designed for, and verified with standard TSMC I/O pads with ESD protection. I/O Pads are not included in pad type the core


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PDF nDA10200x2-18a 10-bit nDA10200x2-18a N-7075 TSMC 0.18 um CMOS TSMC rf cmos 0.18 um IFSR15 cmos tsmc 0.18 1/TSMC rf cmos 0.18 um
2000 - XPC823ZT66B2T

Abstract: XPC823 XPC823ZT75B2T XPC823ZT81B2T KXPC823ZT81B2T MPC823 W90913 XPC823ZT
Text: Communications System Division PCN: MPC823 XC Qualification in TSMC /WaferTech Motorola is pleased to announce an additional wafer fabrication facility, TSMC /WaferTech, for the MPC823 integrated controller , demand in the marketplace. The TSMC /WaferTech process has identical electrical parameter targets as the , either TSMC /WaferTech or MOS11. This method provides maximum flexibility to the customer to service , MOS11 and not through the TSMC expansion. There is no need to transition scheduled backlog to the new


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PDF MPC823 XPC823 MOS11 W90913 W90904 W90912 XPC823ZT66B2T XPC823ZT75B2T XPC823ZT81B2T KXPC823ZT81B2T W90913 XPC823ZT
TSMC 0.18 um CMOS

Abstract: verilog code for adc verilog code pipeline square root vhdl coding for analog to digital converter AD8138 AD8351 N-7075 0.18-um CMOS technology characteristics vhdl coding for pipeline TSMC Flash IP
Text: systems. QUICK REFERENCE DATA Hard Macro / TSMC Generic, 6 Metal 0.18 µm CMOS 1.6 mm2 / 1.180 × 1.32 , shielding and guardring. It is implemented in TSMC 0.18 µm CMOS process, using no extra mixed signal , multimedia. Implemented in a generic 0.18 µm CMOS process, operating from a single 1.8 V supply and , TSMC density rules, it meets all TSMC density rules on poly and metal. It is designed for, and verified with standard TSMC I/O pads with ESD protection. I/O Pads are not included in the core


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PDF nAD10110x2-18a 10-bit nAD10110x2-18a N-7075 TSMC 0.18 um CMOS verilog code for adc verilog code pipeline square root vhdl coding for analog to digital converter AD8138 AD8351 0.18-um CMOS technology characteristics vhdl coding for pipeline TSMC Flash IP
XPC823ZT66B2T

Abstract: XPC823ZT81B2T XPC823 XPC823ZT75B2T motorola tsmc XPC823ZT66B2 KXPC823ZT81B2T MPC823 MOS11 xpc823zt66
Text: Communications System Division PCN: MPC823 XC Qualification in TSMC /WaferTech Motorola is pleased to announce an additional wafer fabrication facility, TSMC /WaferTech, for the MPC823 integrated controller , demand in the marketplace. The TSMC /WaferTech process has identical electrical parameter targets as the , either TSMC /WaferTech or MOS11. This method provides maximum flexibility to the customer to service , MOS11 and not through the TSMC expansion. There is no need to transition scheduled backlog to the new


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PDF MPC823 XPC823 MOS11 W90913 W90904 W90912 XPC823ZT66B2T XPC823ZT81B2T XPC823ZT75B2T motorola tsmc XPC823ZT66B2 KXPC823ZT81B2T xpc823zt66
CL018G

Abstract: TSMC 0.18 um CMOS silicon TSMC 0.18 um CMOS low power low noise frequency divider specification cmos tsmc 0.18 tsmc cmos model N-7075 0.18 um CMOS Process adc verilog tsmc cmos 0.18 um
Text: BRIEF PRODUCT SPECIFICATION nPLL20240-18a 240MHz Low Jitter PLL FEATURES · · · · · · · · · TSMC CL018G 1.8 V 240 MHz Low Jitter PLL Reference Clock Input 20 Mhz, 40 MHz and 80 MHz Programmable Steps, 3, 6 or 12 Divider 80 MHz, 40 MHz and 20 MHz Complimentary Outputs Low Power Dissipation , , and occupies less than 0.03 mm2, implemented in a generic 0.18 µm CMOS process, operating from a , clocks Duty Cycle at 80 MHz clocks Hard Macro / TSMC CL018G 1.8V 1P5M 0.03 mm2 Min. Typ


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PDF nPLL20240-18a 240MHz CL018G N-7075 TSMC 0.18 um CMOS silicon TSMC 0.18 um CMOS low power low noise frequency divider specification cmos tsmc 0.18 tsmc cmos model 0.18 um CMOS Process adc verilog tsmc cmos 0.18 um
2008 - SHA-256 asic

Abstract: SHA256 SHA-256
Text: available in the technology. ASIC Technology UMC 0.18 µm TSMC 0.09 µm Fmax (MHz) 280 500 Logic Area ( um 2) 250,040 50,800 Number of eq. gates¹ 20.5 K 18.0 K 1. Equivalent gate count uses , implementation, running at 280 MHz and requiring just 20,500 gates in a 0.18 µm ASIC process. The complete


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PDF SHA-256. SHA256 SHA-256 SHA256 SHA-256 asic
2009 - verilog code for implementation of des

Abstract: verilog code for des tsmc sram des verilog RTL 604
Text: Throughput (MHz) (Mbps) TSMC .09 µm 7,297 2.82 2,588 334 1336 TSMC .13 µm 14,793 5.0922 2,905 232 928 TSMC .18 µm 29,958 9.9792 3,002 151 604 Non Pipelined , .) Frequency Throughput (MHz) (Gbps) TSMC .09 µm 8,411 2.82 2,983 625 2.50 TSMC .13 µm 20,525 5.0922 4,031 555 2.22 TSMC .18 µm 41,626 9.9792 4,171 416 1.66 , through extensive simulation and rigorous code coverage measurements. Deliverables TSMC .09 µm 106


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PDF 0x0123456789abcdef 0x4e6f772069732074 0x68652074696d6520 0x666f7220616c6c20 0x3fa40e8a984d4815 0x6a271787ab8883f9 0x893d51ec4b563b53 verilog code for implementation of des verilog code for des tsmc sram des verilog RTL 604
2012 - 130nm CMOS

Abstract: 130nm tsmc cmos model 130-nm tsmc cmos TSMC IO
Text: Data sheet IO ESD protection Low capacitive IO protection for TSMC 130nm CMOS technology Sofics has verified its TakeCharge ESD protection clamps on TSMC 130nm CMOS technology. The devices are , IO interfaces in TSMC 130nm CMOS technology. It features a low leakage current, low capacitance and a small silicon footprint. Data sheet: Low capacitive IO protection for TSMC 130nm CMOS , output-driver must be silicide blocked: min width outputdriver 320 um IO Protection The output-driver


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PDF 130nm 130nm B-9880 130nm CMOS tsmc cmos model 130-nm tsmc cmos TSMC IO
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