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Part ECAD Model Manufacturer Description Datasheet Download Buy Part
UJ3C065080T3S UJ3C065080T3S ECAD Model UnitedSiC Power Field-Effect Transistor
UF3C065080B7S UF3C065080B7S ECAD Model UnitedSiC 650V-80mΩ SiC FET D2PAK-7L
UF3C120150K4S UF3C120150K4S ECAD Model UnitedSiC 1200V-150mΩ SiC FET TO-247-4L
UF3SC120040B7S UF3SC120040B7S ECAD Model UnitedSiC 1200V-35mΩ SiC FET D2PAK-7L
UJ3C065080B3 UJ3C065080B3 ECAD Model UnitedSiC 650V-80mΩ SiC FET D2PAK-3L
UJ4C075023B7S UJ4C075023B7S ECAD Model UnitedSiC 750V-23mΩ SiC FET D2PAK-7L

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TR1602A

Abstract: No abstract text available
Text: (SBDIP) (MODE 1) TOP VIEW - 40] T CLOCK m m 39] EPE 38] W LS 1 37] W LS 2 36| SBS , Dissipation Per O utput Transistor For T/\ = Full Package-Temperature R a n g e , 10 TPB tTT 5 10 Propagation Delay Tim e Clock to Data Start Bit tCD 5 10 425 205 315 , ) TRANSMITTER SHIFT REGISTER LOADED (NOTE 2) te c T CLOCK tcD WRITE (TPB) (NOTE 3) *CTH -8 - THRE tcD SDO 1ST DATA BIT NOTES: 1. The holding register is loaded on the trailing edge of TPB. 2. The


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PDF CDP1854A/3, CDP1854AC/3 CDP1854A/3 CDP1854AC/3 CDP1800-series y--01 TR1602A
2006 - 13002C

Abstract: 13002B TRANSISTOR NPN TRANSISTOR TCD 100 transistor 13002e 13002a 13002B 13002C TRANSISTOR 13002A transistor 13002e 13002
Text: SILICON PLANAR EPITAXIAL, HIGH VOLTAGE FAST SWITCHING POWER TRANSISTOR CD13002 TCD13002 (Tin Lead , V V V A A W VALUE 600 400 9.0 1.0 1.5 1.0 MIN 600 400 9.0 TYP MAX 100 50 100 28 20 0.11 0.24 0.88 0.4 0.9 15 5.0 0.05 0.12 0.82 0.07 4.0 A 15-19 B 18-22 C 21-25 CD 13002B XY CD 13002C XY CD 13002E XY TCD 13002A XY TCD 13002B XY TCD 13002C XY V V V µs µs MHz E 24-28 CD 13002A XY UNIT V V V µA


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PDF CD13002 TCD13002 C-120 CD13002 CTD13002Rev 050706E 13002C 13002B TRANSISTOR NPN TRANSISTOR TCD 100 transistor 13002e 13002a 13002B 13002C TRANSISTOR 13002A transistor 13002e 13002
2010 - TRANSISTOR TCD 100

Abstract: No abstract text available
Text: 25 °C Release delay, tDET + tCD (ms) 10000 1000 Vcc = 1.6 V Vcc = 3 V Vcc = 6 V 100 , monitored on separate sense input VSEN I Factory-trimmed voltage thresholds in 100 mV increments , . . . . . . . . . . . . . . . . . . . . . 19 SOT23-5 - 5-lead small outline transistor package , 25 °C, external pull-up resistor on RST is 100 kΩ, CD pin open . . . . . . . . . . . . . . . . . , = VCC, external pull-up resistor on RST is 100 kΩ, CD pin open . . . . . . . . . . . . . . . . .


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PDF STM1831 OT23-5 OT23-5 TRANSISTOR TCD 100
2006 - 13002a

Abstract: 13002C TRANSISTOR TCD 100 13002B TRANSISTOR NPN 13002e transistor 13002e 13002B 13002 FLUORESCENT LAMPS CFLS 13002b TRANSISTOR
Text: CD13002 TO-92 PLASTIC PACKAGE NPN SILICON PLANAR EPITAXIAL,HIGH VOLTAGE FAST SWITCHING POWER TRANSISTOR Compact Fluorescent Lamps (CFLS) E ABSOLUTE MAXIMUM RATING (Ta =25ºC ) DESCRIPTION , availability. CB MIN 600 400 9.0 TYP MAX 100 50 100 28 20 0.11 0.24 0.88 0.4 0.9 , XY CD 13002B XY CD 13002C XY CD 13002E XY TCD 13002A XY TCD 13002B XY TCD 13002C XY TCD 13002E XY UNIT V V V mA mA mA V V V ms ms MHz TO-92 Plastic


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PDF CD13002 13002a 13002C TRANSISTOR TCD 100 13002B TRANSISTOR NPN 13002e transistor 13002e 13002B 13002 FLUORESCENT LAMPS CFLS 13002b TRANSISTOR
2010 - STM1831

Abstract: TRANSISTOR TCD 100 STM1831L
Text: monitored on separate sense input VSEN Factory-trimmed voltage thresholds in 100 mV increments from , . . . . . . . . . . . . . . . . 19 SOT23-5 - 5-lead small outline transistor package mechanical , 25 °C, external pull-up resistor on RST is 100 k, CD pin open . . . . . . . . . . . . . . . . . . . , VCC, external pull-up resistor on RST is 100 k, CD pin open . . . . . . . . . . . . . . . . . . . . . , outline transistor package mechanical drawing . . . . . . . . . . . . . . 21 Doc ID 18180 Rev 1


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PDF STM1831 OT23-5 OT23-5 STM1831 TRANSISTOR TCD 100 STM1831L
2006 - Not Available

Abstract: No abstract text available
Text: TCD TDC TCB 5 6 7 8 9 10 RAB RBC RCD RDC RCB RBA 1 TBA , Storage temperature 4 13 PSC PS12NG TAB 5 12 PSB TBC 6 11 PSA TCD 7 10 TBA TDC , 1.20V PU 1.00V PSC PSD 12 µA VEE 1.20 V PUD C PUD TAB TBC TCD TDC TCB , * VON Rising VONPD Power-down threshold 0.95 1.00 1.05 V * VON Falling VHY , V * VOV Rising VOVPU Power-up threshold 0.95 1.00 1.05 V * VOV Falling


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PDF 16-Lead 25MIN 27BSC DSFP-PS12 NR091206
13002C TRANSISTOR

Abstract: 13002B TRANSISTOR NPN transistor 13002C transistor 13002e transistor+13002e
Text: SILICON PLANAR EPITAXIAL, HIGH VOLTAGE FAST SWITCHING POWER TRANSISTOR CD13002 TCD13002 (Tin Lead , V V V A A W VALUE 600 400 9.0 1.0 1.5 1.0 MIN 600 400 9.0 TYP MAX 100 50 100 28 20 0.11 0.24 0.88 0.4 0.9 15 5.0 0.05 0.12 0.82 0.07 4.0 A 15-19 B 18-22 C 21-25 CD 13002B XY CD 13002C XY CD 13002E XY TCD 13002A XY TCD 13002B XY TCD 13002C XY V V V µs µs MHz E 24-28 CD 13002A XY UNIT V V V


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PDF CD13002 TCD13002 C-120 CD13002 CTD13002Rev 050706E 13002C TRANSISTOR 13002B TRANSISTOR NPN transistor 13002C transistor 13002e transistor+13002e
1999 - TRANSISTOR TCD 100

Abstract: SRAM 6116 AN-203 AN203 AN231
Text: increase this bus efficiency to 100 % by eliminating the idle cycles imposed upon the system by , from Vcc through the on transistor of the ASIC to ground through the on transistor of the SRAM. This , to no impact on Clock to Valid Data ( tCD ). This means that Smart ZBT still provides the fast tCDs , impact on tCD . Therefore, the turn-on of the output drivers is delayed, while the availability of data is unaffected. The following table exemplifies the benefits of Smart ZBT: Frequency (MHz) 100


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PDF AN-231 x4033 TRANSISTOR TCD 100 SRAM 6116 AN-203 AN203 AN231
2006 - Not Available

Abstract: No abstract text available
Text: +1.8V CONVERTER OUT PS12NG PSC 2 PUD CPUD PSD TAB TBC TCD TDC TCB TBA , TAB 5 12 PSB TBC 6 11 PSA TCD 7 10 TBA TDC 8 9 -0.3V.+8V ESD (all pins , PSC PSD 12 µA VEE 1.20 V PUD C PUD TAB TBC TCD TDC TCB TBA R AB , VONPD Power-down threshold 0.95 1.00 1.05 V * VON Falling VHY Power-up , * VOV Rising VOVPU Power-up threshold 0.95 1.00 1.05 V * VOV Falling VHY


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PDF 16-Lead 25MIN 27BSC DSFP-PS12 NR112206
TRANSISTOR TCD 100 LS

Abstract: No abstract text available
Text: ) TCD548 1 AD GENERAL The TCD 5481AD is an interline CCD area im age sensor developed for a NTSC , Transistor Drain V oltage Protective Transistor Bias V oltage O verflow Drain Voltage O perating Tem , s s e t fo rt h in t h e m o s t re c e n t p ro d u c ts s p e c ific a t io n s . A ls o , p le a , (Phase 4) Horizontal CCD Clock (Phase 1) Horizontal CCD Clock (Phase 2) Reset Gate O utput Transistor Drain SYM BO L OS OFD SS1 SS2 NC RD PT PIN NAME O utput Transistor Source O verflow Drain


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PDF TCD5481AD TCD548 5481AD TRANSISTOR TCD 100 LS
2007 - TRANSISTOR TCD 100

Abstract: psa 200 power supply WINDOW COMPARATOR 125OC PS12 PS12NG-G power on sequence CIRCUIT diagram
Text: +1.8V CONVERTER OUT PS12NG PSC 2 PUD CPUD PSD TAB TBC TCD TDC TCB TBA , 14 PSD 4 13 PSC TAB 5 12 PSB TBC 6 11 PSA Value TCD 7 10 TBA , TAB TBC TCD TDC TCB TBA R AB R BC R CD R DC R CB R BA 2 PS12 , Falling VHY Power-up/Power-down hysteresis - 100 - mV - - ION Input , V * VOV Falling VHY Power-up/power-down hysteresis - 100 - mV - -


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PDF MS-012, DSFP-PS12 NR042707 TRANSISTOR TCD 100 psa 200 power supply WINDOW COMPARATOR 125OC PS12 PS12NG-G power on sequence CIRCUIT diagram
1999 - transistor 9740

Abstract: 74HCT00 74HCT123 74HCT193 74HCT32 HA4600 HA5020 HFA1145 HFA3046 Mancini
Text: repetition frequency. The input signal is also present at the input to the HFA3046 transistor array which , bias the long tailed transistor at 10mA which is the optimum point for speed. R5 and R6 are small , TCD CPU PL PL 10K 10K SX2 GND 5V P3 10K R5 5V B1 CLR 300pF C , 5V P2 R4 SY0 MR CPU 5V 10K 74HCT32 TCD GND 5V P0 SX0 MR , EUROPE Intersil SA Mercure Center 100 , Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111


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PDF AN9740 transistor 9740 74HCT00 74HCT123 74HCT193 74HCT32 HA4600 HA5020 HFA1145 HFA3046 Mancini
1997 - 74HCT00 HARRIS

Abstract: AN9740 HARRIS 74HCT123 transistor 9740 diode 1334 74HCT00 74HCT193 74HCT32 HA4600
Text: so the HFA3046 was configured as a comparator. R6, R7, and R8 bias the long tailed transistor at 10mA , frequency. 1 2V/DIV The input signal is also present at the input to the HFA3046 transistor array , 5V -5V VCC SY2 P3 SX3 5V -5V 5V P2 5V P2 C1 TCD CPU PL R4 SY0 MR CPU 5V 10K 74HCT32 TCD GND 5V P0 SX0 MR CPD 5V , Harris Semiconductor Mercure Center 100 , Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111


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PDF AN9740 1-800-4-HARRIS 74HCT00 HARRIS AN9740 HARRIS 74HCT123 transistor 9740 diode 1334 74HCT00 74HCT193 74HCT32 HA4600
1999 - p2 10K

Abstract: transistor 9740
Text: signal is also present at the input to the HFA3046 transistor array which has been configured as a high , bias the long tailed transistor at 10mA which is the optimum point for speed. R5 and R6 are small , 5V 5V TCD 5V SY1 10K P1 VCC 5V 5V 10K SY0 ENABLE 74HCT193 5V SX1 10K P1 VCC X Y P0 MR TCD , Center 100 , Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA


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PDF AN9740 p2 10K transistor 9740
2000 - HFA3046

Abstract: 74HCT193 HFA1145 74HCT00 74HCT123 74HCT32 HA4600 HA5020 transistor 9740
Text: , and R8 bias the long tailed transistor at 10mA which is the optimum point for speed. R5 and R6 are , /DIV The input signal is also present at the input to the HFA3046 transistor array which has been , 5V P1 SX1 10K X 5V 5V VCC 10K 5V Y CPD 5V TCD CPU PL PL , MR CPU 5V 10K 74HCT32 TCD GND 5V P0 SX0 MR CPD 5V VCC 10K


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PDF AN9740 HA4600 480MHz) HA5020 HFA1145 HA4600. HFA3046 74HCT193 HFA1145 74HCT00 74HCT123 74HCT32 transistor 9740
2001 - KLI-10203

Abstract: kli-8013 KLI-14403 MPS5771 KLI-6013 KLI-6003 KLI-8023 cm218 10203 H2N transistor
Text: supplies required to support the KLI-10203. 5K .1 100 uF 10 uF LS 35 ID .1 , Description Symbol PHIA TGn LOGn H1n H2n PHIR VIDn VDD VSSn LS OG RD SUB ID IG SUB , SUB 11 30 SUB 12 29 RD 13 28 OG 14 27 LS 15 26 VDD 16 , Test 10200 Active Pixels 24 Dark LS / LOD OG VIDn TG VSSn * Blank CCD Cells , (either polarity) between any two pins. Includes pins: VIDn, VSSn, RD, VDD, LS and ID. Care must be


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PDF KLI-10203 74ACTypical kli-8013 KLI-14403 MPS5771 KLI-6013 KLI-6003 KLI-8023 cm218 10203 H2N transistor
2014 - Not Available

Abstract: No abstract text available
Text: KLI-8023 Image Sensor Device Description LS LOGn Photodiode Array 14 Test TG1 IG TG2 6 Blank , regions, reset transistor and output amplifier noise, and input clocking noise. An input referred noise , an 'off' state and LOG strongly biased, all of the photocurrent will be drawn off to the LS drain , ; that is, 100 % of the collected photogenerated charge is transferred to the adjacent CCD. The use of , passing through V sat and Vdark. The percent linearity is then 100 minus the non-linearity. The output


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PDF KLI-8023 PS-0052 MTD/PS-0219 PS-0052
2012 - LDR sensor light dark sensor

Abstract: KEK-4H0093-KLI-8023-12-5 oscilloscope KLI-8023-AAA CCD linear multispectral 4H0614 KLI8023
Text: Revision 1.0 PS-0052 Pg 6 KLI-8023 Image Sensor Device Description LS LOGn Photodiode Array 14 Test , components from dark current within the photosite and CCD regions, reset transistor and output amplifier , LOG strongly biased, all of the photocurrent will be drawn off to the LS drain. Referring to the , , no charge is left behind during such transfers and lag is equal to zero; that is, 100 % of the , sat and Vdark. The percent linearity is then 100 minus the non-linearity. The output linearity of a


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PDF KLI-8023 PS-0052 PS-0052 MTD/PS-0219 LDR sensor light dark sensor KEK-4H0093-KLI-8023-12-5 oscilloscope KLI-8023-AAA CCD linear multispectral 4H0614 KLI8023
2003 - KLI-14403

Abstract: KLI-6003 transistor H1A Kodak CCD 28 pin KLI-6013 EL7202 KLI-8023 7218E 1N914 2N2369
Text: .1 .1 Ferrite Bead + 15V 100 uF LS 35 26 10 uF .1 .1 uF 29 28 .1 , Symbol PhiA TG LOGn H1A,B H2A,B PHIR VIDn VDD VSSn LS OG RD SUB SUB 2 39 H1A , LS 8 33 SUB TG 9 32 PhiA SUB 10 SUB PHIR VSSB VIDB SUB VIDG VSSG , 14404 Active Pixels TG H2A OG C CCD lank 4B 2 Blank CCD Cells H1A 16 Dark LS , any two pins. Includes pins: VIDn, VSSn, RD, VDD, LS and ID. Care must be taken not to short output


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PDF KLI-14403 74ACT 500KHz KLI-6003 transistor H1A Kodak CCD 28 pin KLI-6013 EL7202 KLI-8023 7218E 1N914 2N2369
2003 - KLI-14403

Abstract: KLI-6003 kli-2113 CCD KODAK KLI-2113 transistor h1a KLI-8811 KLI-10203 Kodak KLI-8023 mps5771 KLI2113
Text: 100 pF, and requires fast rise and fall times. The complimentary bipolar switching transistor circuit , · · Pin Description Symbol PhiA TG LOGn H1A,B H2A,B PHIR VIDn VDD VSSn LS OG RD SUB ID IG , ,10,11,15,18,20, 21,23,27,30,31,33,37, 38,40 35 36 SUB H2A SUB SUB SUB LOGG LOGB LS TG SUB 1 2 3 , Blank CCD Cells ID PHIR PhiAn IG TG LS / LOD Ce lls Vdd LOGn 16 Test 14404 Active Pixels , , VSSn, RD, VDD, LS and ID. Care must be taken not to short output pins to ground during operation as


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PDF KLI-14403 74ACT 002pA/pixel com/US/en/dpq/site/SENSORS/name/KLI-14403 product/show/KLI-14403 KLI-14403 KLI-6003 kli-2113 CCD KODAK KLI-2113 transistor h1a KLI-8811 KLI-10203 Kodak KLI-8023 mps5771 KLI2113
2002 - MAX111

Abstract: MAX1115 MAX1115EKA MAX1116 MAX1116EKA AADU maxim 2112 TRANSISTOR TCD 100
Text: , VIN = VREF (P-P), fSCLK = 5MHz, fSAMPLE = 100ksps, RIN = 100 ) Signal-to-Noise Plus Distortion , COUT 4 ±10 V µA pF TIMING CHARACTERISTICS (Figures 6a­6d) CNVST High Time tcsh 100 ns CNVST Low Time tcsl 100 ns Conversion Time tconv 7.5 µs Serial Clock , Falling Edge to DOUT tcd CLOAD = 100pF Serial Clock Rising Edge To DOUT High-Z tchz CLOAD = 100pF, Figure 2 Last Serial Clock to Next CNVST (successive conversions on CH0) tccs 100


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PDF MAX1115/MAX1116 MAX1115 MAX1116 100ksps. MAX1115) MAX1116) MAX1115/MAX1116 MAX111 MAX1115EKA MAX1116EKA AADU maxim 2112 TRANSISTOR TCD 100
1999 - TR1602A

Abstract: CDP1854ACD3 CDP1800 CDP6402
Text: Output Transistor For TA = Full Package-Temperature Range . . . . . . . . . . . 100mW , tCL Clock Low Level Clock High Level TPB Propagation Delay Time tCH tTT tCD , tCL 2 3 4 5 6 7 14 15 16 1 2 4 3 tCD WRITE (TPB) (NOTE 3) tTT tCTH tTTH THRE tCD 1ST DATA BIT SDO NOTES: 1. The holding register is loaded , TPB and transmission of a start bit occurs 1/2 clock period + tCD later. 3. Write is the overlap of


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PDF CDP1854A/3, CDP1854AC/3 TR1602A CDP6402 CDP1800 CDP1854A/3 CDP1854AC/3 CDP1800-sts CDP1854ACD3 CDP6402
2002 - qvga Hsync Vsync generator

Abstract: JIS-Z8901 ORD 1114 55LHS-3L NL3224AC35-06 EN0229EJ4V0DS00 55pwb22 Jaso CCP2E25TE C1239
Text: NL3224AC35-06 module is composed of the amorphous silicon thin film transistor liquid crystal display (a-Si TFT LCD) panel structure with driver LSIs for driving the TFT (Thin Film Transistor ) array and a , Frequency tcf - 6.4 - MHz 157.3 ns (typ.) Note1 Duty tcd 0.4 - 0.6 - , parameters is as follows. tcf = 1/tc, tcd = tch/tc = tch×tcd Note2: Definition of parameters is as follows , (typ.) Note1 Duty tcd 0.4 - 0.6 - Note1 Rise time, Fall time tcrf - -


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PDF NL3224AC35-06 EN0229EJ4V0DS00 qvga Hsync Vsync generator JIS-Z8901 ORD 1114 55LHS-3L NL3224AC35-06 EN0229EJ4V0DS00 55pwb22 Jaso CCP2E25TE C1239
2002 - CDP1854ACD3

Abstract: TR1602A CDP1800 CDP6402 tr1602-a
Text: . . . . . . . . . . . . . . . . . . ±10mA Device Dissipation Per Output Transistor For TA = Full , Clock High Level TPB Propagation Delay Time tCH tTT tCD Clock to Data Start Bit TPB , 14 15 16 1 2 4 3 tCD WRITE (TPB) (NOTE 3) tTT tCTH tTTH THRE tCD , occurs 1/2 clock period + tCD later. 3. Write is the overlap of TPB, CS1, and CS3 = 1 and CS3, RD/WR = 0 , Bit Clock to THRE THRL to THRE Clock to TSRE tCD tCT tTTHR tTTS 9 CDP1854A


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PDF CDP1854A/3, CDP1854AC/3 TR1602A CDP6402 CDP1800 CDP1854A/3 CDP1854AC/3 CDP1854ACD3 CDP6402 tr1602-a
tft 320 240 qvga color 16,7

Abstract: JASO THP 100 CCP2E25TE NL3224AC35-06 IL-402-30S-S1L-SA 55LHS-3L
Text: film transistor liquid crystal display (a-Si TFT LCD) panel structure with driver LSIs for driving the TFT (Thin Film Transistor ) array and a backlight unit. The a-Si TFT LCD panel structure is injected , 157.3 ns (typ.) Note1 Duty tcd 0.4 - 0.6 - Note1 Rise time, Fall time tcrf , Rise time, Fall time Note2 - Note1: Definition of units is as follows. tcf = 1/tc, tcd = tch , Frequency tcf - 6.4 - MHz 157.3 ns (typ.) Note1 Duty tcd 0.4 - 0.6 -


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PDF NL3224AC35-06 NL3224AC35-06 DE0203 tft 320 240 qvga color 16,7 JASO THP 100 CCP2E25TE IL-402-30S-S1L-SA 55LHS-3L
Supplyframe Tracking Pixel