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Part Manufacturer Description Datasheet Download Buy Part
TPS51219RTET Texas Instruments High Performance, Single Sync Step-Down Controller with Differential Voltage Feedback 16-WQFN -40 to 85
LMH1219RTWT Texas Instruments 12G-SDI Adaptive Cable Equalizer With Integrated Reclocker 24-WQFN -40 to 85
TPS71219DRCR Texas Instruments Dual 250 mA Output, UltraLow Noise, High PSRR, Low-Dropout Linear Regulator 10-VSON -40 to 125
TPS71219DRCRG4 Texas Instruments Dual 250 mA Output, UltraLow Noise, High PSRR, Low-Dropout Linear Regulator 10-VSON -40 to 125
TPS71219DRCT Texas Instruments Dual 250 mA Output, UltraLow Noise, High PSRR, Low-Dropout Linear Regulator 10-VSON -40 to 125
TPS71219DRCTG4 Texas Instruments Dual 250 mA Output, UltraLow Noise, High PSRR, Low-Dropout Linear Regulator 10-VSON -40 to 125
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Traco Power
TRA 1-1219 Iso DC-DC Converter; Vin 10.8 to 13.2Vdc; Vout 9Vdc; I/O isolation 1000Vdc TRA 1-1219 ECAD Model
Distributors Part Package Stock Lead Time Min Order Qty 1 10 100 1,000 10,000
Allied Electronics & Automation TRA 1-1219 Bulk 0 10 - $6.2 $5.1 $4.75 $4.75 More Info
RS Components (2) TRA 1-1219 Bulk 5 1 $6.148 $5.589 $4.978 $4.978 $4.978 More Info
TRA 1-1219 Tube 0 10 - $5.31 $4.886 $4.513 $4.513 More Info

TRA 1-1219 datasheet (1)

Part ECAD Model Manufacturer Description Type PDF
TRA 1-1219 TRA 1-1219 ECAD Model Traco Power Power Supplies - Board Mount - DC DC Converters - DC DC CONVERTER 9V 1W Original PDF

TRA 1-1219 Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
2010 - TRA 1-2411

Abstract: tra 1-0519 2411 DC/DC tra1 TRA 1-0511
Text: TRA 1-1211 TRA 1-1219 5 VDC 9 VDC 200 mA 110 mA Casing TRA 1-1212 12 VDC 84 mA , DC/DC Converters SIP-Package TRA -1 Series www.tracopower.com 1W Semi-regulated output , for 12V input models 3% typ for 24V input models TRA 1-0511 TRA 1-0519 Ripple & Noise 30 mVpk-pk typ. (20 MHz BW) Short circuit protection limited 0.5 sec. Input voltage TRA 1-0513 200 mA 110 mA 12 VDC 84 mA 15 VDC 67 mA TRA 1-0521 ± 5 VDC ± 100 mA TRA


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PDF 24Vin TRA 1-2411 tra 1-0519 2411 DC/DC tra1 TRA 1-0511
1995 - mm58274b

Abstract: MM58274 MM58274CN C1995 johnson counter MM58274CV MM58274CJ MM58274C MM58174A J16A
Text: 140 300 ns tRW Read Strobe Width (Note 3 Note 7) tRA Address Bus Hold Time from


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PDF MM58274C MM58274C MM58174A MM58274 mm58274b MM58274CN C1995 johnson counter MM58274CV MM58274CJ J16A
2011 - MM58274C

Abstract: MM58274 MM58174
Text: tAD tCSD tRD tRW tRA tCSH tRH tHZ Address Bus Valid to Data Valid Chip Select On to Data Valid Read


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PDF MM58274C MM58274C SNOS618A MM58174A MM58274 MM58174
Not Available

Abstract: No abstract text available
Text: PCB-Mounted Receptacle Assemblies Low-Profile, Vertical, Through-Mount, Single-Row 2 .5 4 m m (0.100 in.) C enterline DUBOX™ System Vertical Card Connectors Features ■S tandoffs fo r easy cleaning. ■Low p ro file [(7.0 m m (0.276 in.)] a llo w s clo se r stacking o f parallel c irc u it boards. O ptions Berg Electronics Products Page ■BergS tik* h e a d e rs . 13-50 ■S tra ig h t 4-w all h e a d e rs . 13-80 ■R ight-angle 4-w all


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44-PIN dice

Abstract: No abstract text available
Text: No Change -1 = L O W -to -H IG H le v e l tra n s itio n Data Input LE OE Q Output


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PDF 32-Channel HV8308DJ HV8408DJ HV8308PJ HV8408PJ HV8308X HV8408X 44-pin 44-PIN dice
2010 - TSR 1-2450

Abstract: TMR 6-2411WI 12-0-12 transformer 500ma TRACOPOWER ten 5-1211 traco tma 1212d TEN 3-1213 TRACO POWER traco ten5 application note TSR 3-2450 tmr2e TEP-160
Text: I/O isolation test voltage 1000VDC TRA 1-1211 TRA 1-1219 5 VDC 9 VDC 200mA 110mA , Input Range 29 TMR-3WI Series NEW unregulated Output 1W TMH Series NEW 1W TRA , TMA 1515S TMA 1505D TMA 1512D TMA 1515D TMA 2405S Semi-regulated models See TRA -1 series page , , www.tracopower.com/products/tme.pdf 21 DC/DC Converters SIP-Package www.tracopower.com TRA -1 Series 1 , models TRA 1-0511 TRA 1-0519 Ripple & Noise 30 mVpk-pk typ. (20 MHz BW) Short circuit


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Not Available

Abstract: No abstract text available
Text: designed to be used with a PLL IC to provide a fu lly functional FM tra n s­ ceiver. T he chip is , itte r circuits. T X E N A B L > 2 .0V powers up all tra n s­ m itter functions. T X ENABL<1 .OV tu , J O-HWV- (T TX ENABL ^ 4 0 kQ RF o utput pin for the tra n sm itte r electronics , ground connection shared by the input stage of the tra n s­ m it pow er am p lifier and the receiver RF , itte r pow er am p ia also reduced w ith o utput power. NOTE: T his pin M U S T be low w hen the tra


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PDF RF2945 F2945 32-lead 915MHz RF2945
8248

Abstract: DAC8248
Text: tching and tra cking over the full operating tem per ature range. T h e DAC consists of tw o th in -film , irc u itry and 24 single-pole, d o u b le -th ro w N M O S tra n sistor cu rre n t switches. Figure 1 show s a sim p lifie d c irc u it fo r the R-2R ladd er and tra n sisto r sw itches fo r a single DAC. R is typ ica lly 11kfl. The tra n sisto r sw itches are b ina rily scaled in size to m aintain a con stant voltage d rop across each sw itch. Figure 2 shows a single N M OS tra n sisto r switch. FIG U R E


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PDF 12-BIT DAC-8248 12-bit DAC-8248 MC6809 MC68008 8248 DAC8248
1997 - matsushita servo motors

Abstract: sony led tv electronic diagram filter 465 KHz magnetic head for tape recorder philips 6975 Mahr C166 80C166 video-on-demand 1996 vhs motor drum
Text: manufacturing, it represents an important aid to testing and adjusting equipment. c Tra 0 1 k2 k2 c Tra c Tra 8 9 k1 k1 c Tra c Tra c Tra 6 7 k1 k1 c Tra 4 5 k1 k1 3 2 f0 f2 f0 f0 f2 f0 f0 f1 f2 1 f0 f0 A c Tra c Tra k1 c Tra c Tra k1 0 1 k1 k1 c Tra c Tra k8 k9 c Tra c Tra k7 c Tra c Tra k6 k5 c Tra c Tra k4 k3


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PDF 16-bit matsushita servo motors sony led tv electronic diagram filter 465 KHz magnetic head for tape recorder philips 6975 Mahr C166 80C166 video-on-demand 1996 vhs motor drum
F6856

Abstract: No abstract text available
Text: ra lle l d a ta fro m th e CPU in to a c o n tin u o u s se ria l d a ta s tre a m for tra n s m is s , tra n s fe r w ith E. R ead /W rite: A HIG H level a llo w s d a ta fro m th e a d d re s s e d re g , n tra n s fe r be tw een the d a ta bus and th e a d d re s s e d re g is te r w hen the CE in p u t , lock: TC LK p ro v id e s tim in g fo r th e tra n s m itte r lo g ic . TC LK fre q u e n c y is th e sam e a s th e tra n s m itte d ba ud rate. T ra n s m itte r S erial O u tp u t: TSO is th e tra n s


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PDF F6856 F3846/F6856 F3846 F6856 t3S46 F6856P, F6856CP, F6856DL F6856DM
2sd526 equivalent

Abstract: No abstract text available
Text: ratin g s of tra n sisto rs are one of the most im portant factors in determ ining the effective tra n sisto r drive and in expecting sufficiently high reliability of tra n sisto r cir cuits over intended , increase of am bient tem p e ra tu re in tu rn will increase conductivity of the tra n sisto r or c u rre n t flow in the device. Thus, increased power dissipation of the tra n sisto r fu rth e r raises the , aterials, stru ctu re, design, and fabricating conditions of tra n sis tors, differ according to the kinds


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Not Available

Abstract: No abstract text available
Text: CSM A/CD side addresses for accessing m em ory during tra n sm it and receive operations. Generate M M , receive packet. W rite tra n sm it status w o rd in firs t locations o f tra n sm it packet. Determ ine if enough m em ory is available fo r reception. De-allocate tra n sm it m em ory a fte r suitable com , fo r tra n s m it and receive in order to allo w full-duplex operation. M M U requests fo r , tra n s m it FIFO fo r enqueuing the packet. Conversely if there is free m em ory fo r receive, there


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PDF pre-10BASE-T
Not Available

Abstract: No abstract text available
Text: three fe a tu re s : the random access port, se ria l port, and tra n s fe r cycles. (1) Random , c k w rite cycle, or w rite d a ta tra n sfe r cycle. D esigners can use th is fu n ctio n to , a d ata tra n sfe r. For d eta ils, see C H A P T E R 4 S E R IA L PO R T A N D D ATA TR A N S F E , The d a ta tra n s fe r cycle is the cycle during w hich d ata is tra n s fe rre d betw een the random , Types of data transfer cycles As show n below , th e re are tw o types o f d a ta tra n sfe r, each


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68hc551

Abstract: No abstract text available
Text: m o f th e c irc u it is illu s tra te d in fig u re 1. T h e in te rn a l b au d ra te g e n e ra , process or u n til a m a ste r reset is perform ed. The c o n te n ts o f th e tra n s m it and receive data registers are n o t a ffe c te d by th e reset fu n c tio n . Transmit Data Data to be tra n s m itte d is loaded in to th e tra n s m it data register (TDR). It is th e n tra n s fe rre d to th e tra , th e TDR be fore th e fir s t ch a ra cte r has been tra n s m itte d . The second c h a ra cte r is


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PDF C68HC551 68hc551
MSM518122-JS/ZS

Abstract: No abstract text available
Text: reference levels for m easuring tim ing of input signals. Also, tra n sitio n tim e s are m easured betw , n tio na l C)E sign a l fu n ctio n, a d a ta tra n sfe r o peration is started betw een the R A M , te rm in e s the dire ctio n of d a ta tra n sfe r betw e e n the R AM and SAM . W hen W E /W E is "high" at th e fallin g e dge o f RAS, the d ata is tra n sfe rre d from R AM to SAM ( read tr a n s fe , to R AM (w rite tra n s fe r). OKI SEMICONDUCTOR 35 ■M SM 518122-JS/ZS ■W rite M


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PDF MSM518122-JS/ZS 518122-JS/ZS MSM518122-JS/ZS
Not Available

Abstract: No abstract text available
Text: M A C A IR d a ta c o n fig u re d d a ta bus. T he N H M 5 1 3 tra n s c e iv e r is s p e c ific a , c ific a tio n s : A-3818, A-5232, A-5690, a n d A-4905 The tra n s m itte r s e c tio n o f th is u , ord er c o m p o n e n ts o f the tra n s m is s io n in a c c o rd a n c e w ith th e M A C A IR s p , . The NHI-1514 tra n s m is s io n . tra n sce ive r p ro d u ce s a tra p e zo id a l w a ve fo rm d , The N H I-1515 tra n s c e iv e r is id e n tic a l to th e N HI-1513 u n it b u t it in c o r p o ra


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PDF NHI-1500 I-1515
AC emi filter 240V

Abstract: No abstract text available
Text: . U nexpected m ains voltage tra nsients are now being recognized as a s ig n ific a n t fa c to r in , instantaneous tra nsients and subtle factors w ith in and external to the pow er sup ply. . . The fo llo w in g , power su p p ly design: {1) Put voltage tra nsient pro te c tio n on the inpu t pow er lines." W ith th , signed w ith assurance th a t fa ilu re caused by power line tra nsients are rare. The standard spe cifie , tha t lig h t ning induced tra nsients propog ate th ro u g h a system as a c u rre n t source


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Not Available

Abstract: No abstract text available
Text: dependent upon the num ber of address tra nsitions. S pecified loD (m ax) 's measured w ith a m axi­ mum of tw o tra nsitions per address in p u t per random cycle, one tra nsition per access cycle in S tatic Column Mode. 5. S pecified V|_(mj n) is steady state operation. During tra nsitions, V|[_ may , c e d to th e la te r o f RAS. C A S . a nd Q E lo w tra n s itio n f. a nd tQ H 9 fe re fe re n c e d to th e e a rlie r of C A S o r OE h ig h tra n s itio n g T ra n s itio n is m e a s u re d


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PDF C259HL 51C259HL
Not Available

Abstract: No abstract text available
Text: Transmit Interface Signals 0 I I 0 Transm it Clock. Tra n sm it C lo ck is d ata tra nsm it bit clock. Alt tra nsm it interfa ce signals are synchronized to this clock. This signal is always active. Tra n sm it Data. Tra n sm it D ata is the serial tra nsm it data. R equest to S end. T he com m u nicatio n c o n tro lle r in dicate s th a t it w ish e s to tra nsm it d ata by a sserting R equest to Send. O , asserts C lear to Send w hen it can enco de and tra nsm it d ata on th e channel. RTS ÜT5 Controller


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PDF Am7960 500Kbps Am7960 4533A
E 13007-1

Abstract: NS8250 ns455 j 13007-1 R600B TP3311 TP3320 AT-600-B sec E 13007-1
Text: to the power-up mode. In a p plication s where tra nsm ission tow ard the telephone line is not , OSCOUT, CLKX and CLK r remain in a low im ped ance high or low state. TRANSMITTER The tra n s m itte r con sists o f a d ig ita lly c o n trolled fre quency m o dulator follow ed by a tra n s m it sw , am p lifie r can d ire ctly drive a tra nsform er or DAA coupler to the telephone line. In order to , o-w ire line, the only operating mode is half-duplex w ith sp lit baud rates: when the MODEM tra n sm


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PDF TP3310/TP3311 /TP3320/TP3321 /TP3320/TP3321 TP3320 TP3321 20-pin E 13007-1 NS8250 ns455 j 13007-1 R600B TP3311 AT-600-B sec E 13007-1
Not Available

Abstract: No abstract text available
Text: D IC tra n s m its and receives data (in fo rm a tio n or c o n tro l) in a fo rm a t called a fram , field o f th e fram e. T h e A D L C tra n s m itte r generates a fla g p a tte rn in te rn a lly and , are no t tra n sfe rre d to th e Rx FIFO. T h e d e te c tio n o f a fla g is in ­ d ica te d b y , precedes th e FCS field. T he l-fie ld c o n ta in s " d a ta ” to be tra n sfe rre d b u t is n o t alw , ining b its o f th e receiver s h ift register w ith zeros, and tra n s fe r a fu ll b y te to th e Rx


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PDF MC6854 MC6854S MC6854CS MC68A54S MC68A54CS MC68B54S MC6854P MC6854CP MC68A54P MC68A54CP
Not Available

Abstract: No abstract text available
Text: maxi­ mum of tw o tra nsitions per address inpu t per random cycle, one tra nsition per access cycle in Static Column Mode. 5. S pecified V|L(mjn ) is steady state operation. During tra nsitions, V |L , q u T e 'S re fe re n c e d to th e la te r o f RAS. CAS. a nd O E lo w tra n s itio n f 1 ^ 2 a nd tO H a re re fe re n c e d to th e e a rlie r of C A S o r OE h igh tra n s itio n g. T ra n s , refe ren ce to t he late r o f the 6 X 5 or W £ low tra n s itio n . _ d. If th e low tra n sitio


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PDF 51C259H 51C259H
Not Available

Abstract: No abstract text available
Text: and tra n s p o rt fu n c tio n as a separate gate electrode requiring m u ltip le layers and m u ltip , tra n sfe r gate storage w e ll w hen the tra nsfer gate voltage goes high. W hen the tra n s fe r gate voltage goes lo w , the charge is transferred into the CCD tra n sp o rt s h ift register. The tra , enter the end-of-scan (EOS) s h ift registers to create the end-of-scan signal. In addition, the tra , reference signals. shift registers There are tw o CCD tra n s p o rt registers, one on each side o f th e


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13282AP

Abstract: No abstract text available
Text: 100 M H z B andw idth 3.5 ns R ise/Fall Time S ub con tra st C ontrol for Each C hannel B lanking and , request. RECOMMENDED OPERATING CONDITIONS Characteristic P o w e r S u p p ly V oltag e C o n tra s t , iü h ii 7j[] B Clamp S u b c o n tra s t C o n tro l B la n k in g Inp ut S ig n a l A m p litu , Internal DC B ias V oltage O u tp u t S ignal A m p litu d e V oltage G ain C o n tra s t C ontrol V2, V4 , n tra s t C ontrol V1, V3, V 5 = 5.0 to 0 V V 1 3 = 5.0 V V2, V4, V 6 = 0.7 V pp Vo u t = 4.0 V pp R


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PDF MC132B2A/D C13282A 3282A ------------------------------1PHX36133-0 MC13282A/D 13282AP
Not Available

Abstract: No abstract text available
Text: KS5824 includ es select, enable, read/write, in te rru p t and bus inte rface lo gic to a llow data tra n , ratios, tra n s m it c o n tro l, receive c o n tro l, and in te rru p t co n tro l. For peripheral o r m , , Rx CLK, RAW, RS, Rx Data, CSo, CS, CS2, CTS, DCD RTS, Tx Data O utput C apacitance IRQ · Under tra n , is not selected · 500 kbps · U nder non tra n s m ittin g and re ceiving operatio n · Input level (E , pen den t clo c k s , and three peripheral/m odem c o n tro l lines. CMOS INTERGRATED CIRCUIT tra


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PDF KS5824 KS5824
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