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2003 - Au1500

Abstract: AU1100 pci controller alchemy
Text: PCI clock), and the SDRAM interface at 99MHz ( 10.1ns per SDRAM clock). The operating frequencies of , access). This yields 4*15.2ns + 5*5.1ns + 6* 10.1ns or 146.9ns for PCI device initiated single-beat read , arbitration, and 6 SDRAM clocks for a single-beat write). This yields 6*15.2ns + 5*5.1ns + 6* 10.1ns or , This yields 14*15.2ns + 5*5.1ns + 12* 10.1ns or 359.5.1ns for PCI device initiated burst read access to , 12* 10.1ns or 344.3ns for PCI device initiated burst write access to Au1500 SDRAM. At 344.3ns per


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PDF Au1500TM 0275A Au1000TM, Au1100TM Au1500 AU1100 pci controller alchemy
Not Available

Abstract: No abstract text available
Text: 10±1NS 1 5 ± .8NS 30 + 1.2NS 45 ± 1.6NS 60+1.8NS 75 + 2.0NS 90 + 2.4NS 105±2.8NS 120±3.2NS 135±3.6NS


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PDF Input0453-0100-04 100NS 125NS 140NS 155NS 432-0463/TWX 710-730-5301/FAX
L83-103

Abstract: L83-102 83111 L8312 L83-105 L8311 83118
Text: -83-110 PULSE WIDTH @ 1.5V LEVEL 5.0 ± 1ns 6.0 ± 1ns 7.0 ± 1ns 8.0 ± 1ns 9.0 ± 1ns 10±1ns 15± 1ns 20 ± 1ns 25 ±


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PDF L-83-100 100ns L-83-1XX L-83-101 L-83-102 L-83-103 L-83-104 L-83-105 L-83-106 L-83-107 L83-103 L83-102 83111 L8312 L83-105 L8311 83118
1996 - Not Available

Abstract: No abstract text available
Text: . tFALL = 10.1ns tFALL = 10.1ns 50mV /DIV OUTPUT IN0 = +1V IN1 = ­1V RL = 1k SELECT PULSE 0 TO , ! ESD SENSITIVE DEVICE REV. 0 ­3­ AD8180/AD8182­Typical Performance Curves tFALL = 10.1ns tFALL = 10.1ns VIN = 50mV rms RL = 5k 1.0 NORMALIZED FLATNESS ­ dB 8180R 1 8182R 0 ­1 ­2 ­3 ­4 ­5


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PDF AD8180) AD8182) AD8180/AD8182
1996 - ccd board Circuit Schematic Diagram Electronic

Abstract: 12 line ccd scanner cmos logic 4000 series AD8180 schematic diagram 800 watt power amplifier picture-in-picture AD8182AN 780 AC 446V 10k resistor 1/4 watt datasheet
Text: Z tFALL = 10.1ns 50mV /DIV tFALL = 10.1ns OUTPUT IN0 = +1V IN1 = ­1V RL = 1k , 8182R IN0 = +1Vdc IN0 = ­1Vdc NORMALIZED OUTPUT ­ dB tFALL = 10.1ns tON = 10.5ns tOFF , ­0.4 10ns/DIV 0.0 NORMALIZED OUTPUT ­ dB tFALL = 10.1ns ­7 Figure 5. Enable and


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PDF AD8180/AD8182 AD8180) AD8182) AD8180 AD8182 14-Lead ccd board Circuit Schematic Diagram Electronic 12 line ccd scanner cmos logic 4000 series AD8180 schematic diagram 800 watt power amplifier picture-in-picture AD8182AN 780 AC 446V 10k resistor 1/4 watt datasheet
2001 - 99716M

Abstract: DML D01 0103ma 5502M 5807m 1058.20 5121M 74297 0808mA 74481
Text: No file text available


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PDF ------------------------27V 99716M DML D01 0103ma 5502M 5807m 1058.20 5121M 74297 0808mA 74481
2003 - AU1100

Abstract: amd alchemy au1100 a/S3C9004/P9004/C9014/Reset Software for Alchemy Au1000 Processor QVGA GRAPHICS LCD DISPLAY alchemy AMD AU1000 MIPS32 lcd qvga 320x240 Au1500 Au1000
Text: controller at 99MHz, an SDRAM singlebeat access is 60ns (6 cycles at 10.1ns ), and an SDRAM burst access is 121ns (12 cycles at 10.1ns ). Accesses to SDRAM can add upwards to 121ns to the system bus latency for


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PDF Au1100TM 0274A Au1100 Au1000, Au1500 amd alchemy au1100 a/S3C9004/P9004/C9014/Reset Software for Alchemy Au1000 Processor QVGA GRAPHICS LCD DISPLAY alchemy AMD AU1000 MIPS32 lcd qvga 320x240 Au1000
IC 3160

Abstract: No abstract text available
Text: ) 10.1ns = ( 0 .8 + 1 .8 + 3 .6 )+ (1 .1 )+ (1 .2 + 1.6) T a b le 2 - 0 0 4 2 /3 1 6 0 N ote: C a lcu


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PDF 60-70LM IC 3160
Not Available

Abstract: No abstract text available
Text: (3.8) - (0.2 + 0.7 + 7.5) 4.6 ns th 0.7 ns tco 10.1ns = Clock (max) + Reg co + Output =


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PDF 032V/LV 032V-100LJ44 032V-100LT44 032V-80LJ44 2032LV-80LJ* 032V-80LT44 2032LV-80LT44* 032V-60LJ44 2032LV-60LJ* 032V-60LT44
2002 - MD2810-D08

Abstract: Diskonchip MD2811-D32 MD2810 Diskonchip Millennium Plus MD-2810-D08 Millennium AP-DOC-054 AP-DOC-10 MD3831-D16
Text: (min) 18 ns (min) Read access time (RAM)1 130 ns (max) 101ns (max) 111 ns (max) Read


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PDF AP-DOC-056) 16MByte 128Mbit) 32MByte 256Mbit) 32-pin 16/32MB 48-pin 69-ball MD2810-D08 Diskonchip MD2811-D32 MD2810 Diskonchip Millennium Plus MD-2810-D08 Millennium AP-DOC-054 AP-DOC-10 MD3831-D16
2001 - AN006

Abstract: CYNCP80192 CYNSE70032 RFC-2430 "routing tables"
Text: Non-pipelined Pipelined 24ns 24ns 72ns n/a 5ns 5ns 101ns 29ns The CPU will also need to receive and


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Not Available

Abstract: No abstract text available
Text: ) 10.1ns = (0.8 + 1 . 8 + 3 .6 )+ (1.1)+ (1.2 +1.6) Table 2-0042/3160 Note: Calculations are based upon


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PDF 208-Pin 3160-100LM 3160-70LM 3160-125LM
Z80 INTERFACING TECHNIQUES

Abstract: Z80 application note dynamic ram latch 74574 MUX 74157 MK4116-2 74LSI38 MK4027 16Kx8 static ram ttl mk4116 MK4116-3
Text: , the circuit exceeds the required access time by 101ns (worst case). The circuit shown in Figure 6


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PDF 16-pin C22S00 222D00 322C00 Z80 INTERFACING TECHNIQUES Z80 application note dynamic ram latch 74574 MUX 74157 MK4116-2 74LSI38 MK4027 16Kx8 static ram ttl mk4116 MK4116-3
I3160

Abstract: No abstract text available
Text: #46) 10.1ns = (0.8 + 1.8 + 3.6) + (1.1) + (1.2 + 1.6) Table 2-0042/3160 Note: Calculations are


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PDF 3160-100LM 3160-70LM 3160-125LM 3160-70LM 208-Pin I3160
Not Available

Abstract: No abstract text available
Text: the zero level of the negative and positive transitions are 10.1ns and ±0.5n, respectively. FIG


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PDF OPA623 350MHz, 100V/ns, OPA623 AMPLIFIERS23 10ns/div 17313b5 0024bb3
Not Available

Abstract: No abstract text available
Text: Derivations of tsu, th and tco from the Product Term Clock1 tsu = = = 0.8ns = = = = 4.2ns = = = = 10.1ns =


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PDF P--------125 100MHzfmax 3160-X 0212B/3160 3160-125LQ 3160-125LB272 3160-125LM* 3160-100LQ 3160-100LB272 3160-100LM*
1998 - Not Available

Abstract: No abstract text available
Text: Discontinued (7/00 - last order; 9/00 - last ship) IBM11M32845CB32M x 72 E12/12, 3.3V, Au, EDOMMDL18DSU-001041529. 32M x 72 E13/11, 3.3V, Au, EDOMMDL18DSU-001041529. IBM11M32845CB PRELIMINARY 32M x 72 Chipkill Correct DRAM Module Features · 168-Pin JEDEC Standard, 8-Byte Dual In-line Memory Module · 32M x 72 (Dual Bank) Chipkill Correct EDO DIMM · Performance: tRAC RAS Access Time CAS Access Time 19ns tAA Access Time From Address 34ns tRC Cycle Time 101ns


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PDF IBM11M32845CB32M E12/12, EDOMMDL18DSU-001041529. E13/11, IBM11M32845CB 168-Pin 101ns SA14-XXXX-xx
1997 - Not Available

Abstract: No abstract text available
Text: 3.6) + (4.6) - (0.8 + 1.8 + 4.0) tco = = = 10.1ns = Clock (max) + Reg co + Output (tiobp


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PDF
1999 - B272

Abstract: No abstract text available
Text: 3.6) + (4.6) - (0.8 + 1.8 + 4.0) tco = = = 10.1ns = Clock (max) + Reg co + Output (tiobp


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PDF 0212B/3160 3160-125LQ 208-Pin 3160-125LB272 272-Ball 3160-125LM* 3160-100LQ 3160-100LB272 B272
1999 - 203d6

Abstract: B272
Text: (#24+ #30+ #34) (0.8 + 1.8 + 3.6) + (4.6) - (0.8 + 1.8 + 4.0) tco = = = 10.1ns = Clock (max


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PDF 0212B/3160 3160-125LQ 208-Pin 3160-125LB272 272-Ball 3160-100LQ 3160-100LB272 3160-70LQ 203d6 B272
1998 - B272

Abstract: No abstract text available
Text: 3.6) + (4.6) - (0.8 + 1.8 + 4.0) tco = = = 10.1ns = Clock (max) + Reg co + Output (tiobp


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PDF 0212B/3160 3160-125LQ 208-Pin 3160-125LB272 272-Ball 3160-125LM* 3160-100LQ 3160-100LB272 B272
Not Available

Abstract: No abstract text available
Text: (#39) + (#44 + #46) 10.1ns = (0 .8 + 1 .8 + 3 .6)+ (1.1)+ (1.2 +1 .6 ) Table 2-0042/3160 th tco


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PDF
1998 - B272

Abstract: 203d6
Text: 3.6) + (4.6) - (0.8 + 1.8 + 4.0) tco = = = 10.1ns = Clock (max) + Reg co + Output (tiobp


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PDF 0212B/3160 3160-125LQ 208-Pin 3160-125LB272 272-Ball 3160-125LM* 3160-100LQ 3160-100LB272 B272 203d6
1998 - chipkill

Abstract: No abstract text available
Text: IBM11M32845CB32M x 72 E12/12, 3.3V, Au, EDOMMDL18DSU-001041529. 32M x 72 E13/11, 3.3V, Au, EDOMMDL18DSU-001041529. IBM11M32845CB PRELIMINARY Features · 168-Pin JEDEC Standard, 8-Byte Dual In-line Memory Module · 32M x 72 (Dual Bank) Chipkill Correct EDO DIMM · Performance: tRAC tCAC tAA tRC tHPC RAS Access Time CAS Access Time Access Time From Address Cycle Time EDO Mode Cycle Time -5R 50ns 19ns 34ns 101ns 22ns 32M x 72 Chipkill Correct DRAM Module · Optimized for ECC applications · System


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PDF IBM11M32845CB32M E12/12, EDOMMDL18DSU-001041529. E13/11, IBM11M32845CB 168-Pin 101ns SA14-XXXX-xx chipkill
1999 - B272

Abstract: BC470
Text: ) - (0.8 + 1.8 + 4.0) tco = = = 10.1ns = Clock (max) + Reg co + Output (tiobp + tgrp +


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PDF 0212B/3160 3160-125LQ 208-Pin 3160-125LB272 272-Ball 3160-100LQ 3160-100LB272 3160-70LQ B272 BC470
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