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Part Manufacturer Description Datasheet Download Buy Part
ISO1176TREFERENCE Texas Instruments ISO1176T Reference Design Board
ISL21080-EVALZ Intersil Corporation 300nA NanoPower Voltage References; Package: Eval Board
ISL21010CFH315Z-TK Intersil Corporation Micropower Voltage Reference; SOT3; Temp Range: -40° to 125°C
ISL21010CFH320Z-TK Intersil Corporation Micropower Voltage Reference; SOT3; Temp Range: -40° to 125°C
ISL21010CFH330Z-TK Intersil Corporation Micropower Voltage Reference; SOT3; Temp Range: -40° to 125°C
ISL21010DFH310Z-TK Intersil Corporation Micropower Voltage Reference; SOT3; Temp Range: -40° to 125°C

TMS 3812 cross reference Datasheets Context Search

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2009 - AX125

Abstract: AX2000 CS180 IDTQS32X2384 Silicon Sculptor II Axcelerator FPGAs Axcelerator Family FPGAs
Text: V VCCI DC I/O Supply Voltage ­0.3 to 3.75 V VREF DC I/O Reference Voltage ­0.3 , )* LVTTL 24mA High Slew 35 3.3 381.2 262.6 643.7 LVTTL 16mA High Slew 35 3.3 381.2 220.1 601.3 LVTTL 12mA High Slew 35 3.3 381.2 160.9 542.1 LVTTL 8mA High Slew 35 3.3 381.2 125.4 506.5 LVTTL 24mA Low Slew 35 3.3 381.2 164.2 545.4 LVTTL 16mA Low Slew 35 3.3 381.2 145.9 527.0 LVTTL 12mA Low Slew 35 3.3


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PDF 18-channel AX125 AX2000 CS180 IDTQS32X2384 Silicon Sculptor II Axcelerator FPGAs Axcelerator Family FPGAs
2005 - CQFP 256 PIN actel

Abstract: No abstract text available
Text: Voltage DC I/O Reference Voltage Input Voltage Output Voltage Storage Temperature Supply Voltage for , 3.3 3.3 3.3 3.3 2.5 1.8 381.2 381.2 381.2 381.2 381.2 381.2 381.2 381.2 218.8 113.4 262.6 220.1 160.9 , rates. jc values are provided for reference . The absolute maximum junction temperature is 125°C. The , more information. VCCDA should be tied to 3.3V. VCCPLA/B/C/D/E/F/G/H Supply Voltage Reference , to 1.5V whether PLL is used or not. VCOMPLA/B/C/D/E/F/G/HSupply Voltage Compensation reference


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PDF 18-channel CQFP 256 PIN actel
2008 - FBGA 896

Abstract: AX125 AX2000 CS180 IDTQS32X2384 Silicon Sculptor II Axcelerator Family FPGAs
Text: V VCCI DC I/O Supply Voltage ­0.3 to 3.75 V VREF DC I/O Reference Voltage ­0.3 , )* LVTTL 24mA High Slew 35 3.3 381.2 262.6 643.7 LVTTL 16mA High Slew 35 3.3 381.2 220.1 601.3 LVTTL 12mA High Slew 35 3.3 381.2 160.9 542.1 LVTTL 8mA High Slew 35 3.3 381.2 125.4 506.5 LVTTL 24mA Low Slew 35 3.3 381.2 164.2 545.4 LVTTL 16mA Low Slew 35 3.3 381.2 145.9 527.0 LVTTL 12mA Low Slew 35 3.3


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PDF 18-channel FBGA 896 AX125 AX2000 CS180 IDTQS32X2384 Silicon Sculptor II Axcelerator Family FPGAs
1999 - Texas Memory Systems

Abstract: 0x609f sam 5000 manual NET10 0xF8000000
Text: . 1.1 Related Texts The following Texas Memory Systems user manual may be useful for reference purposes , continually checks the correctness of the reference buffers to detect the presence of memory or DMA errors , several output buffers. The results of these computations are compared to previously captured reference , reference buffer, an error is flagged. The data that are compared to a reference are the floating-point , with its reference , it is capable of pinpointing the location in the test buffer where the error


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PDF EXACT450 SAM-450 Exact450 0x13/0x1b SAM-450 Texas Memory Systems 0x609f sam 5000 manual NET10 0xF8000000
2003 - casio tv 1400

Abstract: LCD tv display pinout diagram ST20 boot Matrix CCD "line sensor" Epson Epson matrix ccd line BGA196 Casio 1.8 colour TFT SENSOR rgb f13 Casio 1.8" colour TFT ST20 manual
Text: UXGA CMOS digital still cameras. ST supplies complete reference designs including the sensor and , LCD interface TV interface: total 5 pins UOUT D12 CVBS out REXT B14 TV Reference voltage GNDA REXT B13 TV Reference voltage TV VDDA C14 TV core supply 1.8V TV VSSA , : total 2 pins LOW BATT A13 Sense the battery level BATT VREF B11 Reference for the , pins VP TDI C4 JTAG TDI EWARP VP TDO B3 JTAG TDO EWARP VP TMS C3 JTAG TMS


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PDF STV0684 casio tv 1400 LCD tv display pinout diagram ST20 boot Matrix CCD "line sensor" Epson Epson matrix ccd line BGA196 Casio 1.8 colour TFT SENSOR rgb f13 Casio 1.8" colour TFT ST20 manual
1997 - INTELDX4 write-through

Abstract: Intel486TM PROCESSOR FAMILY A80486DX2SA66 SB80486DX2SC50 240486 CACHE MEMORY FOR 8086 D18153 SB80486DX2SC-50 AP-485
Text: . 6 Table 4. Pin Cross Reference for 208-Lead SQFP Package , . 12 Table 7. Pin Cross Reference for 168-Pin PGA Package , . 6 Table 4. Pin Cross Reference for 208-Lead SQFP Package , . 12 Table 7. Pin Cross Reference for 168-Pin PGA Package , Package (pg. 6) · Table 4, Pin Cross Reference for 208-Lead SQFP Package (pg. 8) 168-Pin PGA - Pin Grid


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PDF 32-Bit 208-Lead 168-Pin 16-bit 64-Bit INTELDX4 write-through Intel486TM PROCESSOR FAMILY A80486DX2SA66 SB80486DX2SC50 240486 CACHE MEMORY FOR 8086 D18153 SB80486DX2SC-50 AP-485
2009 - MPC5604C

Abstract: mpc5604b SPC560B4 SPC560C4 linflex spc560b Nexus S JTAG freescale
Text: . . . . . . . . . . . . . 15 CTU ( Cross Triggering Unit) . . . . . . . . . . . . . . . . . . . . . , This document is not intended to replace the reference manual or device errata list and differences pointed out in this document should be cross referenced with the relevant sections in the latest reference manual and errata document. The table below shows the full part numbers and device , reference manual. 2 Summary of Differences This section gives a summary of all the differences


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PDF AN3864 MPC5604B/C SPC560B/C4 e200Z0 MPC5604B MPC5604C SPC560B4 SPC560C4 MPC5604C SPC560C4 linflex spc560b Nexus S JTAG freescale
2001 - ddr1 ram

Abstract: No abstract text available
Text: Clock Input Rise & Fall Time 2.0 V/ns Clock Input Reference Level CK/CK cross V Output , HSTL-compatible I/O interface with dedicated input reference voltage (VREF): VDDQ/2 typical · DDR1 functional , VDDQ V SS T DQ DQ SA V SS SA0 V SS SA DQ DQ U VSS VDDQ TMS , VDDQ TMS TDI TCK TDO RSVD (2) VDDQ V SS Notes: 1. Pad Location 6L is a true , . VDDQ Output Power Supply - Output buffer supply voltage. VREF Input Reference Voltage - Input


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PDF CXK77Q36162AGB CXK77Q18162AGB CXK77Q36162AGB BGA153-P-1422 200mA 250mA ddr1 ram
1997 - BGA-153P-021

Abstract: sony bus control BGA153-P-1422
Text: Fall Time 2.0 V/ns Clock Input Reference Level CK/CK cross V Output Reference Level , interface with dedicated input reference voltage (VREF): VDDQ/2 typical · DDR1 functional compatibility · , VDDQ VSS T DQ NC SA VSS SA0 VSS SA DQ NC U VSS VDDQ TMS , supply voltage. VREF Input Reference Voltage - Input buffer threshold voltage. VSS Ground TCK Input JTAG Clock TMS Input JTAG Mode Select - Weakly pulled "high" internally


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PDF CXK77Q18162AGB CXK77Q18162AGB All35 BGA-153P-021 BGA153-P-1422 BGA-153P-021 sony bus control BGA153-P-1422
1997 - A80486DX4WB100

Abstract: INTEL A80486DX4WB100 240486 A3232 intel A3260 FC80486DX4WB100 INTELDX4 PROCESSOR A3232-01 241618 Intel486TM PROCESSOR FAMILY
Text: . 6 Table 4. Pin Cross Reference for 208-Lead SQFP Package , . 12 Table 7. Pin Cross Reference for 168-Pin PGA Package , -Lead SQFP Package (pg. 6) · Table 4, Pin Cross Reference for 208-Lead SQFP Package (pg. 8) 168-Pin PGA - , Assignment for 168-Pin PGA Package (pg. 12) · Table 7, Pin Cross Reference for 168-Pin PGA Package (pg. 14 , Embedded Write-Back Enhanced IntelDX4TM Processor Table 4. Pin Cross Reference for 208-Lead SQFP Package


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PDF 32-Bit 208-Lead 16-Kbyte 168-Pin 16-bit 64-Bit A80486DX4WB100 INTEL A80486DX4WB100 240486 A3232 intel A3260 FC80486DX4WB100 INTELDX4 PROCESSOR A3232-01 241618 Intel486TM PROCESSOR FAMILY
2002 - Not Available

Abstract: No abstract text available
Text: HSTL-compatible I/O interface with dedicated input reference voltage (VREF): 0.75V typical · DDR1 functional , VSS DQ VSS DQ VSS DQ VSS DQ VSS NC (x18) VDD SA TMS 4 SA V SS SA V SS VDD VDD V SS VDD VDD V SS LBO , Supply - Core supply voltage. Output Power Supply - Output buffer supply voltage. Input Reference Voltage , Input Input ZQ Input VDD VDDQ VREF VSS TCK TMS TDI TDO RSVD NC Input Input Input Output JTAG , ) Input Voltage (TCK, TMS , TDI) Operating Temperature Junction Temperature Storage Temperature Symbol VDD


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PDF CXK77Q36162GB CXK77Q36162GB 750mA 700mA
2002 - CXK77L18162GB

Abstract: CXK77L18162GB-25 CXK77L18162GB-27 CXK77L18162GB-3
Text: Time 2.0 V/ns Clock Input Reference Level CK/CK cross V Output Reference Level 0.9 , reference voltage (VREF): VDDQ/2 typical · DDR1 functional compatibility · Register - Register (R-R) read , VDDQ TMS TDI TCK TDO RSVD (2) VDDQ V SS Notes: 1. Pad Location 6L is a true , Power Supply - Output buffer supply voltage. VREF Input Reference Voltage - Input buffer threshold voltage. VSS Ground TCK Input JTAG Clock TMS Input JTAG Mode Select - Weakly


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PDF CXK77L18162GB CXK77L18162GB 860mA 880mA 940mA 940mA 1000mA 980mA 780mA 830mA CXK77L18162GB-25 CXK77L18162GB-27 CXK77L18162GB-3
2002 - CXK77L18162AGB-25

Abstract: CXK77L18162AGB-27 CXK77L18162AGB-3 ddr1 ram
Text: 0.75 V Clock Input Rise & Fall Time 2.0 V/ns Clock Input Reference Level CK/CK cross , reference voltage (VREF): 0.75V typical · DDR1 functional compatibility · Register - Register (R-R) read , VDDQ TMS TDI TCK TDO RSVD (2) VDDQ V SS Notes: 1. Pad Location 6L is a true , Power Supply - Output buffer supply voltage. VREF Input Reference Voltage - Input buffer threshold voltage. VSS Ground TCK Input JTAG Clock TMS Input JTAG Mode Select - Weakly


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PDF CXK77L18162AGB CXK77L18162AGB BGA-153P-021 BGA153-P-1422 CXK77L18162AGB-25 CXK77L18162AGB-27 CXK77L18162AGB-3 ddr1 ram
1995 - A10186

Abstract: INTELDX4 PROCESSOR A80486DX4WB100 A80486 240486 FC80486DX4WB100 A3232-01 A80486DX4WB-100 WB75 fc80486dx4
Text: . 6 Table 4. Pin Cross Reference for 208-Lead SQFP Package , . 12 Table 7. Pin Cross Reference for 168-Pin PGA Package , ) · Table 4, Pin Cross Reference for 208-Lead SQFP Package (pg. 8) 168-Pin PGA - Pin Grid Array · , Package (pg. 12) · Table 7, Pin Cross Reference for 168-Pin PGA Package (pg. 14) 3 A 208 207 , 4. Pin Cross Reference for 208-Lead SQFP Package (Sheet 1 of 2) Address Pin # Data Pin #


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PDF 32-Bit 208-Lead 16-Kbyte 168-Pin 16-bit 64-Bit A10186 INTELDX4 PROCESSOR A80486DX4WB100 A80486 240486 FC80486DX4WB100 A3232-01 A80486DX4WB-100 WB75 fc80486dx4
Not Available

Abstract: No abstract text available
Text: Input reference level 2.0/0.8V Clock input reference level K/K cross ; C/C cross Clock input , TCK JTAG Clock M1, M2 Mode Select K Negative Clock TMS JTAG Mode Select NC , /ns * 2 For Output reference level 1.4V Output load conditions Fig. 1 3.3V i/o , . TMS input pin controls the state transition of 16 state TAP controller as specified in IEEE std. 1149.1. Inputs on TDI, TMS are registered on the rising edge of TCK clock and the output data on TDO is


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PDF CXK77B3610GB CXK77B3610GB-6/7 CXK77B361OGB-6 166MHz CXK77B361OGB-7 142MHz 119TBGA 19P-01
2011 - linky

Abstract: No abstract text available
Text: and Mounting Techniques Reference Manual, SOLDERRM/D. This document contains information on a , resistor. The Schottky diode pair D5 clamps the voltage within the input range of the zero cross detector , C11 High Voltage coupling capacitor; 630 V 220 ±20% nF C12 Zero Cross noise , Low pass transmit filter R10 TX Coupling resistor ; 0.5 W R11 3 Zero Cross coupling HiV , Pins: TX_OUT, ALC_IN, RX_IN, RX_OUT, REF_OUT, ZC_IN, XIN, XOUT, TDO, TDI, TCK, TMS , TRSTB, TEST


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PDF NCN49597 NCN49597 NCN49597/D linky
2004 - X80486DX4WB100

Abstract: 240486 INTELDX4 PROCESSOR 273021
Text: . 6 Table 4. Pin Cross Reference for 208-Lead SQFP Package , . 12 Table 7. Pin Cross Reference for 168-Pin PGA Package , Cross Reference for 208-Lead SQFP Package (pg. 8) 168-Pin PGA - Pin Grid Array · Figure 3, Package , Table 7, Pin Cross Reference for 168-Pin PGA Package (pg. 14) 3 208 207 206 205 204 203 , Write-Back Enhanced IntelDX4TM Processor Table 4. Pin Cross Reference for 208-Lead SQFP Package (Sheet 1


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PDF 32-Bit 208-Lead 16-Kbyte 168-Pin 16-bit 64-Bit X80486DX4WB100 240486 INTELDX4 PROCESSOR 273021
2005 - Not Available

Abstract: No abstract text available
Text: Internal Reference and Five Differential Analog Inputs 12-Bit D/A Converter 16-Bit Timer_A With Three , ) TDO/TDI TDI/TCLK TMS TCK RST/NMI DVCC DVSS XIN XOUT AVSS AVCC VREF P6.0/A0+ P6.1/A0- P6.2/A1+ P6.3/A1 , · DALLAS, TEXAS 75265 COM0 DVCC TMS TCK 3 MSP430F42x0 MIXED SIGNAL , TMS TCK TDI/TCLK TDO/TDI Watchdog Timer+ 15/16-Bit Timer_A3 3 CC Reg 1 Interrupt Vector POR Brownout , Functions TERMINAL NAME TDO/TDI TDI/TCLK TMS TCK RST/NMI DVCC DVSS XIN XOUT AVSS AVCC VREF P6.0/A0+ P6.1/A0


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PDF MSP430F42x0 SLAS455C 16-Bit 125-ns 12-Bit
BGA153

Abstract: CQ 34 TC55YK1618XB-666 153-bump
Text: TMS TDI TCK TDO TRST vddq Vss AO to A19 Address Inputs 1/01 to 1/018 Data Inputs/Outputs VREF Reference Voltage Input CK, CK Differential Clock Inputs B1,B2, B3 Control Inputs CQ, CQ Differential , TMS , TDI, TCK, TDO, TRST Boundary Scan Test Access Ports /The information contained herein is subject , Reference Voltage Input for input buffers. The inputs must be tied together. 5G, 5H CK,CK Differential Input Differential Reference Clock for both input and output signals. CK clock input must be the


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PDF TC55YK1618XB-666 576-WORD 18-BIT TC55YK1618XB 368-bit BGA153-1422-1 BGA153 CQ 34 153-bump
bd-9b

Abstract: BGA153 3DA18 TC55YK1636XB-666 A1841
Text: I/036 A16 Vss AO Vss A3 1/01 I/02 Vss vddq TMS TDI TCK TDO TRST vddq Vss AO to A18 Address Inputs 1/01 to I/036 Data Inputs/Outputs VREF Reference Voltage Input CK, CK Differential Clock Inputs , ) Vddo Output Power Supply (1.5 V) Vss Ground NC No Connection TMS , TDI, TCK, TDO, TRST Boundary Scan , edge of CK). 5E, 5N VREF Input Reference Voltage Input for input buffers. The inputs must be tied together. 5G, 5H CK,CK Differential Input Differential Reference Clock for both input and output signals


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PDF TC55YK1636XB-666 288-WORD 36-BIT TC55YK1636XB 368-bit BGA153-1422-1 bd-9b BGA153 3DA18 A1841
Not Available

Abstract: No abstract text available
Text: AO to A18 Address Inputs Data Inputs /Outputs Reference Voltage Input Differential Clock Inputs , /010 Vss I/01 to 1/036 VREF CK, CK B1.B2, B3 CQ2, CQ2 G ZQ LBÖ V dd V ddo Vss NC TMS , TDI, TCK, TDO , dd Vss A15 Vss CQ2 V ddq 1/034 V ddq 1/036 V ddo I/033 Vss CQ1 v ddq NC V dd A16 TMS , registered on the rising edge of CK (the falling edge of CK). Reference Voltage Input for input buffers , Input 5G, 5H CK,CK Differential Input Differential Reference Clock for both input and output


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PDF TC55YK1636X6-666 TC55YK1636XB 368-bit BGA153-1422-1 TC55YK1636XB-666
2001 - CXK77P36L80GB-4A

Abstract: CXK77P36R80GB CXK77P36R80GB-33 CXK77P36R80GB-4A
Text: K/K cross V Output Reference Level 0.75 V Output Load Conditions RQ = 250 See , ) for TCK, TMS , TDI 2. Modified DC Recommended Operating Conditions (p. 6). Removed Clock Input Cross , interface with dedicated input reference voltage (VREF): 0.75V typical · Register - Register (R-R) read , VDDQ TMS TDI TCK TDO RSVD (3) VDDQ Notes: 1. Pad Locations 2T and 6T are true , Input Reference Voltage - Input buffer threshold voltage. VSS Ground TCK Input JTAG Clock


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PDF CXK77P36R80GB CXK77P36R80GB 200mV -100uA CXK77P36L80GB-4A CXK77P36R80GB-33 CXK77P36R80GB-4A
2006 - ADC10AE0

Abstract: ADC10AE1 MSP430F227x MSP430x22x2 device pinout, DA package
Text: integrated reference and data transfer controller (DTC), two general purpose operational amplifiers in the , With Internal Reference , Sample-and-Hold, Autoscan, and Data Transfer Controller D D D , 22 21 20 P1.7/TA 2/TDO /TDI P1.6/TA 1/TDI P1.5/TA 0/ TMS P1.4/SMCLK /TCK P1.3/TA 2 P1.2/TA 1 P1.1/TA 0 , 31 30 29 28 27 26 25 24 23 22 21 20 P1.7/TA 2/TDO /TDI P1.6/TA 1/TDI P1.5/TA 0/ TMS P1.4/SMCLK /TCK P1 , .6/TA1/TDI/TCLK P1.7/TA2/TDO/TDI P1.4/SMCLK/TCK TEST/SBWTCK P1.5/TA0/ TMS P2.5/Rosc P1.3/TA2


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PDF MSP430x22x2, MSP430x22x4 SLAS504 MSP430F2232: MSP430F2252: MSP430F2272: MSP430F2234: MSP430F2254: MSP430F2274: ADC10AE0 ADC10AE1 MSP430F227x MSP430x22x2 device pinout, DA package
2005 - Not Available

Abstract: No abstract text available
Text: Internal Reference and Five Differential Analog Inputs 12-Bit D/A Converter 16-Bit Timer_A With Three , ) TDO/TDI TDI/TCLK TMS TCK RST/NMI DVCC DVSS XIN XOUT AVSS AVCC VREF P6.0/A0+ P6.1/A0- P6.2/A1+ P6.3/A1 , · DALLAS, TEXAS 75265 COM0 DVCC TMS TCK 3 MSP430F42x0 MIXED SIGNAL , TMS TCK TDI/TCLK TDO/TDI Watchdog Timer+ 15/16-Bit Timer_A3 3 CC Reg 1 Interrupt Vector POR Brownout , Functions TERMINAL NAME TDO/TDI TDI/TCLK TMS TCK RST/NMI DVCC DVSS XIN XOUT AVSS AVCC VREF P6.0/A0+ P6.1/A0


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PDF MSP430F42x0 SLAS455C 16-Bit 125-ns 12-Bit
2005 - SD16UNI

Abstract: No abstract text available
Text: Internal Reference and Five Differential Analog Inputs 12-Bit D/A Converter 16-Bit Timer_A With Three , ) TDO/TDI TDI/TCLK TMS TCK RST/NMI DVCC DVSS XIN XOUT AVSS AVCC VREF P6.0/A0+ P6.1/A0- P6.2/A1+ P6.3/A1 , · DALLAS, TEXAS 75265 COM0 DVCC TMS TCK 3 MSP430F42x0 MIXED SIGNAL , TMS TCK TDI/TCLK TDO/TDI Watchdog Timer+ 15/16-Bit Timer_A3 3 CC Reg 1 Interrupt Vector POR Brownout , Functions TERMINAL NAME TDO/TDI TDI/TCLK TMS TCK RST/NMI DVCC DVSS XIN XOUT AVSS AVCC VREF P6.0/A0+ P6.1/A0


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PDF MSP430F42x0 SLAS455C 16-Bit 125-ns 12-Bit SD16UNI
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