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3621D101KT (1676955-2) TE Connectivity (1676955-2) 3621D 100UH 10%
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2010 - MSC8156

Abstract: DDR3 timing MT41J64M16BLA-15E MSC8156 datasheet MICRON ddr3 MT41J64M16 MT41J64M16 S25FL128P 0x01801 DDR3 layout samtec PCIE
Text: Signal EE0 Direct connection to HSC I Connected to test point TMS I Direct connection , Configuration Word Control 3.6.2.1 Loading Reset Configuration Word from External I2C When the load RCW , 2.5 UART_RXD_GPIO28 91 B 2.5 TMS 92 B 2.5 PORST_B 93 B 2.5


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PDF MSC8156MDDS MSC8156 DDR3 timing MT41J64M16BLA-15E MSC8156 datasheet MICRON ddr3 MT41J64M16 MT41J64M16 S25FL128P 0x01801 DDR3 layout samtec PCIE
2000 - CPLD ISP

Abstract: XAPP326 programming for embedded systems
Text: 1 0 Note: 1 or 0 are values of TMS at each transition. Figure 1: IEEE 1149.1 JTAG TAP , CPLD Event Description Programmer Action Test-Logic/Reset BEGIN BEGIN loop0 TMS = 1, TCK = Test-Logic/Reset Ensure device in TestLogic/Reset State Loop five times 1 TMS = 0, TCK = Run-Test/Idle 2 TMS = 1, TCK = Select DR-Scan 3 TMS = 1, TCK = Select IR-Scan 4 TMS = 0, TCK = Capture-IR 5 TMS = 0, TCK = Shift-IR loop1 TMS


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PDF XAPP326 CPLD ISP XAPP326 programming for embedded systems
1996 - Not Available

Abstract: No abstract text available
Text: Division, Gated-TCK, and Free-Running-TCK Modes Discrete TAP Control Mode Supports Arbitrary TMS /TDI , 24 23 22 21 20 19 18 17 16 15 14 13 A0 A1 A2 RDY TDO VCC TCK TMS TRST TDI RST TOE SN54LVT8980 . , 28 27 26 25 24 23 22 21 20 19 11 12 13 14 15 16 17 18 RDY TDO VCC NC TCK TMS TRST NC ­ No , serial test bus ­ test clock (TCK), test mode select ( TMS ), test data input (TDI), test data output (TDO , connected, the TMS , TDI, and TDO signals can be connected to distant target IEEE Std 1149.1 devices via a


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PDF SN54LVT8980, SN74LVT8980 SCBS676D
1996 - TMS 1100

Abstract: LVT8990 LVT8980 SN54LVT8980 SN74LVT8980 scbs676b
Text: 17 9 16 10 15 11 14 12 13 A0 A1 A2 RDY TDO VCC TCK TMS TRST TDI , Arbitrary TMS /TDI Sequences for Non-Compliant Targets Programmable 32-Bit Test Cycle Counter Allows , 19 12 13 14 15 16 17 18 RDY TDO VCC NC TCK TMS TRST D6 D7 CLKIN NC TOE RST TDI , test bus ­ test clock (TCK), test mode select ( TMS ), test data input (TDI), test data output (TDO , connected, the TMS , TDI, and TDO signals can be connected to distant target IEEE Std 1149.1 devices via a


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PDF SN54LVT8980, SN74LVT8980 SCBS676B SN54LVT8980 TMS 1100 LVT8990 LVT8980 SN54LVT8980 SN74LVT8980 scbs676b
2002 - TMS 1100

Abstract: SN54LVT8980A SN74LVT8980A SN74LVT8980ADW SN74LVT8980ADWR SNJ54LVT8980AFK SNJ54LVT8980AJT SNJ54LVT8980AW
Text: A1 A2 RDY TDO VCC TCK TMS TRST TDI RST TOE SN54LVT8980A . . . FK PACKAGE (TOP VIEW , Arbitrary TMS /TDI Sequences for Noncompliant Targets Programmable 32-Bit Test Cycle Counter Allows , TCK TMS TRST D6 D7 CLKIN NC TOE RST TDI D Members of Texas Instruments Broad NC - No , : test clock (TCK), test mode select ( TMS ), test data input (TDI), test data output (TDO), and test , TMS , TDI, and TDO signals can be connected to distant target IEEE Std 1149.1 devices via a pipeline


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PDF SN54LVT8980A, SN74LVT8980A SCBS755B SN54LVT8980A TMS 1100 SN54LVT8980A SN74LVT8980A SN74LVT8980ADW SN74LVT8980ADWR SNJ54LVT8980AFK SNJ54LVT8980AJT SNJ54LVT8980AW
2003 - Not Available

Abstract: No abstract text available
Text: Discrete TAP Control Mode Supports Arbitrary TMS /TDI Sequences for Noncompliant Targets Programmable 32 , 14 13 A0 A1 A2 RDY TDO VCC TCK TMS TRST TDI RST TOE description/ordering information The , -wire IEEE Std 1149.1 serial test bus: test clock (TCK), test mode select ( TMS ), test data input (TDI), test , directly connected, the TMS , TDI, and TDO signals can be connected to distant target IEEE Std 1149.1 , eTBCs to generate the TMS sequences necessary to move the test bus from any stable TAP-controller state


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PDF SN74LVT8980AEP SCBS761A
2002 - SN54LVT8980A

Abstract: SN74LVT8980A SN74LVT8980ADW SN74LVT8980ADWR SNJ54LVT8980AFK SNJ54LVT8980AJT SNJ54LVT8980AW
Text: TCK TMS TRST TDI RST TOE SN54LVT8980A . . . FK PACKAGE (TOP VIEW) D0 R/W STRB NC A0 , TAP Control Mode Supports Arbitrary TMS /TDI Sequences for Noncompliant Targets Programmable 32 , 20 19 11 12 13 14 15 16 17 18 RDY TDO VCC NC TCK TMS TRST D6 D7 CLKIN NC TOE , -wire IEEE Std 1149.1 serial test bus: test clock (TCK), test mode select ( TMS ), test data input (TDI), test , directly connected, the TMS , TDI, and TDO signals can be connected to distant target IEEE Std 1149.1


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PDF SN54LVT8980A, SN74LVT8980A SCBS755A SN54LVT8980A SN54LVT8980A SN74LVT8980A SN74LVT8980ADW SN74LVT8980ADWR SNJ54LVT8980AFK SNJ54LVT8980AJT SNJ54LVT8980AW
2002 - Not Available

Abstract: No abstract text available
Text: Modes Discrete TAP Control Mode Supports Arbitrary TMS /TDI Sequences for Noncompliant Targets , TMS TRST TDI RST TOE SN54LVT8980A . . . FK PACKAGE (TOP VIEW) D1 D2 D3 NC GND D4 D5 5 6 7 8 9 10 4 3 2 1 28 27 26 25 24 23 22 21 20 19 11 12 13 14 15 16 17 18 RDY TDO VCC NC TCK TMS , 4- or 5-wire IEEE Std 1149.1 serial test bus: test clock (TCK), test mode select ( TMS ), test data , . However, as well as being directly connected, the TMS , TDI, and TDO signals can be connected to distant


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PDF SN54LVT8980A, SN74LVT8980A SCBS755
2002 - Not Available

Abstract: No abstract text available
Text: A1 A2 RDY TDO VCC TCK TMS TRST TDI RST TOE SN54LVT8980A . . . FK PACKAGE (TOP VIEW , Arbitrary TMS /TDI Sequences for Noncompliant Targets Programmable 32-Bit Test Cycle Counter Allows , TCK TMS TRST D6 D7 CLKIN NC TOE RST TDI D Members of Texas Instruments Broad NC - No , : test clock (TCK), test mode select ( TMS ), test data input (TDI), test data output (TDO), and test , TMS , TDI, and TDO signals can be connected to distant target IEEE Std 1149.1 devices via a pipeline


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PDF SN54LVT8980A, SN74LVT8980A SCBS755B SN54LVT8980A
TMS9981

Abstract: tms9900 tw 9907 SN74148 ST12 ST15 Scans-0011652 tms 9980 processor
Text:  TMS 9980A/ TMS 9981 Product Data Book TMS 9980A/9981 INTRODUCTION 1. INTRODUCTION 1.1 DESCRIPTION The TMS 9980A/ TMS 9981 is a software-compatible member of Tl's 9900 family of microprocessors. Designed to minimize the system cost for smaller systems, the TMS 9980A/ TMS 9981 is a single-chip 16 , -pin package (see Figure 1). The instruction set of the TMS 9980A/ TMS 9981 includes the capabilities offered by , Instruments provides a compatible set of MOS and TTL memory and logic function circuits to be used with a TMS


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PDF 980A/9981 980A/TMS 16-bit 40-pin 200pf tw-10 tw-20 TMS9981 tms9900 tw 9907 SN74148 ST12 ST15 Scans-0011652 tms 9980 processor
2003 - Not Available

Abstract: No abstract text available
Text: Mode Supports Arbitrary TMS /TDI Sequences for Noncompliant Targets Programmable 32-Bit Test Cycle , TCK TMS TRST TDI RST TOE description/ordering information The SN74LVT8980A embedded test-bus , select ( TMS ), test data input (TDI), test data output (TDO), and test reset (TRST). All such signals can , logic or buffering. However, as well as being directly connected, the TMS , TDI, and TDO signals can be , TMS sequences necessary to move the test bus from any stable TAP-controller state to any other such


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PDF SN74LVT8980AÄ SCBS761A
2003 - Not Available

Abstract: No abstract text available
Text: Discrete TAP Control Mode Supports Arbitrary TMS /TDI Sequences for Noncompliant Targets Programmable 32 , 14 13 A0 A1 A2 RDY TDO VCC TCK TMS TRST TDI RST TOE description/ordering information The , -wire IEEE Std 1149.1 serial test bus: test clock (TCK), test mode select ( TMS ), test data input (TDI), test , directly connected, the TMS , TDI, and TDO signals can be connected to distant target IEEE Std 1149.1 , eTBCs to generate the TMS sequences necessary to move the test bus from any stable TAP-controller state


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PDF SN74LVT8980AEP SCBS761A
2532 eprom

Abstract: 25l32 eprom 2532 MA 25L32 tms 2532 jl 2532 2532 eprom texas TMS2532 2532 rom TMS4732
Text: MOS LSI 32.768-BIT ERASABLE TMS 2532-30 JL, TMS 2532-35 JL, TMS 2532-45 JL. TMS 25L32-45 JL , €¢ Max Access/Min Cycle Time: TMS 2532-30 300 ns TMS 2532-35 350 ns TMS 2532-45 450 ns TMS 25L32-45 , Technology • 3-State Output Buffers • 40% Lower Power TMS 25L32 . . . 500 mW Max Active TMS 2532 . . . , description The TMS 2532 series ( TMS 2532-30 JL, TMS 2532-35 JL, TMS 2532-45 JL, and TMS 25L32-45 JL) are 32 , TMS 2532 series are plug-in compatible with the TMS 4732 32K ROM. The devices are offered in a


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PDF 768-BIT 25L32-45 1979-REVISED 25L32 2532 eprom 25l32 eprom 2532 MA 25L32 tms 2532 jl 2532 2532 eprom texas TMS2532 2532 rom TMS4732
2003 - SN74LVT8980A

Abstract: SN74LVT8980AIDWREP
Text: TMS /TDI Sequences for Noncompliant Targets Programmable 32-Bit Test Cycle Counter Allows Virtually , 8 17 9 16 10 15 11 14 12 13 A0 A1 A2 RDY TDO VCC TCK TMS TRST , support one 4- or 5-wire IEEE Std 1149.1 serial test bus: test clock (TCK), test mode select ( TMS ), test , . However, as well as being directly connected, the TMS , TDI, and TDO signals can be connected to distant , issued by the host to cause the eTBCs to generate the TMS sequences necessary to move the test bus from


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PDF SN74LVT8980AEP SCBS761A SN74LVT8980A SN74LVT8980AIDWREP
1995 - Not Available

Abstract: No abstract text available
Text: Modes Discrete TAP Control Mode Supports Arbitrary TMS /TDI Sequences for Noncompliant Targets , 14 13 A0 A1 A2 RDY TDO VCC TCK TMS TRST TDI RST TOE description/ordering information The , -wire IEEE Std 1149.1 serial test bus: test clock (TCK), test mode select ( TMS ), test data input (TDI), test , directly connected, the TMS , TDI, and TDO signals can be connected to distant target IEEE Std 1149.1 , eTBCs to generate the TMS sequences necessary to move the test bus from any stable TAP-controller state


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PDF SN74LVT8980A-EP SCBS761
tms 99000

Abstract: TMS99000 tms99105 TIM99610 7m 0880 TMS 8560 source code for park and clark transformation 99120 TMS 1100 8086 microprocessor is called parallel processor
Text: TEXAS INSTR -CUC/UPÏ 45 TMS 99000 SYSTEM BRIEF • " T-4-Q-DËj flit, 172 2 OPSTìl? 7 A THIRD GENERATION OF MICROPROCESSOR COMPONENTS, SOFTWARE, AND SUPPORT jjLrl6; The new TMS 99000 , represents true third generation features and performance. The TMS 99000 is a third generation descendent of the TMS 99000 16-bit microprocessor, sharing the same advanced memory-to-memory architecture of the TMS 9900. With TMS 99000 instruction set as a superset of the TMS 9900, full object code compatibility


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PDF 16-bit tms 99000 TMS99000 tms99105 TIM99610 7m 0880 TMS 8560 source code for park and clark transformation 99120 TMS 1100 8086 microprocessor is called parallel processor
eprom 2516

Abstract: 2516 eprom 2516 eprom texas TMS2516 2516-35 tms4016 2516 ansi y32 2516-45
Text: MOS LSI TMS 2516-25 JL. TMS 2516-35 JL AND TMS 2516-45 JL 16,384-BIT ERASABLE PROGRAMMABLE , Access/Min Cycle Time - TMS 2516-25 . . . 250 ns - TMS 2516-35 . . . 350 ns - TMS 2516-45 . . . 450 ns , • No Pull-Up Resistors Required Vpp +25 V Power Supply vSs 0 V Ground description The TMS 2516 , bus. The TMS 2516 is plug-in compatible with the TMS 401 6 1 6K static RAM. It is offered in a , seconds. Texas Instruments INCORPORATED POST OFFICE BOX 225012 • DALLAS, TEXAS 75265 TMS 2516-25 JL


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PDF 384-BIT 1979-REVISED 24-PIN eprom 2516 2516 eprom 2516 eprom texas TMS2516 2516-35 tms4016 2516 ansi y32 2516-45
40L45

Abstract: 40L47-45 40L47 Telect 18-PIN 40L45-45 40L45-30
Text: MOS LSI TMS 40L4S JL. NL; TMS 40L47 JL. N| 1024-WQRD BY 4-BIT STATIC RAMi NOV EM Bf n 1177 , Fully Static Operation (No Clocks, No Refresh, No Timing Strobe) 3 Performance Ranges: TMS 40L45-25, TMS 40L47 25 TMS 40L45-30, TMS 40L47 30 TMS 40L45-45, TMS 40L47-45 ACCESS TIME (MAX) 250 ns 300 ns , Power Dissipation 250 mW * Typical 370 mW 'Maximum Standby Power Dissipation ( TMS 40L47) 12 mW Typical , required. The TMS 40L45/40L47 series is manufactured using Tl's reliable N channel silicon-gate technology


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PDF 40L4S 40L47 1024-WQRD 300-mil 20-Pin 40L45-25, 40L45-30, 40L45-45, 40L45 40L47-45 Telect 18-PIN 40L45-45 40L45-30
1997 - TMS 1100

Abstract: Tms 1000 SN54LVT8980A SN74LVT8980A LVT8980A
Text: TCK TMS TRST TDI RST TOFF SN54LVT8980A . . . FK PACKAGE (TOP VIEW) PRODUCT PREVIEW D , Arbitrary TMS /TDI Sequences for Non-Compliant Targets Programmable 32-Bit Test Cycle Counter Allows , 19 11 12 13 14 15 16 17 18 RDY TDO VCC NC TCK TMS TRST D6 D7 CLKIN NC TOFF RST , test clock (TCK), test mode select ( TMS ), test data input (TDI), test data output (TDO), and test , TMS , TDI, and TDO signals can be connected to distant-target IEEE Std 1149.1 devices via a pipeline


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PDF SN54LVT8980A, SN74LVT8980A SCBS695 SN54LVT8980A TMS 1100 Tms 1000 SN54LVT8980A SN74LVT8980A LVT8980A
2002 - Not Available

Abstract: No abstract text available
Text: Free-Running-TCK Modes Discrete TAP Control Mode Supports Arbitrary TMS /TDI Sequences for Noncompliant Targets , A0 A1 A2 RDY TDO VCC TCK TMS TRST TDI RST TOE SN54LVT8980A . . . FK PACKAGE (TOP VIEW) D1 D2 D3 , 14 15 16 17 18 RDY TDO VCC NC TCK TMS TRST NC - No internal connection description The , support one 4- or 5-wire IEEE Std 1149.1 serial test bus: test clock (TCK), test mode select ( TMS ), test , . However, as well as being directly connected, the TMS , TDI, and TDO signals can be connected to distant


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PDF SN54LVT8980A, SN74LVT8980A SCBS755B
TMS9995

Abstract: tms9900 Each TMS 9995 system 32768-bit ST15 ST13 ST12 ST11 ST10 0C16
Text:  TMS 9995 16-Bit Microcomputer Data Manual TABLE OF CONTENTS 1. INTRODUCTION , .1 2.2 TMS 9995 Organization , .5 2.3 TMS 9995 interfaces .8 2.3.1 TMS 9995 Memory Interface .8 2.3.2 TMS 9995 Interrupts


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PDF 16-Bit IN916 IN3064 TMS9995 tms9900 Each TMS 9995 system 32768-bit ST15 ST13 ST12 ST11 ST10 0C16
2003 - SN54LVT8980A

Abstract: SN74LVT8980A SN74LVT8980A-EP SN74LVT8980AIDWREP DSP TEXAS JTAG
Text: TMS /TDI Sequences for Noncompliant Targets Programmable 32-Bit Test Cycle Counter Allows Virtually , 8 17 9 16 10 15 11 14 12 13 A0 A1 A2 RDY TDO VCC TCK TMS TRST , support one 4- or 5-wire IEEE Std 1149.1 serial test bus: test clock (TCK), test mode select ( TMS ), test , . However, as well as being directly connected, the TMS , TDI, and TDO signals can be connected to distant , issued by the host to cause the eTBCs to generate the TMS sequences necessary to move the test bus from


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PDF SN74LVT8980AEP SCBS761A SN54LVT8980A SN74LVT8980A SN74LVT8980A-EP SN74LVT8980AIDWREP DSP TEXAS JTAG
2003 - Not Available

Abstract: No abstract text available
Text: Discrete TAP Control Mode Supports Arbitrary TMS /TDI Sequences for Noncompliant Targets Programmable 32 , 14 13 A0 A1 A2 RDY TDO VCC TCK TMS TRST TDI RST TOE description/ordering information The , -wire IEEE Std 1149.1 serial test bus: test clock (TCK), test mode select ( TMS ), test data input (TDI), test , directly connected, the TMS , TDI, and TDO signals can be connected to distant target IEEE Std 1149.1 , eTBCs to generate the TMS sequences necessary to move the test bus from any stable TAP-controller state


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PDF SN74LVT8980AEP SCBS761A
2003 - Not Available

Abstract: No abstract text available
Text: Discrete TAP Control Mode Supports Arbitrary TMS /TDI Sequences for Noncompliant Targets Programmable 32 , 14 13 A0 A1 A2 RDY TDO VCC TCK TMS TRST TDI RST TOE description/ordering information The , -wire IEEE Std 1149.1 serial test bus: test clock (TCK), test mode select ( TMS ), test data input (TDI), test , directly connected, the TMS , TDI, and TDO signals can be connected to distant target IEEE Std 1149.1 , eTBCs to generate the TMS sequences necessary to move the test bus from any stable TAP-controller state


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PDF SN74LVT8980AEP SCBS761A
2003 - Not Available

Abstract: No abstract text available
Text: Mode Supports Arbitrary TMS /TDI Sequences for Noncompliant Targets Programmable 32-Bit Test Cycle , TCK TMS TRST TDI RST TOE description/ordering information The SN74LVT8980A embedded test-bus , select ( TMS ), test data input (TDI), test data output (TDO), and test reset (TRST). All such signals can , logic or buffering. However, as well as being directly connected, the TMS , TDI, and TDO signals can be , TMS sequences necessary to move the test bus from any stable TAP-controller state to any other such


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PDF SN74LVT8980AÄ SCBS761A
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